CN116401992A

CN116401992A - Node routing path optimization method and device

Info

Publication number: CN116401992A
Application number: CN202310551444.3A
Authority: CN
Inventors: 万鹭; 张吉锋; 邵中尉
Original assignee: Shanghai Sierxin Technology Co ltd
Current assignee: Shanghai Sierxin Technology Co ltd
Priority date: 2023-05-16
Filing date: 2023-05-16
Publication date: 2023-07-07

Abstract

The application provides a node routing path optimization method and device, and relates to the technical field of integrated circuits and computer aided design. The node routing path optimization method comprises the following steps: preprocessing FPGA wiring data, and updating weights of all connecting lines and a weight table of FPGA interconnection; initial segmentation is carried out by taking the minimum segmentation size as a segmentation target, and a segmentation result is obtained; and updating the weight table of the FPGA interconnection again according to the segmentation result, optimizing the wiring path, optimizing the segmentation result to a greater extent, and greatly improving the system performance.

Description

Node routing path optimization method and device

Technical Field

The present disclosure relates to the field of integrated circuits and computer aided design technologies, and in particular, to a method and an apparatus for optimizing a node routing path.

Background

The large-scale design requires a plurality of Field Programmable Gate Arrays (FPGAs) to be interconnected to accommodate and verify, and the FPGA prototype verification system supports partitioning of the large-scale design. In the system in the prior art, because the number of physical connection lines of the FPGA is limited, not all the FPGAs can be mutually communicated in pairs, which may cause bad segmentation results and greatly reduced system performance.

Disclosure of Invention

In view of this, the embodiment of the present disclosure provides a method and an apparatus for optimizing a node routing path, which optimize the segmentation result to a greater extent and greatly improve the system performance.

The embodiment of the specification provides the following technical scheme:

in one aspect, a method for optimizing a node routing path is provided, including:

preprocessing FPGA wiring data, and updating weights of all connecting lines and a weight table of FPGA interconnection;

initial segmentation is carried out by taking the minimum segmentation size as a segmentation target, and a segmentation result is obtained;

and updating the weight table of the FPGA interconnection again according to the segmentation result, and optimizing the wiring path.

In some embodiments, prior to preprocessing the FPGA routing data, the method further comprises:

reading in the FPGA wiring data and carrying out grammar analysis, and reading in user-defined grouping information, node information, original design module name information corresponding to each node, network connection information between nodes and pre-specified division standard information, wherein the node information at least comprises the number of resources occupied by each node and trigger device or clock device information of each node.

In some embodiments, preprocessing the FPGA routing data, updating weights of all wires and weight tables of FPGA interconnects, including:

and updating the weight of all the connecting lines according to the node attribute information, and giving a preset weight value to the connecting lines when the driving nodes of the connecting lines are trigger devices, clock devices or have a preset number of load nodes, wherein the preset weight value is higher than that of the connecting lines of which the driving nodes are non-trigger devices, non-clock devices or do not reach the preset number of load nodes.

In some embodiments, the initial segmentation with a segmentation minimum segmentation size as a segmentation target comprises:

and successively dividing according to the sequence from small to large of the weights of the connecting lines, and dividing by taking the cutting minimum number of the connecting lines as an objective function, wherein the minimum number of the connecting lines is the number of the connecting lines with the shortest routing paths between two nodes.

In some embodiments, after updating the weights of all the wires and the weight table of the FPGA interconnection, the method further includes:

and carrying out cluster merging on the updated node parts, and restoring the nodes merged in the clustering process after the initial segmentation.

In some embodiments, updating the weight table of FPGA interconnection again according to the segmentation result, optimizing the routing path includes:

according to the segmentation result, the connection lines crossing the FPGA are classified into a first type connection line and a second type connection line, wherein the first type connection line is an interconnection line which is directly connected between the crossing FPGAs, and the second type connection line is an interconnection line which is not directly connected between the crossing FPGAs;

fixing the FPGA interconnection lines used by the first type of connection lines, and updating a weight table of the FPGA interconnection according to wiring conditions;

and sequencing the second class of connection lines, executing a routing path optimization algorithm on each path based on the sequencing result, and updating a weight table of FPGA interconnection according to the optimization result.

In some embodiments, ordering the second class of links includes:

and calculating the measurement value of each second type of connection line based on the number of the FPGA of the driving node and the load node, the shortest path length of the FPGA series connection of the driving node and the load node, the shortest path length between each load node and the driving node and the weight of the FPGA interconnection line through which the shortest path between each load node and the driving node passes, and sequencing according to the measurement value of each second type of connection line.

In some embodiments, performing a routing path optimization algorithm on each path based on the ordering result, and updating the weight table of the FPGA interconnect according to the optimization result, including:

s1: setting an FPGA where a driving node of a target connecting line to be routed is located as an initial FPGA, and recording the initial FPGA as Fs; setting an FPGA where a load node of a target connection line to be routed is located as a target FPGA;

s2: adding Fs into the vertex set, and calculating the shortest path length from Fs to other FPGAs, wherein no path is expressed as ++;

s3: selecting the vertex Fi with the shortest path length in the step S2, adding the vertex Fi into the vertex set, and updating the shortest paths from the current Fs to other vertexes;

s4: repeating the step S2, selecting the node with the shortest path length of the previous step each time to add into the vertex set, and updating Fs to the shortest paths of other vertexes until a target FPGA is newly added in the vertex set;

s5: setting the interconnection weight value on the shortest path obtained in the step S4 to be 0, and adding the FPGA passing through the path into an initial FPGA set;

s6: repeating the steps S2 to S4 until a target FPGA is newly added in the vertex set;

s7: repeating the steps S5 to S6 until all the target FPGAs are traversed;

s8: and updating the weight table of the FPGA interconnection according to the route path optimization result.

In some embodiments, the method further comprises:

based on the routing result obtained in step S8, the longest routing path is obtained and optimized and improved.

In another aspect, a node routing path optimization apparatus according to any one of the above embodiments is provided, including:

the preprocessing module is used for preprocessing the FPGA wiring data and updating weights of all connecting lines and weight tables of FPGA interconnection;

the segmentation module is used for carrying out initial segmentation by taking the minimum segmentation size as a segmentation target to obtain a segmentation result;

and the path optimization module is used for updating the weight table of the FPGA interconnection again according to the segmentation result and optimizing the wiring path.

Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:

the range of placing the FPGA is not limited when the large-scale design is distinguished, so that the condition of no solution is avoided, and the segmentation result can reach the optimal solution or the better solution because the least net number is used as the objective function for segmentation during segmentation; under the condition that two FPGAs which are not directly connected or are occupied in interconnection lines have communication requirements, under the condition that the module layout and the FPGA connection lines are fixed, the most suitable route path is sought, and even if signals are transferred and transmitted through other FPGAs, the performance of system degradation can be greatly reduced, namely the system performance is greatly improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is an example of the connection relationship of a large design in prior art scenario 1;

FIG. 2 is an FPGA interconnect example of a large design in prior art scenario 1;

fig. 3 to 6 are route path examples of prior art scheme 2;

fig. 7 is a schematic flow chart of a node routing path optimization method provided in an embodiment of the present application;

FIG. 8 is a flow chart of a method for optimizing a node routing path according to a preferred embodiment of the present application;

FIG. 9 is an exemplary flow chart for updating the weight table of the FPGA interconnect according to a routing path optimization algorithm;

FIGS. 10-11 are examples of maze search routing when performing a routing path optimization algorithm;

fig. 12 is a schematic structural diagram of a node routing path optimization device according to an embodiment of the present application.

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.

In view of this, the inventors have conducted intensive studies and improved searches on various approaches to circumvent the limitation of the physical connection between FPGAs, and found that:

scheme 1: when partitioning, the range of placing the FPGA is limited for the module with communication, and the module is placed on the same FPGA or two FPGAs with interconnection lines respectively, so that the mode has the situations of no solution and poor solution for complex large-scale design. For example, with a common problem scenario, when the connection relationship of a large-scale design is shown in fig. 1, and the interconnection condition between FPGA devices is shown in fig. 2, if the A, B, C, D module occupies a large resource, and two modules cannot be placed on the same FPGA, the design has no feasible solution.

Scheme 2: under the condition that no direct interconnection exists or communication requirements exist between two FPGAs with occupied interconnection lines, signals are transferred and transmitted through other FPGAs, the situation that the signal routing path is overlong often occurs in the mode, and because the time delay of the signal transmission of the interconnection lines between the FPGAs is far longer than the time delay of the signal transmission inside the FPGAs, when the communication between the two modules in the design needs to be transmitted through a plurality of FPGAs in a routing way, the accuracy of a transmission result is guaranteed by adopting a mode of reducing the system frequency by the FPGA prototype verification system, and the overall performance of the system is greatly reduced.

Common problem scenarios are as follows: in the case of FPGA interconnection shown in fig. 3, since there is no interconnection line directly connecting F1 and F6, when there is a communication requirement between F1 and F6, signals need to be transferred by other FPGAs.

a) When the routing path is F1- > F4- > F5- > F2- > F3- > F6 (as shown in figure 4), the number of transit FPGAs is 4; when the routing path is F1- > F4- > F5- > F6 (as shown in fig. 5), the number of transit FPGAs is 2; obviously, the delay of the transmission of the first routing path across the FPGA is 2 more than that of the transmission of the second routing path across the FPGA, so that the overall performance of the system is lower.

b) When the routing paths are F1- > F2- > F3- > F6 (as shown in fig. 6) and the routing paths are F1- > F4- > F5- > F6 (as shown in fig. 5), the number of the transferred FPGAs is 2, if the signal quantity transmitted by the interconnection line between F1 and F2 is far greater than the signal quantity transmitted by the interconnection line between F1 and F4 (assuming that the signal quantity transmitted by the interconnection line between the rest FPGAs is equal), that is, the signal transmission rate between F1 and F2 is smaller than the signal transmission rate between F1 and F4, it is obvious that the first routing path has longer transmission delay than the second routing path, and the overall performance of the system is lower.

Based on this, the embodiment of the present specification proposes a processing scheme: the reduced performance of the system under the above conditions is greatly alleviated, mainly by adjusting the module layout. Specifically, when partitioning a large-scale design, the range of placing the FPGA is not limited for the module with communication, so as to solve the condition without solution; based on the maze search wiring concept, the segmentation is carried out by taking the number of the least cutting lines (net) as an objective function during segmentation, so as to achieve the segmentation results of better solutions and optimal solutions; under the condition that no direct interconnection exists or communication requirements exist between two FPGAs of which interconnection lines are occupied, signals are transferred and transmitted through other FPGAs, and under the condition that module layout and the FPGA connection lines are fixed, the best suitable routing path is sought, so that the performance of system degradation is greatly reduced.

The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

As shown in fig. 7, the node routing path optimization method provided in the embodiment of the present application mainly includes the following steps:

Fig. 8 shows a preferred embodiment of a node routing path optimization procedure. In some embodiments, before preprocessing the FPGA wiring data, the FPGA wiring data (i.e., user design for FPGA wiring) may be read in first and parsed, and user-defined grouping information, node information, primary design module name information corresponding to each node, network connection information between nodes, and pre-specified division standard information are read in, where the node information at least includes the number of resources occupied by each node, and trigger device or clock device information of each node. In some embodiments, the node information, the original design module name information corresponding to each node, the network connection information between the nodes, and the pre-specified division standard information may be four parts of information generated after the FPGA wiring data is read in.

In some embodiments, preprocessing the FPGA routing data, updating the weights of all the wires and the weight table of the FPGA interconnect may be implemented as follows:

Illustratively, in the preprocessing phase, the operation of updating the net weights is as follows: the system updates the weight of all the nets according to the node attribute information, gives the driving nodes a higher weight value for the nets of the trigger device and the clock device, and gives the nodes with more load higher weight values; the operation of updating the FPGA interconnection weight table is as follows: the system gives the connection weight value to the FPGA direct interconnection lines according to the number of the FPGA direct interconnection lines, and the weight is smaller as the number of the interconnection lines is larger.

In some embodiments, after updating the weights of all the links and the weight table of the FPGA interconnection, in order to reduce the magnitude of the segmentation as much as possible, further refinement operation of cluster merging may be performed on the updated node portions, and after the initial segmentation, the nodes merged in the clustering process may be restored. Specifically, in the restoration process, an attempt is made to move the restored node to another FPGA, and if the number of cut net pieces or the net with a smaller cut weight value can be reduced, the node is moved.

In some embodiments, initial segmentation with a segmentation minimum segmentation size (cutsize) as the segmentation target may be implemented as follows:

and performing sequential segmentation according to the sequence from small to large of the weights of the connecting lines, and performing segmentation by taking the least number of the connecting lines as an objective function, wherein the least number of the connecting lines is the number of the connecting lines with the shortest routing paths between two nodes.

In some embodiments, to achieve the purpose of optimizing the routing, the weight table of the FPGA interconnection may be updated again according to the segmentation result to optimize the routing path, which may be specifically implemented as the following procedures:

firstly, according to a segmentation result, classifying connection lines crossing the FPGA into a first type connection line and a second type connection line, wherein the first type connection line is an interconnection line crossing the FPGA and having direct connection, the second type connection line is an interconnection line crossing the FPGA and having no direct connection, and the second type connection line is exemplarily shown in a design diagram in FIG. 1, and is arranged in an FPGA matrix in FIG. 2, if A is arranged on F1, B, C is arranged on F2, D is arranged on F4, net (A- > B) and net (A- > C) are the first type net, and net (A- > D) is the second type net; the FPGA interconnection lines used by the first type of connection lines are fixed, and the weight table of the FPGA interconnection is updated according to the wiring condition, and referring to fig. 1 and fig. 2, the net (a- > B) and the net (a- > C) are exemplarily, the used FPGA interconnection lines are fixed, and the number of interconnection lines in the FPGA matrix shown in fig. 2 is assumed to be consistent, the initial weight values are all 1, and because the net (a- > B) weight is 1 and the net (a- > C) weight is 2, the net weight value born by the current F1- > F2 interconnection line is 3 after adding 1 and 2, and the net weight value born by the current F1- > F3, F2- > F4 and F3- > F4 interconnection lines is 0, so that the F1- > F2 interconnection line is given a higher weight value.

And secondly, sorting the second class of connection lines, executing a routing path optimization algorithm on each path based on the sorting result, and updating a weight table of FPGA interconnection according to the optimization result. In some embodiments, the second class of links may be ordered as follows, including: and calculating the measurement value of each second type of connection line based on the number of the FPGA of the driving node and the load node, the shortest path length of the FPGA series connection of the driving node and the load node, the shortest path length between each load node and the driving node and the weight of the FPGA interconnection line through which the shortest path between each load node and the driving node passes, and sequencing according to the measurement value of each second type of connection line. In some embodiments, the number of FPGAs of the driving node and the load node of each second type of connection line, the shortest path length of the serial connection of the driving node and the FPGA of the load node, the shortest path length between each load node and the driving node, and the weight of the FPGA interconnection line through which the shortest path between each load node and the driving node passes are all in positive correlation with the measurement value.

FIG. 9 is an exemplary flow chart for updating the weight table of the FPGA interconnect according to a routing path optimization algorithm. Fig. 10 to 11 are examples of an optimization manner of maze search wiring when the route path optimization algorithm is executed. In some embodiments, after the second class of connection lines are ordered, a routing path optimization algorithm is executed on each path based on the ordering result, and the weight table of the FPGA interconnection is updated according to the optimization result, which specifically includes the following flows (examples in conjunction with fig. 9 and 10 to 11):

s1: setting an FPGA where a driving node of a target connection line to be routed is located as a starting FPGA, and recording the starting FPGA as Fs, such as F1 in FIG. 10; setting an FPGA where a load node of a target connection line to be routed is located as a target FPGA;

s2: adding Fs into the vertex set, calculating the shortest path length from Fs to other FPGAs, no path is denoted +. the Distance (i.e., distance) from F1 (i.e., node F1) to F2 (i.e., node F2) is calculated to be 1, the Distance from F1 to F2 is calculated to be 1, and the Distance from F1 to F4 is calculated to be 2, so that the Distance from F1 to F2 is the shortest path length from F1 to other FPGAs;

s3: selecting the vertex Fi with the shortest path length in the step S2 (F2 shown in fig. 10) to be added into the vertex set, and then updating the current Fs to other shortest paths of all the vertices, wherein, for example, as shown in fig. 10, F1- > F2 paths are shortest, F2 is added into the vertex set, the vertex set is updated from { F1} to { F1, F2}, and the distances of the rest nodes to the vertex set are synchronously updated;

s4: repeating step S2, selecting the node with the shortest path length of the last step to add into the vertex set each time, updating Fs to other shortest paths of each vertex until a target FPGA is newly added in the vertex set, namely, by calculating that the distance from F1 to F4 is 2, the distance from F1 to F5 is 3, the distance from F1 to F3 is 10, the path length from F1 to F4 is shortest, so that F4 is added into the vertex set, the vertex set is updated from { F1, F2, F4}, and the shortest paths from F1 to other vertices F4, F5 and F3 are updated;

s5: setting the interconnection weight value on the shortest path obtained in the step S4 to 0, and exemplarily setting the interconnection weight of F1 and F2, the interconnection weight of F1 and F5, the interconnection weight of F5 and F6, and the interconnection weight of F6 and F3 on the shortest path from F1 to F3 to 0 as shown in fig. 11, and adding the FPGA through which the path passes to the initial FPGA set;

s7: repeating the steps S5 to S6 until all the target FPGAs are traversed;

In some embodiments, after updating the weight table of FPGA interconnection according to the routing path optimization result, the longest routing path is obtained and optimized and improved based on the routing result obtained in step S8.

In addition, as shown in fig. 12, some embodiments of the present application further provide a node route optimization device of the node route optimization method according to any one of the foregoing embodiments, where the device mainly includes a preprocessing module 11, a segmentation module 12, and a route optimization module 13. Specifically, the preprocessing module 11 is mainly used for preprocessing the wiring data of the FPGA, and updating weights of all the wires and weight tables of the FPGA interconnection; the segmentation module 12 is mainly used for carrying out initial segmentation by taking a segmentation minimum segmentation size as a segmentation target to obtain a segmentation result; the path optimization module 13 is mainly used for updating the weight table of the FPGA interconnection again according to the segmentation result, and optimizing the routing path.

It should be noted that, the node routing path optimization method and the device thereof in any of the above embodiments may be implemented by a corresponding system, electronic device or storage medium. In some embodiments, a system or electronic device implementing node routing path optimization may include a processor and a memory, the processor implementing the steps of the node routing path optimization method of any of the embodiments described above when executing a stored computer program. In some embodiments, a storage medium stores a computer program, wherein the computer program when executed by a processor implements the steps of the node routing path optimization method of any of the embodiments described above.

In some embodiments, a processor may process data and/or information obtained from other devices or system components. The processor may execute program instructions to perform one or more of the functions described herein based on such data, information, and/or processing results. In some embodiments, a processor may contain one or more sub-processing devices (e.g., single-core processing devices or multi-core processing devices). By way of example only, the processor may include a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), an Application Specific Instruction Processor (ASIP), a Graphics Processor (GPU), a Physical Processor (PPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), an editable logic circuit (PLD), a controller, a microcontroller unit, a Reduced Instruction Set Computer (RISC), a microprocessor, or the like, or any combination thereof.

In some embodiments, the processor may be implemented at a server or user terminal. In some embodiments, a server may be used to manage resources and process data and/or information from at least one component of the present system or an external data source (e.g., a radar device). The server may execute program instructions to perform one or more of the functions described herein based on such data, information, and/or processing results. In some embodiments, the server may be a single server or a group of servers. The server set may be centralized or distributed (e.g., the servers may be distributed systems), may be dedicated, or may be serviced concurrently by other devices or systems. In some embodiments, the server may be regional or remote. In some embodiments, the server may be implemented on a cloud platform or provided in a virtual manner. For example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-layer cloud, or the like, or any combination thereof. In some embodiments, a user terminal refers to one or more terminal devices or software used by a user. In some embodiments, any user, such as a person, business, etc., may be used with the user terminal. In some embodiments, the user terminal may be one or any combination of a mobile device, tablet computer, laptop computer, desktop computer, or other input and/or output enabled device. The above examples are only intended to illustrate the broad scope of the user terminal device and not to limit its scope.

In some embodiments, the processor is also communicatively coupled to the memory. The memory may be used to store data and/or instructions, such as computer programs. The memory may include one or more memory components, each of which may be a separate device or may be part of another device. In some embodiments, the memory may include Random Access Memory (RAM), read Only Memory (ROM), mass storage, removable memory, volatile read-write memory, and the like, or any combination thereof. By way of example, mass storage may include magnetic disks, optical disks, solid state disks, and the like. In some embodiments, the memory may be implemented on a cloud platform.

In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.

In summary, compared with the prior art, the node routing path optimization scheme provided by the embodiment of the application has at least the following beneficial effects:

the range of placing the FPGA is not limited when the large-scale design is distinguished, so that the condition of no solution is avoided, and the segmentation result can reach the optimal solution or the better solution because the least net number is used as the objective function for segmentation during segmentation; under the condition that two FPGAs which are not directly connected or are occupied in interconnection lines have communication requirements, under the condition that the module layout and the FPGA connection lines are fixed, the most suitable routing path is sought, and even if signals are transferred and transmitted through other FPGAs, the performance of the system reduction can be greatly reduced.

Meanwhile, the specification uses specific words to describe the embodiments of the specification. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present description. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present description may be combined as suitable.

Furthermore, the order in which the elements and sequences are processed, the use of numerical letters, or other designations in the description are not intended to limit the order in which the processes and methods of the description are performed unless explicitly recited in the claims. While certain presently useful inventive embodiments have been discussed in the foregoing disclosure, by way of various examples, it is to be understood that such details are merely illustrative and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements included within the spirit and scope of the embodiments of the present disclosure. For example, while the system components described above may be implemented by hardware devices, they may also be implemented solely by software solutions, such as installing the described system on an existing processing device or mobile device.

While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations to the present disclosure may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this specification, and therefore, such modifications, improvements, and modifications are intended to be included within the spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A method for optimizing a routing path of a node, comprising:

2. The method of claim 1, wherein prior to preprocessing the FPGA routing data, the method further comprises:

3. The method of claim 1, wherein preprocessing the FPGA routing data, updating weights of all wires and the weight table of FPGA interconnects, comprises:

4. The method of claim 1, wherein the initial segmentation with a segmentation minimum segmentation size as a segmentation target comprises:

5. The method of claim 1, further comprising, after updating the weights of all links and the weight table of FPGA interconnects:

6. The method according to any one of claims 1 to 5, wherein updating the weight table of FPGA interconnection again according to the division result, optimizing the routing path, comprises:

7. The method of claim 6, wherein ordering the second class of links comprises:

8. The method of claim 6, wherein performing a routing path optimization algorithm for each path based on the ranking results and updating the weight table of the FPGA interconnect based on the optimization results comprises:

s7: repeating the steps S5 to S6 until all the target FPGAs are traversed;

9. The method of claim 8, wherein the method further comprises:

10. A node route path optimizing apparatus according to the node route path optimizing method according to any one of claims 1 to 9, comprising: