CN116388136B - Surge current limiting circuit and chip - Google Patents
Surge current limiting circuit and chip Download PDFInfo
- Publication number
- CN116388136B CN116388136B CN202310641299.8A CN202310641299A CN116388136B CN 116388136 B CN116388136 B CN 116388136B CN 202310641299 A CN202310641299 A CN 202310641299A CN 116388136 B CN116388136 B CN 116388136B
- Authority
- CN
- China
- Prior art keywords
- field effect
- voltage
- effect transistor
- circuit
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000670 limiting effect Effects 0.000 title claims abstract description 52
- 230000005669 field effect Effects 0.000 claims abstract description 108
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 238000005070 sampling Methods 0.000 claims abstract description 33
- 230000000630 rising effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000001052 transient effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Direct Current Feeding And Distribution (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The present disclosure relates to the field of electronic devices, and in particular, to a surge current limiting circuit and a chip. The inrush current limiting circuit includes: the drain electrode of the field effect tube is connected to the power supply end through a load and a load capacitor, and the source electrode of the field effect tube is connected with the lowest voltage end of the system; the current mirror driving circuit is coupled to the grid electrode of the field effect transistor; a soft start charging circuit coupled to the control terminal of the current mirror driving circuit, configured to apply a driving voltage of the current mirror driving circuit to the gate of the field effect transistor with a charging rate; the impulse current sampling circuit is coupled to the drain electrode and the grid electrode of the field effect transistor and is configured to enable the grid electrode voltage of the field effect transistor to reversely change along with the sampled impulse current; and the comparison circuit is coupled to the source electrode and the grid electrode of the field effect transistor and is configured to control the grid electrode voltage of the field effect transistor to be reduced when the source electrode voltage of the field effect transistor is larger than a preset threshold voltage. The surge current limiting circuit has good limiting effect on surge current.
Description
Technical Field
The present disclosure relates to the field of electronic devices, and in particular, to a surge current limiting circuit and a chip.
Background
The surge current refers to transient current flowing into the power supply and the load equipment at the moment of connecting the power supply with the load. When the circuit board is inserted into the electrified backboard and equipment, the input filter capacitor on the circuit board is rapidly charged, so that the transient current is far greater than the steady-state input current, and further, the components on the circuit board are permanently damaged, and the power supply drops instantly, so that the normal operation of the backboard and the equipment is affected. It is therefore desirable to limit the surge current caused by transient effects to protect circuit boards, backplanes and devices from the surge current surge.
In the prior art, two modes are mainly adopted for limiting the surge current, one mode is to control the grid voltage of an external N-channel power field effect transistor through the cooperation of an active current limiting amplifier and an external circuit so as to limit the surge current, however, the mode is difficult to rapidly turn off the power field effect transistor and also difficult to adjust the current limiting value due to the fact that a capacitor is required to be connected between the grid and the source of the power field effect transistor in parallel; the other mode is that the under-voltage circuit, the overvoltage circuit and the power-on reset circuit are used together to prevent the grid voltage of the power field effect transistor from rising caused by false triggering, and then the active current limiting circuit is started to limit the surge current, but the mode cannot distinguish whether the abnormal current is the surge current or the heavy current caused by overload of the load.
Disclosure of Invention
In order to solve the defects existing in the prior art, the purpose of the application is to provide an inrush current limiting circuit and a chip for limiting an inrush current.
To achieve the above object, the present application provides an inrush current limiting circuit, including:
the drain electrode of the field effect tube is connected with the power supply end through the load and load capacitor end, and the source electrode of the field effect tube is connected with the lowest potential end of the system through the sampling resistor;
a current mirror driving circuit coupled to the gate of the field effect transistor;
a soft start charging circuit coupled to a control terminal of the current mirror driving circuit and configured to cause a driving voltage of the current mirror driving circuit to be applied to a gate of a field effect transistor at a charging voltage rising rate;
a rush current sampling circuit coupled to the drain and gate of the field effect transistor and configured to inversely vary the gate voltage of the field effect transistor with the sampled rush current;
and a comparison circuit coupled to the source and the gate of the field effect transistor and configured to control the gate voltage of the field effect transistor to decrease when the source voltage of the field effect transistor is greater than a preset threshold voltage.
Further, the soft start charging circuit at least includes:
a charging capacitor coupled to the charging current source;
a first zener diode arranged in parallel with the reverse bias of the charging capacitor;
and the operational amplifier is coupled between the charging capacitor and the current mirror driving circuit and controls the current mirror driving circuit.
Further, the charging circuit further comprises a current source and a switch connected in series between the charging power supply and the charging capacitor.
Further, the comparison circuit at least includes:
the reverse input end of the comparator is connected with the source electrode of the field effect tube, and the forward input end of the comparator is connected with a preset threshold voltage;
an isolation diode is coupled between the gate of the field effect transistor and the output of the comparator in a reverse bias manner.
Further, the comparison circuit is provided with at least two groups, and comparators of different groups are connected with different threshold voltages.
Further, the rush current sampling circuit comprises a sampling capacitor coupled to the drain of the field effect transistor.
Further, the rush current sampling circuit is coupled between the drain electrode of the field effect transistor and the current mirror driving circuit, and is configured to make the driving voltage output by the current mirror driving circuit change inversely with the rush current sampled by the sampling capacitor.
Further, the current mirror driving circuit comprises a first triode, a collector electrode of the first triode is connected with a drain electrode of the field effect tube, an emitter electrode of the first triode is connected with a collector electrode of the second triode, and the collector electrode of the second triode is connected with the drain electrode of the field effect tube through the sampling capacitor.
Further, a reverse biased zener diode is coupled between the collector and the emitter of the second triode.
To achieve the above object, the present application further provides a method of limiting an inrush current, the method including;
the grid voltage of the field effect transistor is controlled to rise to a preset voltage value according to a preset voltage rising speed;
adjusting the grid voltage of the field effect transistor based on the drain voltage change rate of the field effect transistor;
and adjusting the grid voltage of the field effect transistor based on the source voltage of the field effect transistor.
Further, the adjusting the voltage rising speed of the gate voltage of the field effect transistor includes:
based on the voltage rising rate of the charging capacitor during charging, the voltage rising rate of the gate voltage of the field effect transistor is correspondingly adjusted.
Further, the adjusting the gate voltage of the field effect transistor based on the drain voltage change rate of the field effect transistor includes:
and based on the drain voltage change rate of the sampling capacitor sampling field effect transistor, correspondingly adjusting the gate voltage of the field effect transistor.
Further, the adjusting the gate voltage of the field effect transistor based on the source voltage of the field effect transistor includes;
and adjusting the grid voltage of the field effect transistor based on a comparison result of the source voltage of the field effect transistor and a preset threshold voltage.
To achieve the above object, the present application further provides an inrush current limiting chip including the inrush current limiting circuit as described above.
The surge current limiting circuit and the chip are simple in structure, good in limiting effect on surge current, and capable of rapidly switching off the field effect transistor under the condition of heavy load, so that the working reliability of the circuit is greatly improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and explain the application and do not limit it. In the drawings:
fig. 1 is a schematic structural diagram of an inrush current limiting circuit provided in embodiment 1 of the present application;
fig. 2 is a schematic structural diagram of an inrush current limiting circuit provided in embodiment 2 of the present application;
fig. 3 is a schematic diagram of the structure of the inrush current limiting circuit provided in embodiment 3 of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and examples of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that references to "one" or "a plurality" in this application are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
An embodiment of the present application provides an inrush current limiting circuit, which improves the reliability of circuit operation.
Fig. 1 is a schematic structural diagram of an inrush current limiting circuit provided in embodiment 1 of the present application, and the inrush current limiting circuit of the present application will be described in detail below with reference to fig. 1, and the inrush current limiting circuit includes:
the field effect tube M1, the drain electrode of the field effect tube M1 is connected to the power supply end RTN through the load capacitor CL and the load, the source electrode of the field effect tube M1 is connected with one end of the sampling resistor Rs, the other end of the sampling resistor Rs is the power utilization end VEE, and the VEE end is connected with the grid electrode of the field effect tube M1 through the capacitor CG.
It can be understood that the RTN end of the power supply is the power supply of the device end or the back plate for supplying power to the circuit board, and the VEE end is connected with the lowest potential of the system to supply power to the circuit board.
The current mirror driving circuit 102 is coupled to the gate of the field effect transistor M1.
It can be appreciated that the current mirror driving circuit 102 is configured to provide a driving voltage to control the on and off of the fet M1 when powered on.
A soft start charging circuit, hereinafter referred to as charging circuit 101, coupled to the control terminal of the current mirror driving circuit 102, and configured to apply the driving voltage of the current mirror driving circuit 102 to the gate of the fet M1 with the charging rate;
it can be understood that the magnitude of the driving voltage outputted by the current mirror driving circuit 102 is related to the voltage of the control terminal and the components of the current mirror driving circuit 102, in this embodiment, the control terminal of the current mirror driving circuit 102 is coupled to the charging circuit 101, so that the voltage of the control terminal is determined by the charging voltage of the charging circuit, and at a constant charging rate, the voltage of the control terminal gradually increases with time, so that the driving voltage applied to the gate of the field effect transistor M1 also gradually increases, thereby avoiding abrupt changes of the driving voltage.
A rush current sampling circuit 103 coupled to the drain and gate of the field effect transistor M1 and configured to inversely vary the gate voltage of the field effect transistor M1 with the sampled rush current;
when the circuit board is inserted into the backboard, huge impact current can be generated, in the embodiment, the magnitude of the impact current is represented by sampling the drain voltage change rate of the field effect transistor M1, so that the gate voltage of the field effect transistor M1 changes reversely along with the sampled impact current, and the transient current is eliminated in sequence.
The comparison circuit 104 is coupled to the source and the gate of the fet M1, and is configured to control the gate voltage of the fet M1 to decrease when the source voltage of the fet M1 is greater than a preset threshold voltage.
Because larger load current is generated when the source electrode of the field effect transistor M1 is excessively loaded, in order to protect a circuit, a threshold voltage is preset, the source electrode voltage of the field effect transistor M1 is compared with the preset threshold voltage, and when the source electrode voltage of the field effect transistor M1 is larger than the preset threshold voltage, the gate electrode voltage of the field effect transistor M1 is controlled to be reduced so as to turn off the field effect transistor M1.
Example two
An embodiment of the present application provides an inrush current limiting circuit, which improves the reliability of circuit operation.
Fig. 2 is a schematic structural diagram of an inrush current limiting circuit provided in embodiment 2 of the present application, and the inrush current limiting circuit of the present application will be described in detail below with reference to fig. 2.
As shown in fig. 2, embodiment 2 is different from embodiment 1 in that:
the rush current sampling circuit 103 is coupled between the drain of the field effect transistor M1 and the current mirror driving circuit 102, and is configured to make the driving voltage output by the current mirror driving circuit 102 inversely vary with the rush current sampled by the sampling capacitor.
Example III
An embodiment of the present application provides an inrush current limiting circuit, which improves the reliability of circuit operation.
Fig. 3 is a schematic structural diagram of an inrush current limiting circuit provided in embodiment 3 of the present application, and the inrush current limiting circuit of the present application will be described in detail below with reference to fig. 3, and the inrush current limiting circuit includes:
the input end of the current source IS1 IS connected with a power VCC, the other end of the current source IS1 IS connected with the forward input end of the operational amplifier CF1 through a switch K1, a reverse biased zener diode D1 IS arranged between the forward input end of the operational amplifier CF1 and a ground end VEE, the two ends of the zener diode D1 are connected with a charging capacitor CSS in parallel, the forward input end of the operational amplifier CF1 IS a soft start node SS, the output end of the operational amplifier CF1 IS connected with the base electrode of a triode Q5, the reverse input end of the operational amplifier CF1 IS connected with the emitter electrode of the triode Q5, a resistor R5 IS arranged between the emitter electrode of the triode Q5 and the ground end VEE, the collector electrode of the triode Q5 IS connected with the power VCC through a current mirror circuit consisting of a MOS tube MP1, a MOS tube MP2 and a MOS tube MP3, the common grid electrode and the common source electrode of the MOS tube MP2 and the MOS tube MP3, the collector electrode of the triode Q5 IS connected with the drain electrode of the MOS tube MP1, the drain electrode of the MOS transistor MP1 IS also connected with the grid electrode thereof, the drain electrode of the MOS transistor MP2 IS connected with the collector electrode of the triode Q3, the collector electrode of the triode Q3 IS connected with the base electrode thereof and the base electrode of the triode Q1 to form a second-stage current mirror circuit, the emitter electrode of the triode Q3 IS connected with the collector electrode of the triode Q4 through a resistor R3, the collector electrode of the triode Q4 IS connected with the ground end VEE through a resistor R1, the collector electrode of the triode Q1 IS connected with the drain electrode of the MOS transistor MP3 and the grid electrode of the field effect transistor M1, the emitter electrode of the triode Q1 IS connected with the collector electrode of the triode Q2 through a resistor R4, the reflecting electrode of the triode Q2 IS connected with the ground end VEE, a reverse biased zener diode D4 IS arranged between the collector electrode of the triode Q2 and the ground end VEE, a sampling capacitor CR IS coupled between the collector electrode of the triode Q2 and the field effect transistor M1, the collector of the triode Q2 is a sampling node RAMP, the collector of the triode Q1 is a driving voltage output node GATE, the drain of the field effect tube M1 is connected with a power supply RTN through a load and a load capacitor CL, the source of the field effect tube M1 is connected with the grid of the field effect tube M1 through a resistor Rs and a capacitor CG, and a node between the resistor Rs and the capacitor CG is a VEE node, namely the lowest potential node for supplying power to a circuit board.
The source electrode of the field effect tube M1 is connected to the reverse input ends of the comparator U1 and the comparator U2, the forward input ends of the comparator U1 and the comparator U2 are respectively connected with the threshold voltages of 50MV and 150MV, and the output ends of the comparator U1 and the comparator U2 are respectively connected with the drain electrode of the field effect tube M1 through the isolation diodes D2 and D3 which are reversely biased.
The working mode of the embodiment of the application is as follows: when the circuit board IS connected to a power supply for operation, the switch K1 IS closed, the current source IS1 outputs a charging current ISs to charge the charging capacitor CSS through the switch K1, the current flowing into the charging capacitor CSS generates a voltage drop, and meanwhile, the operational amplifier CF1 outputs a signal to the emitter of the triode Q5, a pull-down current IS generated through the triode Q5 and the resistor R5, and the voltage drop on the resistor R5 IS equal to the voltage at two ends of the capacitor CSS. The current flowing through MOS transistor MP1 is mirrored to MP2 and MP3. Then flows through the resistors R1-R4, and emitter voltage drops are generated through the transistors Q1-Q4, so that noise margin of the sampling node RAMP is improved. Thus, the voltage drop applied to the capacitor CSS will generate a GATE voltage for pull-up at the driving voltage output node GATE, when the GATE voltage exceeds the threshold voltage of the fet M1, the current IRUSH starts to flow through the fet M1, the magnitude of the IRUSH current is determined by the IRAMP flowing through the sampling capacitor CR, the RAMP current continues to rise, and when the voltage across the charging capacitor CSS reaches the clamping value, the RAMP current reaches a constant value.
For example, when the voltage across the charging capacitor CSS is clamped to 2.56V (the bias voltage of the clamping circuit), the current of the corresponding driving voltage output node GATE is constant 11uA and the current of the constant IRAMP is constant 20uA, the voltage of the sampling node RAMP is stabilized at 1V, and at this time, the current IRUSH flowing through the fet M1 and the resistor RS is: irash=iramp CL/CR.
In the present embodiment, the rate of change in the voltage across the charging capacitor css=iss/CSS, the rate of change in the current IRAMP flowing through the sampling capacitor cr=iss/(css·r5), and the rate of change in the current IRUSH flowing through the field-effect transistor M1= (dI) RAMP /dt)(C L /C R )=( Iss · C L )/(Css · R5 ·C R ) 。
When the source voltage of the fet M1 drops to VEE due to a failure such as a bad contact of the load, IRAMP drops to 0 at this time, and the GATE voltage is pulled up to the voltage of the slope control circuit.
Illustratively, when overcurrent occurs, i.e., the voltage drop across resistor RS exceeds 50mV, comparator U1 starts, its internal short-circuit shutdown timer begins to count, operational amplifier CF1 controls the drive voltage output node GATE to steadily output a constant current of 50mV/RS, and when the circuit breaker circuit timer overflows, fet M1 shuts down. When an output short circuit occurs, the voltage drop across the RS resistor exceeds 150mV, and the comparator U2 will rapidly pull down the gate voltage of the fet M1. When the voltage drop on the RS is lower than 150mV but still higher than 50mV, the comparator U1 controls the driving voltage output node GATE until the circuit breaking timer of the internal circuit of the comparator overflows, and because the surge current control is independent of the current limiting and circuit breaking functions, the time of the circuit breaking timer can be set to be very short, so that the pressure born by the field effect transistor M1 under the condition that the output short circuit generates overcurrent is greatly reduced, and the working reliability of the circuit is improved.
Example IV
An embodiment of the present application provides a surge current limiting method, which improves the reliability of circuit operation, including:
the grid voltage of the field effect transistor is controlled to rise to a preset voltage value according to a preset voltage rising speed;
adjusting the grid voltage of the field effect transistor based on the drain voltage change rate of the field effect transistor;
and adjusting the grid voltage of the field effect transistor based on the source voltage of the field effect transistor.
As a preferred embodiment, adjusting the voltage rising speed of the gate voltage of the field effect transistor includes:
based on the voltage rising speed of the charging capacitor during charging, correspondingly adjusting the voltage rising speed of the grid voltage of the field effect transistor.
As a preferred embodiment, the adjusting the gate voltage of the fet based on the drain voltage change rate of the fet includes:
and based on the drain voltage change rate of the sampling capacitor sampling field effect transistor, correspondingly adjusting the gate voltage of the field effect transistor.
As a preferred embodiment, adjusting the gate voltage of the field effect transistor based on the source voltage of the field effect transistor includes;
and adjusting the grid voltage of the field effect transistor based on a comparison result of the source voltage of the field effect transistor and a preset threshold voltage.
Example five
To achieve the above object, the present application further provides an inrush current limiting chip including the inrush current limiting circuit as described above.
The above description is only illustrative of some of the embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the disclosure. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (14)
1. An inrush current limiting circuit, comprising:
the drain electrode of the field effect tube is connected with the power supply end through the load and load capacitor end, and the source electrode of the field effect tube is connected with the lowest potential end of the system through the sampling resistor;
a current mirror driving circuit coupled to the gate of the field effect transistor;
a soft start charging circuit coupled to a control terminal of the current mirror driving circuit and configured to apply a driving voltage output from the current mirror driving circuit to a gate of a field effect transistor at a charging voltage rising rate;
a rush current sampling circuit coupled to the drain and gate of the field effect transistor and configured to inversely vary the gate voltage of the field effect transistor with the sampled rush current;
and a comparison circuit coupled to the source and the gate of the field effect transistor and configured to control the gate voltage of the field effect transistor to decrease when the source voltage of the field effect transistor is greater than a preset threshold voltage.
2. The inrush current limiting circuit of claim 1, wherein said soft start charging circuit comprises at least:
a charging capacitor coupled to the charging current source;
a first zener diode arranged in parallel with the reverse bias of the charging capacitor;
and the operational amplifier is coupled between the charging capacitor and the current mirror driving circuit and controls the current mirror driving circuit.
3. The inrush current limiting circuit of claim 2, further comprising a current source and a switch connected in series between said charging power supply and a charging capacitor.
4. The inrush current limiting circuit of claim 1, wherein said comparison circuit comprises at least:
the reverse input end of the comparator is connected with the source electrode of the field effect tube, and the forward input end of the comparator is connected with a preset threshold voltage;
an isolation diode is coupled between the gate of the field effect transistor and the output of the comparator in a reverse bias manner.
5. The inrush current limiting circuit of claim 1, wherein said comparison circuit is provided with at least two groups, different groups of comparators being connected to different threshold voltages.
6. The inrush current limiting circuit of claim 1, wherein said inrush current sampling circuit comprises a sampling capacitor coupled at a drain of said field effect transistor.
7. The inrush current limiting circuit of claim 6, wherein the inrush current sampling circuit is coupled between the drain of the field effect transistor and the current mirror driving circuit and is configured to inversely vary a driving voltage outputted from the current mirror driving circuit with the inrush current sampled by the sampling capacitor.
8. The inrush current limiting circuit of claim 7, wherein said current mirror drive circuit comprises a first transistor having a collector connected to a drain of said field effect transistor, an emitter connected to a collector of a second transistor, and a collector connected to a drain of said field effect transistor through said sampling capacitor.
9. The inrush current limiting circuit of claim 8, wherein a reverse biased zener diode is coupled between the collector and emitter of said second transistor.
10. A method of limiting an inrush current, the method for the inrush current limiting circuit of any of claims 1-9, comprising;
the grid voltage of the field effect transistor is controlled to rise to a preset voltage value according to a preset voltage rising speed;
adjusting the grid voltage of the field effect transistor based on the drain voltage change rate of the field effect transistor;
and adjusting the grid voltage of the field effect transistor based on the source voltage of the field effect transistor.
11. The method of claim 10, wherein adjusting the voltage rise rate of the gate voltage of the field effect transistor comprises:
based on the voltage rising rate of the charging capacitor during charging, the voltage rising rate of the gate voltage of the field effect transistor is correspondingly adjusted.
12. The method of claim 10, wherein adjusting the gate voltage of the fet based on the rate of change of the drain voltage of the fet comprises:
and based on the drain voltage change rate of the sampling capacitor sampling field effect transistor, correspondingly adjusting the gate voltage of the field effect transistor.
13. The method of claim 10, wherein adjusting the gate voltage of the fet based on the source voltage of the fet comprises:
and adjusting the grid voltage of the field effect transistor based on a comparison result of the source voltage of the field effect transistor and a preset threshold voltage.
14. An inrush current limiting chip, characterized by comprising the inrush current limiting circuit of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310641299.8A CN116388136B (en) | 2023-06-01 | 2023-06-01 | Surge current limiting circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310641299.8A CN116388136B (en) | 2023-06-01 | 2023-06-01 | Surge current limiting circuit and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116388136A CN116388136A (en) | 2023-07-04 |
| CN116388136B true CN116388136B (en) | 2023-07-28 |
Family
ID=86971393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310641299.8A Active CN116388136B (en) | 2023-06-01 | 2023-06-01 | Surge current limiting circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116388136B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN203166497U (en) * | 2013-01-22 | 2013-08-28 | 广州金升阳科技有限公司 | Anti-surge DC protective circuit |
| CN108683416A (en) * | 2018-07-25 | 2018-10-19 | 上海艾为电子技术股份有限公司 | A kind of load switch control circuit |
| CN113110694A (en) * | 2021-04-30 | 2021-07-13 | 南京邮电大学 | Low dropout regulator circuit with current surge suppression |
| CN114204813A (en) * | 2020-09-02 | 2022-03-18 | 赛普拉斯半导体公司 | High voltage tolerant, high speed reverse current detection and protection for buck-boost converters |
| JP2022111661A (en) * | 2021-01-20 | 2022-08-01 | 株式会社デンソー | Reverse connection protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8885310B2 (en) * | 2012-10-31 | 2014-11-11 | Freescale Semiconductor, Inc. | Gate driver with desaturation detection and active clamping |
-
2023
- 2023-06-01 CN CN202310641299.8A patent/CN116388136B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN203166497U (en) * | 2013-01-22 | 2013-08-28 | 广州金升阳科技有限公司 | Anti-surge DC protective circuit |
| CN108683416A (en) * | 2018-07-25 | 2018-10-19 | 上海艾为电子技术股份有限公司 | A kind of load switch control circuit |
| CN114204813A (en) * | 2020-09-02 | 2022-03-18 | 赛普拉斯半导体公司 | High voltage tolerant, high speed reverse current detection and protection for buck-boost converters |
| JP2022111661A (en) * | 2021-01-20 | 2022-08-01 | 株式会社デンソー | Reverse connection protection circuit |
| CN113110694A (en) * | 2021-04-30 | 2021-07-13 | 南京邮电大学 | Low dropout regulator circuit with current surge suppression |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116388136A (en) | 2023-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101259209B1 (en) | Inrush current control system with soft start circuit and method | |
| CN102315632B (en) | Driving circuit for inhibiting over current of IGBT (Insulated Gate Bipolar Transistor) | |
| US10396664B2 (en) | Redundant power supply control circuit | |
| JP6978597B2 (en) | Charging device and terminal | |
| CN101588062B (en) | Protection circuit for semiconductor integrated circuit, driving method and system therefor | |
| CN102013802B (en) | BOOST circuit with short circuit protection function | |
| JP5376641B2 (en) | Battery device | |
| US20080192396A1 (en) | Over-voltage protection circuit and method thereof | |
| WO2019169904A1 (en) | Low-cost input anti-overvoltage protection circuit | |
| CN116667301B (en) | High-compatibility impact current suppression circuit | |
| CN213846230U (en) | Overcurrent protection circuit | |
| CN218387259U (en) | Dischargeable high-voltage DC power supply impact current suppression circuit | |
| CN211699667U (en) | Display device | |
| WO2020119531A1 (en) | Surge protection circuit and terminal and surge voltage bleeding method for power interface | |
| CN215733481U (en) | Optimized reverse connection prevention protection and impact current suppression circuit | |
| CN107979281B (en) | Input voltage division module and overvoltage protection switch | |
| CN116388136B (en) | Surge current limiting circuit and chip | |
| CN112491256A (en) | Overcurrent protection circuit and electrical equipment | |
| CN112018724B (en) | Overvoltage protection circuit | |
| CN108512191B (en) | Surge protection circuit, electronic equipment and surge protection method of circuit | |
| CN213693459U (en) | Overcurrent protection circuit and electrical equipment | |
| CN114498596A (en) | Electrostatic protection circuit, electrostatic protection method and integrated circuit | |
| CN108733122B (en) | Digital output circuit and industrial control equipment | |
| CN113131436A (en) | Overvoltage protection circuit, overvoltage protection device and electronic equipment | |
| EP0713616A1 (en) | Current driver with shutdown circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |