CN116366068A - Gm-C circuit of transconductance capacitance integrator - Google Patents

Abstract

Embodiments of the present specification provide a transconductor-capacitor integrator Gm-C circuit, wherein the circuit comprises: the input high-pass filter is connected with the transconductance unit and is used for providing proper direct-current bias voltage for the input differential pair transistor of the transconductance unit through the input direct-current bias voltage and the pseudo-resistance circuit by adjusting the size of the frequency point; a common mode feedback loop connected with the transconductance unit and used for outputting a common mode level VREF stabilized at an expected design to the transconductance unit; the transconductance unit is used for carrying out integral operation processing on a target signal and a feedback signal based on the direct-current bias voltage and the common mode level VREF under the control of internal processing logic of the incremental delta-sigma analog-to-digital converter with step quantization; and the integrating capacitor is connected with the common-mode feedback loop and the transconductance unit and is used for carrying out integration processing operation on the input signal and the feedback signal, simultaneously introducing voltages at two ends into an error amplifier of the common-mode feedback loop, generating a common-mode feedback signal and feeding the common-mode feedback signal back to a grid electrode of a common-mode feedback transistor TN5 of the transconductance unit, and stabilizing the common-mode voltage.

Description

Gm-C circuit of transconductance capacitance integrator

Technical Field

The document relates to the technical field of electronic circuits, in particular to a transconductance capacitance integrator Gm-C circuit.

Background

At present, direct quantization processing of a target signal by adopting a low-noise analog-to-digital converter is an emerging research field in the field of weak signal acquisition circuits. The Incremental delta-sigma analog-to-digital converter (intrinsic delta-sigma ADC) with the step quantization is a research hot spot in the field, has the advantages of low power consumption, low noise, small area, capability of integrating multiple channels in a single chip and the like, and has a huge application prospect, and especially has relevant applications such as weak signals of a human body acquired through electrodes, for example, nerve signals, electromyographic signals, electrocardiosignals and the like.

In the related art, the signals collected by the electrodes are often superimposed with a direct current offset error which is far larger than the amplitude of the target signal, which brings technical challenges to a signal processing circuit at a later stage. A transconductance-capacitance integrator (Gm-C) circuit of a conventional step-quantized incremental delta-sigma analog-digital converter adopts a direct current input mode, a target signal is directly input into a main circuit without being processed, and the design difficulty of a processing circuit is greatly increased due to the influence of direct current offset errors introduced by electrodes, so that the increase of the power consumption of the whole circuit is influenced.

In view of the above analysis of the development status in the technical field, the prior art solution cannot eliminate the influence of the electrode dc offset at a small cost, so there is a strong need for a step-by-step quantized incremental delta-sigma analog-to-digital converter transconductance capacitor integrator circuit capable of solving the above problems.

Disclosure of Invention

The invention aims to provide a transconductance capacitance integrator Gm-C circuit, which aims to solve the problems in the prior art.

The invention provides a transconductance capacitance integrator Gm-C circuit, which comprises:

the input high-pass filter is connected with the transconductance unit and is used for eliminating the influence of electrode direct current offset under the condition of not influencing an input target signal by adjusting the size of a frequency point, and providing proper direct current bias voltage for an input differential pair transistor of the transconductance unit through an input direct current bias voltage and a pseudo resistance circuit;

the common mode feedback loop is connected with the transconductance unit and is used for outputting a common mode level VREF stabilized at an expected design to the transconductance unit;

the transconductance unit is used for carrying out integral operation processing on a target signal and a feedback signal based on the direct-current bias voltage and the common mode level VREF under the control of internal processing logic of the incremental delta-sigma analog-to-digital converter with step quantization;

and the integrating capacitor is connected with the common-mode feedback loop and the transconductance unit and is used for carrying out integration processing operation on the input signal and the feedback signal, simultaneously introducing voltages at two ends into an error amplifier of the common-mode feedback loop, generating a common-mode feedback signal and feeding the common-mode feedback signal back to a grid electrode of a common-mode feedback transistor TN5 of the transconductance unit, and stabilizing the common-mode voltage.

The technical scheme provided by the embodiment of the invention can have the following beneficial effects: the transconductance capacitance integrator circuit of the incremental delta-sigma analog-to-digital converter with step quantification can eliminate the influence of electrode imbalance at a very low cost, relieve the processing difficulty of a conventional weak signal acquisition circuit, fully exert the advantages of the converter and realize very low power consumption and very small area.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

For a clearer description of one or more embodiments of the present description or of the solutions of the prior art, the drawings that are necessary for the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some of the embodiments described in the description, from which, for a person skilled in the art, other drawings can be obtained without inventive faculty.

FIG. 1 is a schematic diagram of a transconductance-capacitance integrator Gm-C according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an input high pass filter and pseudo-resistance circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an integrating capacitor circuit of a transconductance unit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a common mode feedback loop error amplifier according to an embodiment of the invention.

Detailed Description

In order to enable a person skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be clearly and completely described below with reference to the drawings in one or more embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one or more embodiments of the present disclosure without inventive faculty, are intended to be within the scope of the present disclosure.

According to an embodiment of the present invention, there is provided a transconductor-capacitor integrator Gm-C circuit, fig. 1 is a schematic diagram of the transconductor-capacitor integrator Gm-C according to the embodiment of the present invention, as shown in fig. 1, where the transconductor-capacitor integrator Gm-C according to the embodiment of the present invention specifically includes:

the input high-pass filter 10 is connected with the transconductance unit 14 and is used for eliminating the influence of electrode direct current offset by adjusting the frequency point under the condition of not influencing an input target signal, and providing proper direct current bias voltage for an input differential pair transistor of the transconductance unit 14 through an input direct current bias voltage and a pseudo resistance circuit;

a common mode feedback loop 12 connected to the transconductance unit 14 for outputting a common mode level VREF to the transconductance unit 14 that is stable at a desired design;

a transconductance unit 14, configured to perform an integration operation process of a target signal and a feedback signal based on the dc bias voltage and the common mode level VREF under the control of internal processing logic of the step-by-step quantized delta-sigma analog-to-digital converter;

the integrating capacitor 16 is connected to the common-mode feedback loop 12 and the transconductance unit 14, and is used for performing an integrating processing operation on the input signal and the feedback signal, and simultaneously introducing voltages at two ends into an error amplifier of the common-mode feedback loop 12 to generate a common-mode feedback signal, and feeding the common-mode feedback signal back to a gate of the common-mode feedback transistor TN5 of the transconductance unit 14 to stabilize the common-mode voltage.

The input high-pass filter comprises in particular: the input capacitor, the pseudo-resistance circuit and the input direct-current bias voltage, wherein the pseudo-resistance circuit comprises grid electrodes, source electrodes and body electrodes of the first PMOS transistors TPP1 and TPP1, and the pseudo-resistance circuit is formed by a turned-off PMOS transistor substantially, so that an extremely high resistance value is realized; the drain electrode of the TPP1 is connected with one end of the input capacitor C1, the grid electrode and the source electrode of the TPP1, the body electrode is connected with the direct current input bias voltage, and the other end of the input capacitor C1 is used as the input end of a signal.

The number of the input high-pass filters is 4, wherein one ends of the input capacitor C1, the input capacitor C2, the input capacitor C3 and the input capacitor C4 are respectively connected with the grid electrodes of TP1 and TP2, the grid electrodes of TP3 and TP4, the grid electrodes of TN1 and TN2 and the grid electrodes of TN3 and TN 4.

The input high pass filter is specifically for: and providing proper bias voltage for the input differential pair transistor of the transconductance unit, and adjusting the position of the 3dB bandwidth point of the formed input high-pass filter by adjusting the sizes of the input capacitor and the PMOS transistor of the pseudo-resistance circuit, so that the influence of electrode direct current offset is eliminated under the condition of not influencing a target signal.

The input high-pass filter comprises in particular: an input capacitor C1, an input capacitor C2, an input capacitor C3, an input capacitor C4, a dummy resistor circuit RP1, a dummy resistor circuit RP2, a dummy resistor circuit RP3, a dummy resistor circuit RP4, an input dc bias voltage VBIASN, and an input dc bias voltage VBIASP, wherein the input signal VIP is connected to one ends of the input capacitor C1 and the input capacitor C3, the input signal VIN is connected to one ends of the input capacitor C2 and the input capacitor C4, and the input dc bias voltage VBIASP is connected to gates of PMOS transistors TP1 and TP2 and gates of TP3 and TP4 through the dummy resistor circuit RP1 and the dummy resistor circuit RP2, respectively, to provide a dc bias voltage thereto; the input dc bias voltage VBIASN is connected to the gates of the NMOS transistors TN1 and TN2 and the gates of TN3 and TN4, respectively, through the dummy resistor circuit RP3 and the dummy resistor circuit RP4, and is supplied with the dc bias voltage.

The transconductance unit specifically comprises: an input differential pair transistor, a current source transistor, a common mode feedback transistor, a cascode transistor, and a step quantization phase control switch, wherein the input differential pair transistor comprises: a first PMOS transistor TP1, a second PMOS transistor TP2, a third PMOS transistor TP3, a fourth PMOS transistor TP4, a first NMOS transistor TN1, a second NMOS transistor TN2, a third NMOS transistor TN3, a fourth NMOS transistor TN4; the current source transistor includes: a fifth PMOS transistor TP5; the common mode feedback transistor includes: a fifth NMOS transistor TN5; the cascode transistor includes: a sixth PMOS transistor TP6, a seventh PMOS transistor TP7, a sixth NMOS transistor TN6, and a seventh NMOS transistor TN7; the step quantization stage control switches include a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, a switch SW6, a switch SW7, and a switch SW8;

TN5 is used as a common mode feedback transistor, so that output is stabilized at a common mode level VREF of an expected design, TP5 is used as a current source transistor to provide current, and TP1, TP2, TP3, TP4, TN1, TN2, TN3 and TN4 adopt complementary differential input tubes to carry out twice current multiplexing; the sources of TP1, TP2, TP3 and TP4 are short-circuited to the drain of TP5, the drain of TP1 is connected with the drain of TP2 through a switch SW1, the drain of TP1 is connected with the drain of TP3 through a switch SW3, the drain of TP3 is connected with the drain of TP4 through a switch SW2, and the drain of TP2 is connected with the drain of TP4 through a switch SW 4; sources of TN1, TN2, TN3 and TN4 are short-circuited to a drain of TN5, a drain of TN1 is connected with a drain of TN2 through a switch SW5, a drain of TN1 is connected with a drain of TN3 through a switch SW7, a drain of TN3 is connected with a drain of TN4 through a switch SW6, and a drain of TN2 is connected with a drain of TN4 through a switch SW8; the drain electrode of TP1 is connected with the source electrode of TP6, the drain electrode of TP4 is connected with the source electrode of TP7, the drain electrode of TN1 is connected with the source electrode of TN6, the drain electrode of TN4 is connected with the source electrode of TN7, the drains of TP6, TN6 and the drains of TP7, TN7 are respectively connected with two ends of an integrating capacitor C5.

The transconductance unit is specifically used for: the internal processing logic of the incremental delta-sigma analog-digital converter for executing the step quantization, wherein the SW1, the SW2, the SW5 and the SW6 switches are closed, the SW3, the SW4, the SW7 and the SW8 switches are opened, the TP1 and the TP2 are equivalent to one transistor, the TP3 and the TP4 are equivalent to one transistor, the TN1 and the TN2 are equivalent to one transistor, the TN3 and the TN4 are equivalent to one transistor, and the transconductance unit normally processes signals; when the SW1, SW2, SW5 and SW6 switches are opened and the SW3, SW4, SW7 and SW8 switches are closed, the input differential pair transistors of the transconductance units are connected in a staggered manner, the equivalent input transistors are shorted with each other, and the signal input to the transconductance units is zero.

The common mode feedback loop comprises an error amplifier and a common mode feedback voltage, wherein a common mode level detection end of the error amplifier is respectively connected with a source electrode of TP6 and a source electrode of TP7, a reference level end of the error amplifier is connected with the common mode feedback voltage, and an output end of the error amplifier is connected with a grid electrode of TN 5.

Both ends of the integrating capacitor are respectively connected with the source electrode of TP6 and the source electrode of TP 7.

The error amplifier is particularly used for: TP1 and TP2 are used as current sources, TP3 and TP6 are connected with reference voltage VREF, TP4 and TP5 are respectively connected with output voltages VON and VOP, errors of output common mode level and VREF are extracted for amplification, and an amplification result is fed back to a grid electrode of TN5;

if the feedback is in the form of current, the feedback nodes are selected to be the sources of TP6 and TP7 or the sources of TN6 and TN7 according to the type of pull-up or pull-down of the current feedback.

The above technical solutions of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The Gm-C circuit of the transconductance-capacitance integrator according to the embodiment of the invention specifically comprises:

the input high-pass filter 10 includes an input capacitor, a pseudo-resistance circuit, and an input dc bias voltage.

Common mode feedback loop 12 contains the error amplifier, the common mode reference voltage.

The transconductance unit 14 comprises an input differential pair transistor, a current source transistor, a cascode transistor, and a step quantization stage control switch.

And an integrating capacitor 16.

Fig. 2 is a schematic diagram of an input high-pass filter and a pseudo-resistance circuit according to an embodiment of the present invention, as shown in fig. 2, the input high-pass filter and the pseudo-resistance circuit according to an embodiment of the present invention specifically include:

and the capacitor C1, the pseudo-resistance circuit and the input direct-current bias voltage are input. The source electrode, the grid electrode and the bulk electrode of the PMOS transistor TPP1 are in short circuit to form a pseudo-resistance circuit, and the source electrode, the grid electrode and the bulk electrode of the PMOS transistor TPP1 are in short circuit as one end of the pseudo-resistance circuit, and the end is connected with an input bias voltage; the drain of TPP1 is used as the other end of the pseudo-resistance circuit, and the end is connected with one end of the input capacitor and the grid electrode of the input transistor at the same time, so as to provide proper bias voltage for the input transistor.

The 3dB bandwidth point of the formed high-pass filter can be adjusted by adjusting the sizes of the input capacitor and the PMOS transistor of the pseudo-resistance circuit, so that the influence of electrode direct current offset can be eliminated without influencing the input target signal. Meanwhile, the input direct-current bias voltage provides proper direct-current bias voltage for the input transistor of the transconductance unit through the pseudo-resistance circuit, so that the transconductance unit works normally.

Fig. 3 is a schematic diagram of a transconductor-capacitor integrator circuit according to an embodiment of the present invention, as shown in fig. 3, and specifically includes:

the input signal VIP is connected to one ends of the capacitors C1 and C3, and the input signal VIN is connected to one ends of the capacitors C2 and C4. The input DC bias voltage VBIASP is respectively connected to the grids of the PMOS transistors TP1 and TP2 and the grids of the PMOS transistors TP3 and TP4 through the pseudo-resistor circuits RP1 and RP2 to provide DC bias points for the PMOS transistors TP1 and TP 2; the input DC bias voltage VBIASN is respectively connected to the grids of the NMOS transistors TN1 and TN2 and the grids of TN3 and TN4 through the pseudo-resistance circuits RP3 and RP4 to provide DC bias points for the NMOS transistors; it is specifically noted that this can be simplified when the VBIASN and VBIASP voltages are equal, where the number of capacitors and pseudo-resistance circuits required is halved. The approach in fig. 3 is more generic.

PMOS transistor TP5 provides current as a current source and NMOS transistor TN5 acts as a common mode feedback control transistor, stabilizing the output at the desired designed common mode level VREF. The input differential pair transistors are composed of PMOS transistor pairs TP1, TP2, TP3 and TP4 and NMOS transistor pairs TN1, TN2, TN3 and TN4, and complementary differential input tubes are adopted, so that twice current multiplexing is realized, and half power consumption is saved. The source electrodes of the PMOS transistor pairs TP1, TP2, TP3 and TP4 are short-circuited to the drain electrode of TP5, the drain electrode of TP1 is connected with the drain electrode of TP2 through a switch SW1, the drain electrode of TP1 is connected with the drain electrode of TP3 through a switch SW3, the drain electrode of TP3 is connected with the drain electrode of TP4 through a switch SW2, and the drain electrode of TP2 is connected with the drain electrode of TP4 through a switch SW 4; the sources of the NMOS transistor pairs TN1, TN2, TN3 and TN4 are short-circuited to the drain electrode of TN5, the drain electrode of TN1 is connected with the drain electrode of TN2 through a switch SW5, the drain electrode of TN1 is connected with the drain electrode of TN3 through a switch SW7, the drain electrode of TN3 is connected with the drain electrode of TN4 through a switch SW6, and the drain electrode of TN2 is connected with the drain electrode of TN4 through a switch SW 8.

The switches SW1, SW2, SW5 and SW6 are closed, the switches SW3, SW4, SW7 and SW8 are opened, at the moment, TP1 and TP2 are equivalent to one transistor, TP3 and TP4 are equivalent to one transistor, TN1 and TN2 are equivalent to one transistor, TN3 and TN4 are equivalent to one transistor, and the transconductance unit normally processes signals; when the switches SW1, SW2, SW5, SW6 are open, the switches SW3, SW4, SW7, SW8 are closed, the input transistors of the transconductance units are connected in a staggered manner, the equivalent input transistors are shorted with each other, and the signal input to the transconductance units is zero. The purpose of this set of switches is to step-wise quantized delta-sigma analog-to-digital converter (inter delta-sigma ADC) internal processing logic. Then the drain electrode of TP1 is connected with the source electrode of the cascode tube TP6, the drain electrode of TP4 is connected with the source electrode of the cascode tube TP7, then the drain electrode of TN1 is connected with the source electrode of the cascode tube TN6, the drain electrode of TN4 is connected with the source electrode of the cascode tube TN7, and the drains of TP6, TN6 and the drains of TP7, TN7 are respectively connected with two ends of an integrating capacitor C5. The voltage at two ends of the integrating capacitor is simultaneously introduced into an error amplifier of a common mode feedback loop, and a common mode feedback signal is generated and fed back to a grid electrode of TN5 to stabilize the common mode voltage.

The drain electrode of TP1 is connected with the source electrode of PMOS transistor TP6, the drain electrode of TP4 is connected with the source electrode of PMOS transistor TP7, then the drain electrode of TN1 is connected with the source electrode of NMOS transistor TN6, the drain electrode of TN4 is connected with the source electrode of NMOS transistor TN7, the drain electrodes of TP6, TN6 and the drain electrodes of TP7, TN7 are respectively connected with two ends of an integrating capacitor C5. The voltage at two ends of the integrating capacitor is used as output voltage VON and VOP to be simultaneously introduced into an error amplifier of a common mode feedback loop, a common mode feedback signal is generated and fed back to a grid electrode of TN5, and common mode voltage is stabilized.

Fig. 4 is a schematic diagram of a common mode feedback loop error amplifier according to an embodiment of the present invention, as shown in fig. 4, and specifically includes:

PMOS transistors TP1 and TP2 are used as current sources, differential input transistors TP3 and TP6 are connected with reference voltages VREF, TP4 and TP5 respectively connected with output voltages VON and VOP in the second diagram, errors of output common mode level and VREF are extracted for amplification, and the amplified results are fed back to the grid electrode of a common mode feedback transistor TN5 in the second diagram.

Considering the feedback problem of a digital-to-analog converter (DAC) of the transconductance integrator, if the feedback is in a current form, the feedback nodes are sources of TP6 and TP7 when the feedback is performed by using a pull-up current, and the feedback nodes are sources of TN6 and TN7 when the feedback is performed by using a pull-down current, and the selection is made according to the type of the pull-up or pull-down of the current feedback.

In summary, aiming at the problems existing in the current situation, the invention provides the transconductance capacitance integrator Gm-C circuit, which adopts a capacitive coupling signal input mode, and an input capacitor and a pseudo-resistance circuit form a high-pass filter, so that the influence of electrode direct current offset is eliminated at a minimum cost, and the advantages of the incremental delta-sigma analog-digital converter of step quantification can be fully exerted. The subsequent transconductance unit circuit of the high-pass filter adopts a complementary input differential pair mode, so that current multiplexing is realized, and half of power consumption can be saved theoretically under the condition of unchanged noise.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (10)

1. A transconductor-capacitor integrator Gm-C circuit, comprising:

the input high-pass filter is connected with the transconductance unit and is used for eliminating the influence of electrode direct current offset under the condition of not influencing an input target signal by adjusting the size of a frequency point, and providing proper direct current bias voltage for an input differential pair transistor of the transconductance unit through an input direct current bias voltage and a pseudo resistance circuit;

a common mode feedback loop connected with the transconductance unit and used for outputting a common mode level VREF stabilized at an expected design to the transconductance unit;

the transconductance unit is used for carrying out integral operation processing on a target signal and a feedback signal based on the direct-current bias voltage and the common mode level VREF under the control of internal processing logic of the incremental delta-sigma analog-to-digital converter with step quantization;

and the integrating capacitor is connected with the common-mode feedback loop and the transconductance unit and is used for carrying out integration processing operation on the input signal and the feedback signal, simultaneously introducing voltages at two ends into an error amplifier of the common-mode feedback loop, generating a common-mode feedback signal and feeding the common-mode feedback signal back to a grid electrode of a common-mode feedback transistor TN5 of the transconductance unit, and stabilizing the common-mode voltage.

2. The transconductor-capacitor integrator Gm-C circuit according to claim 1, wherein the input high pass filter comprises in particular: the input capacitor, the pseudo-resistance circuit and the input direct current bias voltage, wherein the pseudo-resistance circuit comprises grid electrodes, source electrodes and body electrodes of first PMOS transistors TPP1 and TPP1, and the pseudo-resistance circuit is formed by using an off PMOS transistor to realize extremely high resistance value; the drain electrode of the TPP1 is connected with one end of the input capacitor C1, the grid electrode and the source electrode of the TPP1, the body electrode is connected with the direct current input bias voltage, and the other end of the input capacitor C1 is used as the input end of a signal.

3. The Gm-C circuit according to claim 2, wherein the input high pass filters are 4, and wherein one ends of the input capacitor C1, the input capacitor C2, the input capacitor C3, and the input capacitor C4 are respectively connected to the gates of TP1 and TP2, the gates of TP3 and TP4, the gates of TN1 and TN2, and the gates of TN3 and TN 4.

4. A transconductor-capacitor integrator Gm-C circuit as claimed in claim 3, characterized in that the input high-pass filter is in particular for: and providing proper bias voltage for the input differential pair transistor of the transconductance unit, and adjusting the position of the 3dB bandwidth point of the formed input high-pass filter by adjusting the sizes of the input capacitor and the PMOS transistor of the pseudo-resistance circuit, so that the influence of electrode direct current offset is eliminated under the condition of not influencing a target signal.

5. The transconductor-capacitor integrator Gm-C circuit according to claim 3, wherein the input high pass filter comprises in particular:

an input capacitor C1, an input capacitor C2, an input capacitor C3, an input capacitor C4, a dummy resistor circuit RP1, a dummy resistor circuit RP2, a dummy resistor circuit RP3, a dummy resistor circuit RP4, an input dc bias voltage VBIASN, and an input dc bias voltage VBIASP, wherein the input signal VIP is connected to one ends of the input capacitor C1 and the input capacitor C3, the input signal VIN is connected to one ends of the input capacitor C2 and the input capacitor C4, and the input dc bias voltage VBIASP is connected to gates of PMOS transistors TP1 and TP2 and gates of TP3 and TP4 through the dummy resistor circuit RP1 and the dummy resistor circuit RP2, respectively, to provide a dc bias voltage thereto; the input dc bias voltage VBIASN is connected to the gates of the NMOS transistors TN1 and TN2 and the gates of TN3 and TN4, respectively, through the dummy resistor circuit RP3 and the dummy resistor circuit RP4, and is supplied with the dc bias voltage.

6. A transconductor-capacitor integrator Gm-C circuit according to claim 3, characterised in that the transconductor cell comprises in particular: an input differential pair transistor, a current source transistor, a common mode feedback transistor, a cascode transistor, and a step quantization stage control switch, wherein the input differential pair transistor comprises: a first PMOS transistor TP1, a second PMOS transistor TP2, a third PMOS transistor TP3, a fourth PMOS transistor TP4, a first NMOS transistor TN1, a second NMOS transistor TN2, a third NMOS transistor TN3, a fourth NMOS transistor TN4; the current source transistor includes: a fifth PMOS transistor TP5; the common mode feedback transistor includes: a fifth NMOS transistor TN5; the cascode transistor includes: a sixth PMOS transistor TP6, a seventh PMOS transistor TP7, a sixth NMOS transistor TN6, and a seventh NMOS transistor TN7; the step quantization stage control switches include a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, a switch SW6, a switch SW7, and a switch SW8;

TN5 is used as a common mode feedback transistor, so that output is stabilized at a common mode level VREF of an expected design, TP5 is used as a current source transistor to provide current, and TP1, TP2, TP3, TP4, TN1, TN2, TN3 and TN4 adopt complementary differential input tubes to carry out twice current multiplexing; the sources of TP1, TP2, TP3 and TP4 are short-circuited to the drain of TP5, the drain of TP1 is connected with the drain of TP2 through a switch SW1, the drain of TP1 is connected with the drain of TP3 through a switch SW3, the drain of TP3 is connected with the drain of TP4 through a switch SW2, and the drain of TP2 is connected with the drain of TP4 through a switch SW 4; sources of TN1, TN2, TN3 and TN4 are short-circuited to a drain of TN5, a drain of TN1 is connected with a drain of TN2 through a switch SW5, a drain of TN1 is connected with a drain of TN3 through a switch SW7, a drain of TN3 is connected with a drain of TN4 through a switch SW6, and a drain of TN2 is connected with a drain of TN4 through a switch SW8; the drain electrode of TP1 is connected with the source electrode of TP6, the drain electrode of TP4 is connected with the source electrode of TP7, the drain electrode of TN1 is connected with the source electrode of TN6, the drain electrode of TN4 is connected with the source electrode of TN7, the drains of TP6, TN6 and the drains of TP7, TN7 are respectively connected with two ends of an integrating capacitor C5.

7. The transconductor-capacitor integrator Gm-C circuit according to claim 6, wherein the transconductor cell is specifically configured to:

the internal processing logic of the incremental delta-sigma analog-digital converter for executing the step quantization, wherein the SW1, the SW2, the SW5 and the SW6 switches are closed, the SW3, the SW4, the SW7 and the SW8 switches are opened, the TP1 and the TP2 are equivalent to one transistor, the TP3 and the TP4 are equivalent to one transistor, the TN1 and the TN2 are equivalent to one transistor, the TN3 and the TN4 are equivalent to one transistor, and the transconductance unit normally processes signals; when the switches SW1, SW2, SW5 and SW6 are opened and the switches SW3, SW4, SW7 and SW8 are closed, the input differential pair transistors of the transconductance units are connected in a staggered manner, the equivalent input transistors are shorted with each other, and the signal input to the transconductance units is zero.

8. The Gm-C circuit of claim 6, wherein the common mode feedback loop comprises an error amplifier and a common mode feedback voltage, wherein the common mode level detection terminal of the error amplifier is connected to the source of TP6 and the source of TP7, respectively, the reference level terminal of the error amplifier is connected to the common mode feedback voltage, and the output terminal of the error amplifier is connected to the gate of TN 5.

9. The Gm-C circuit of claim 6, wherein the integrating capacitor has two ends connected to the source of TP6 and the source of TP7, respectively.

10. The transconductor-capacitor integrator Gm-C circuit according to claim 9, wherein the error amplifier is in particular adapted to:

TP1 and TP2 are used as current sources, TP3 and TP6 are connected with reference voltage VREF, TP4 and TP5 are respectively connected with output voltages VON and VOP, errors of output common mode level and VREF are extracted for amplification, and an amplification result is fed back to a grid electrode of TN5;

if the feedback is in the form of current, the feedback nodes are selected to be the sources of TP6 and TP7 or the sources of TN6 and TN7 according to the type of pull-up or pull-down of the current feedback.

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