CN116364779A - Field effect transistor based on germanium selenide two-dimensional material and application thereof - Google Patents

Field effect transistor based on germanium selenide two-dimensional material and application thereof Download PDF

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Publication number
CN116364779A
CN116364779A CN202310308922.8A CN202310308922A CN116364779A CN 116364779 A CN116364779 A CN 116364779A CN 202310308922 A CN202310308922 A CN 202310308922A CN 116364779 A CN116364779 A CN 116364779A
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germanium selenide
field effect
effect transistor
layer
dimensional material
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袁延忠
张亚君
郭彩霞
袁秋林
杨豪强
于坤
王芳
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Henan Normal University
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Henan Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

The invention relates to a field effect transistor based on germanium selenide two-dimensional material and application thereof. The field effect transistor has the advantages of small volume and neat structure; and germanium selenide is adopted as a channel, so that switching current and subthreshold swing meeting HP application standards can be achieved, and the performance of the field effect transistor is further improved.

Description

Field effect transistor based on germanium selenide two-dimensional material and application thereof
Technical Field
The invention relates to the technical field of field effect transistors, in particular to a field effect transistor based on germanium selenide two-dimensional material and application thereof.
Background
A field effect transistor is a semiconductor device that uses the electric field effect of a control input loop to control an output loop. With the continuous development of electronic information technology, electronic devices are required to have lower energy consumption, smaller volume and higher integration, but the size of FETs has been reduced in the last fifty years. Today, feature sizes of MOS-type field effect transistors and other multi-gate transistors have reached 5 nanometers, the scaling process is extremely difficult, there is little further scaling, and further scaling will lead to practical problems such as Short Channel Effects (SCE). One of the solutions is to overcome the physical size limitations of silicon-based chips by exploring new channel materials with high band gaps to develop FETs.
As the two-dimensional nanomaterial discovered earliest, graphene has huge application potential in the field of nano photoelectrons by virtue of unique physical and chemical properties since 2004, and attracts a great deal of attention and research. But its natural zero band gap structure limits its wide practical application in the nanoelectronics field. In recent years, germanium selenide materials have attracted attention, which possess unique structures and exhibit excellent photoelectric properties, and thus have become alternatives to graphene two-dimensional materials.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a field effect transistor based on a germanium selenide two-dimensional material and application thereof, wherein the field effect transistor is small in volume and neat in structure; and germanium selenide is adopted as a channel, so that switching current and subthreshold swing meeting HP application standards can be achieved, and the performance of the field effect transistor is further improved.
The invention is realized by the following technical scheme: in one aspect, a field effect transistor based on germanium selenide two-dimensional material is provided, comprising a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and source/drain electrodes adjacent to the single gate structure, which are stacked in sequence from bottom to top.
Through the technical scheme, the source leakage current can be regulated and controlled by the dielectric layer material and the gate voltage, and the source leakage current can be regulated and controlled by changing the doping concentration of the silylene substrate, so that the regulating and controlling capability of the field effect transistor is greatly improved. Wherein the first isolation layer and the second isolation layer are an oxide layer and a vacuum layer, and preferably are vacuum layers; the obtained field effect transistor has small volume and neat structure; and germanium selenide is adopted as a channel, so that switching current and subthreshold swing meeting HP application standards can be achieved, and the performance of the field effect transistor is further improved.
Further, the substrate is prepared from a two-dimensional honeycomb-type silylene, and the silylene has a warped single-layer six-membered ring structure.
Further, the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer.
Through the technical scheme, the oxidation layer and the vacuum layer can be used for preventing the germanium selenide channel from being mutually influenced with the single gate structure and the substrate.
Further, the thickness of the oxide layer is 10-70nm.
Through the technical scheme, the silylene substrate layer is grown under the germanium selenide channel by using a vacuumizing technology. The channel material and the substrate material layer are made of different materials, and Schottky contact is formed between the channel material layer and the substrate material layer.
Further, the germanium selenide channel is made of N-doped or P-doped germanium selenide.
Through the technical scheme, a vertical hot wall Chemical Vapor Deposition (CVD) method is utilized to grow a 10nm germanium selenide P-type or N-type heavily doped region on the germanium selenide epitaxial layer; and growing a 10nm silylene P-type or N-type heavily doped region on the silylene epitaxial layer by using a vertical hot wall Chemical Vapor Deposition (CVD) method.
Further, the single gate structure is formed by stacking an insulating dielectric layer and a metal layer.
Through the technical scheme, the gate electrode is manufactured by utilizing photoetching and vapor deposition metal technology; the adopted substrate comprises a metal layer and an insulating medium layer; firstly, spin-coating 601 positive photoresist on an insulating medium layer 1, wherein the spin-coating time is 60s, and the spin-coating speed is 4000 rpm; then, an electrode pattern mask is formed on the insulating dielectric layer 1 through photoetching and development, wherein the used developer is tetramethyl ammonium hydroxide, and the development time is 15s. Finally, sequentially evaporating metal layers with the thickness of 10nm by using an electron beam evaporation evaporator, and then using acetone to carry out bubble washing to remove the photoresist and the metal layers outside the electrode area, thereby obtaining the metal electrode.
Further, the insulating medium layer is made of SiO 2 、SiC、SiN、HfO 2 、TiO 2 Any one of the following.
Further, the gate electrode, the source electrode and the drain electrode are made of one or two metals Au, cu, ni, ti, cr, ag.
Further, the source/drain electrode comprises silicon germanium and germanium selenide, wherein the Ge concentration in the germanium selenide is 23% -27%, and the Si concentration in the silicon germanium is 17% -24%.
In another aspect, an application of the field effect transistor based on germanium selenide two-dimensional material is provided.
By the technical scheme, the silicon transistor with the gate length reduced to below 10 nanometers is almost impossible to reach the aim of an international semiconductor technology roadmap (ITRS) because the short channel effect and the moore law are close to physical limits, and the field effect transistor has the advantages of small volume, quick response and the like. The requirements of ITRS on HP and low power consumption (LP) can be met.
The invention has the beneficial effects that: the invention can regulate and control the source leakage current through the dielectric layer material and the gate voltage, and can also regulate and control the source leakage through changing the doping concentration of the silylene substrate, thereby greatly improving the regulating and controlling capability of the field effect transistor.
According to the invention, by changing the material of the gate dielectric layer, different dielectric layers can obtain different subthreshold swing and on-state current. Wherein the different dielectric layers have different phasesFor dielectric constant. As the dielectric constant increases, the impact of the dielectric layer on device performance increases. For example, in SiO 2 、Al 2 O 3 And HfO 2 When the ion-exchange membrane is a substrate, ions and SS are gradually improved along with the reduction of relative dielectric constants. When the matrix is Al 2 O 3 As ions increased from 786. Mu.A/μm to 1206. Mu.A/μm, the SS value decreased from 134.2mV/dec to 123.4mV/dec.
According to the invention, the output characteristic curve is regulated and controlled through the gate voltage, and when positive bias is applied, the source and drain electrodes are reduced along with the increase of the gate voltage and saturated under smaller source and drain voltages; when a negative gate voltage is applied, the saturation current increases.
The invention regulates and controls the doping of the silylene substrate in the source-drain region, and the optimal doping concentration is 1 multiplied by 10 13 cm -2 。
Drawings
FIG. 1 is a schematic diagram of a bulk field effect transistor according to the present invention;
FIG. 2 is a schematic diagram of a source/drain structure of a FET according to the present invention;
fig. 3 is a graph showing the output characteristics of field effect transistors at different gate voltages.
Wherein, 1-metal layer; 2-an insulating medium layer; a 3-germanium selenide channel; a 4-silylene substrate; 5-source; 6-drain.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the embodiments of the present invention and the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
A field effect transistor based on germanium selenide two-dimensional material, as shown in fig. 1 and 2, comprising a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and source/drain electrodes adjacent to the single gate structure, which are stacked in sequence from bottom to top; the single gate structure is formed by stacking an insulating dielectric layer and a gate electrode; the specific manufacturing method of the field effect transistor of the germanium selenide two-dimensional material comprises the following steps:
step one: manufacturing a gate electrode by utilizing photoetching and vapor plating metal technology; the adopted substrate comprises a metal layer and an insulating medium layer; firstly, spin-coating 601 positive photoresist on an insulating medium layer 1, wherein the spin-coating time is 60s, and the spin-coating speed is 4000 rpm;
then, an electrode pattern mask is formed on the insulating dielectric layer 1 through photoetching and development, wherein the used developer is tetramethyl ammonium hydroxide, and the development time is 15s.
Finally, sequentially evaporating metal layers with the thickness of 10nm by using an electron beam evaporation evaporator, and then using acetone to carry out bubble washing to remove the photoresist and the metal layers outside the electrode area, thereby obtaining the metal electrode.
Step two: preparing a germanium selenide layer under the gate electrode by a vacuumizing technology; first, a germanium selenide material is grown under a gate electrode by a vacuum-pumping technique to prepare a channel material.
Then preparing the germanium selenide layer under the grid electrode by a low-temperature chemical vapor deposition technology, and preparing the germanium selenide layer on the grid electrode layer by a thermal oxidation mode; then using vacuumizing technology to grow a silylene substrate layer under the germanium selenide channel; based on the difference of materials of the channel material and the substrate material layer, schottky contact is formed between the channel material layer and the substrate material layer.
Specifically, the substrate is prepared from two-dimensional honeycomb-type silylene, and the silylene has a warpage single-layer six-membered ring structure; a high-resistivity epitaxial layer is grown on a silicon substrate with extremely low resistance, and devices are manufactured on the epitaxial layer, so that the high-resistivity epitaxial layer ensures that a tube has high breakdown voltage, and the low-resistance substrate reduces the resistance of the substrate, thereby reducing saturation voltage drop.
Further, the germanium selenide channel is made of N-doped and P-doped germanium selenide. Growing a 10nm germanium selenide P-type or N-type heavily doped region on the germanium selenide epitaxial layer by utilizing a vertical hot wall Chemical Vapor Deposition (CVD) method; and growing a 10nm silylene P-type or N-type heavily doped region on the silylene epitaxial layer by using a vertical hot wall Chemical Vapor Deposition (CVD) method.
Further, the single gate structure is formed by stacking an insulating dielectric layer and a gate electrode. The method comprises the steps of manufacturing a gate electrode by utilizing photoetching and vapor plating metal technology, wherein the substrate comprises a metal layer and an insulating medium layer. First, a 601 positive photoresist was spin-coated on the insulating dielectric layer 1 for 60 seconds at a spin-coating speed of 4000 rpm. Then, an electrode pattern mask is manufactured on the insulating medium layer 1 through photoetching and development, wherein the used developer is tetramethyl ammonium hydroxide, and the development time is 15s. Finally, sequentially evaporating metal layers with the thickness of 10nm by using an electron beam evaporation evaporator, and then using acetone to carry out bubble washing to remove the photoresist and the metal layers outside the electrode area, thereby obtaining the metal electrode.
Further, the insulating medium layer is made of SiO 2 、SiC、SiN、HfO 2 、TiO 2 Any one of the following.
Further, the gate electrode, the source electrode and the drain electrode are made of one or two metals Au, cu, ni, ti, cr, ag.
Further, the source/drain electrode comprises silicon germanium and germanium selenide, wherein the concentration of Ge in the germanium selenide is 23% -27%, and the concentration of Si in the silicon germanium is 17% -24%.
In the embodiment, the germanium selenide channel 3 is prepared from two-dimensional material germanium selenide, and the germanium selenide has good optical, electrical, mechanical and thermal properties, and is used as a channel of a field effect transistor to improve the performance.
In the embodiment, the N-doped germanium selenide and the P-doped germanium selenide are used as channels in the double-gate field effect transistor, so that switching current and subthreshold swing meeting HP application standards can be achieved, and further the performance of the field effect transistor is improved.
In this embodiment, the silylene substrate 4 is made of a two-dimensional material silylene, and the silylene has the advantages of moderate band gap, good stability, environmental friendliness, low price and the like, and is often selected as a material base in the semiconductor industry.
In this embodiment, the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer; specifically, the insulating layer 2 and the germanium selenide channel 3 are isolated by a vacuum layer/an oxide layer, and the germanium selenide channel 3 and the silylene substrate 4 are isolated by a vacuum layer/an oxide layer; preferably, the oxide layer has a thickness of 10-70nm. And the oxidation layer and the vacuum layer can be used for preventing the germanium selenide channel from being mutually influenced with the single gate structure and the substrate.
As shown in fig. 3, the output characteristic curve is controlled by the gate voltage, and when a positive bias is applied, the source-drain electrode decreases with an increase in the gate voltage, and is saturated at a smaller source-drain voltage. When a negative gate voltage is applied, the saturation current increases. The optimal doping concentration is 1 multiplied by 10 by regulating and controlling the doping of the silylene substrate in the source-drain region 13 cm -2 。
On the other hand, the application of the field effect transistor based on the germanium selenide two-dimensional material in the photoelectric field is provided. Silicon transistors with gate lengths scaled below 10 nanometers are almost impossible to reach the goal of the international semiconductor technology roadmap (ITRS) because of the short channel effect and moore's law which have been approaching physical limits. The field effect transistor has the advantages of small volume, quick response and the like, and can meet the requirements of ITRS on HP and low power consumption (LP).
In summary, the invention can regulate and control the source leakage current not only through the electron concentration and the gate voltage of the channel, but also through changing the doping concentration of the silylene substrate 4, thereby greatly improving the regulating and controlling capability of the field effect transistor.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.

Claims (10)

1. A field effect transistor based on germanium selenide two-dimensional material, which is characterized by comprising a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure and a source/drain electrode adjacent to the single gate structure, which are stacked in sequence from bottom to top.
2. The germanium selenide two-dimensional material based field effect transistor of claim 1, wherein the substrate is made of a two-dimensional honeycomb type silylene, and the silylene has a warped single layer six-membered ring structure.
3. The germanium selenide two-dimensional material based field effect transistor of claim 1, wherein the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer.
4. A field effect transistor based on germanium selenide two-dimensional material according to claim 3, wherein the thickness of the oxide layer is 10-70nm.
5. The germanium selenide two-dimensional material based field effect transistor of claim 1, wherein the germanium selenide channel is made of N-doped and P-doped germanium selenide.
6. The germanium selenide two-dimensional material based field effect transistor of claim 1, wherein the single gate structure is formed by stacking an insulating dielectric layer and a gate electrode.
7. The germanium selenide two-dimensional material based field effect transistor of claim 6, wherein the insulating dielectric layer is made of SiO 2 、SiC、SiN、HfO 2 、TiO 2 Any one of the following.
8. The germanium selenide two-dimensional material based field effect transistor of claim 6, wherein the gate electrode, the source electrode, and the drain electrode comprise one or two of the metals Au, cu, ni, ti, cr, ag.
9. The germanium selenide two-dimensional material based field effect transistor of claim 1, wherein the source/drain comprises silicon germanium and germanium selenide, wherein the Ge concentration in the germanium selenide is 23% to 27%, and wherein the Si concentration in the silicon germanium is 17% to 24%.
10. Use of a field effect transistor based on a germanium selenide two-dimensional material according to any of claims 1-9 in the photovoltaic field.
CN202310308922.8A 2023-03-27 2023-03-27 Field effect transistor based on germanium selenide two-dimensional material and application thereof Pending CN116364779A (en)

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