CN116364772B - Super-junction IGBT power device and preparation method - Google Patents
Super-junction IGBT power device and preparation method Download PDFInfo
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- CN116364772B CN116364772B CN202310383697.4A CN202310383697A CN116364772B CN 116364772 B CN116364772 B CN 116364772B CN 202310383697 A CN202310383697 A CN 202310383697A CN 116364772 B CN116364772 B CN 116364772B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract
The invention discloses a super-junction IGBT power device and a preparation method thereof. The power device includes: the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer and a non-uniform groove; the first epitaxial layer is arranged on the front surface of the substrate, the second epitaxial layer is arranged on one side, far away from the substrate, of the first epitaxial layer, and the non-uniform groove extends towards the inside of the second epitaxial layer along the surface, far away from the first epitaxial layer, of the second epitaxial layer; the first epitaxial layer includes: at least one first N-type region and a P-type column; the P-type columns and the first N-type regions are alternately arranged; the non-uniform trench includes: deep trenches and shallow trenches; the deep trenches and the shallow trenches are alternately arranged, the width of the deep trenches is larger than that of the shallow trenches, the deep trenches penetrate through the second epitaxial layer, and the bottoms of the deep trenches are contacted with the P-type columns. According to the technical scheme provided by the embodiment of the invention, under the condition that the forward conduction voltage drop of the device is not influenced, the Miller capacitance of the power device is effectively reduced, and the switching speed of the device is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of power semiconductor devices, in particular to a super-junction IGBT power device and a preparation method thereof.
Background
In recent years, superjunction IGBT power devices are popular power semiconductor devices under academic research. The super-junction IGBT is a novel IGBT device formed by arranging P pillars and N pillars arranged in sequence in a drift region of a conventional IGBT device structure. According to the difference of P column potentials which are sequentially arranged, two basic structures exist in the super-junction IGBT power device. The first type of structure is a super-junction IGBT with a P column connected with a P-type base region, and the second type of structure is a super-junction IGBT with a P column unconnected with a P-type base region. The super-junction IGBT power device of the first type structure has poor performance, and the super-junction IGBT power device of the second type structure has the advantage of low forward conduction voltage drop.
On the basis of the super-junction IGBT device with the second type of structure, various new processes and power devices with new structures such as an ultrathin super-junction IGBT device, a multichannel super-junction IGBT device and the like are also provided in the prior art, so that the forward conduction voltage drop of the super-junction IGBT device can be further reduced. However, for a multi-channel superjunction IGBT power device, the miller capacitance increases by providing multiple gate trenches within a single cell, resulting in a reduced superjunction IGBT switching speed.
Disclosure of Invention
The invention provides a super-junction IGBT power device and a preparation method thereof, which are used for reducing the Miller capacitance of the power device and improving the switching speed under the condition of not increasing the forward conduction voltage drop of the super-junction IGBT power device.
According to an aspect of the present invention, there is provided a super-junction IGBT power device, including: the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer and a non-uniform groove; the first epitaxial layer is arranged on the front surface of the substrate, the second epitaxial layer is arranged on one side, far away from the substrate, of the first epitaxial layer, and the non-uniform groove extends towards the inside of the second epitaxial layer along the surface, far away from the first epitaxial layer, of the second epitaxial layer;
the first epitaxial layer includes: at least one first N-type region and a P-type column; the P-type columns and the first N-type regions are alternately arranged;
the non-uniform trench includes: deep trenches and shallow trenches; the deep trenches and the shallow trenches are alternately arranged, the width of the deep trenches is larger than that of the shallow trenches, the deep trenches penetrate through the second epitaxial layer, and the bottoms of the deep trenches are in contact with the P-type columns.
Optionally, the power device includes at least one cell; in each cell, the deep trenches are arranged at the edges of two sides of the cell, and the shallow trenches are arranged between the two deep trenches;
the non-uniform trench includes: an oxide layer and a filler material; the oxide layer is arranged on the inner wall of the non-uniform groove, and the filling material fills the non-uniform groove.
Optionally, the filling material is heavily doped polysilicon.
Optionally, the second epitaxial layer includes: the second N-type region, the P-type base region and the N-type emitter region;
the P-type base region is arranged on one side, away from the first epitaxial layer, of the second N-type region and is arranged between the adjacent deep trench and the shallow trench; the second N-type region is arranged between two adjacent deep trenches, and the bottom of the shallow trench extends to the inside of the second N-type region;
the N-type emitter regions are arranged on two sides of the top of the shallow trench, and the thickness of the N-type emitter regions is smaller than that of the P-type base region.
Optionally, the depth of the shallow trench is 4-6 μm.
Optionally, the super-junction IGBT power device further includes: a collector metal layer, an emitter metal layer, and a dielectric layer;
the collector metal layer is arranged on one side of the substrate far away from the first epitaxial layer;
the dielectric layer is arranged on one side, far away from the first epitaxial layer, of the second epitaxial layer, and a plurality of through holes are formed in the dielectric layer at intervals, and the through holes expose the side face of the N-type emission region;
the emitter metal layer is arranged on one side, far away from the second epitaxial layer, of the dielectric layer, and the through hole is filled with the emitter metal layer.
According to another aspect of the present invention, there is provided a method for manufacturing a super junction IGBT power device, the method comprising:
providing a substrate;
forming a first epitaxial layer with alternately arranged P-type columns and first N-type regions on the surface of the substrate;
forming a second epitaxial layer on one side of the first epitaxial layer away from the substrate;
forming non-uniform grooves which are alternately arranged from the surface of the second epitaxial layer, which is far away from the first epitaxial layer, to the inside of the second epitaxial layer; the non-uniform grooves comprise deep grooves and shallow grooves, and the bottoms of the deep grooves are in contact with the P-type columns.
Optionally, the first epitaxial layer with P-type columns and N-type regions alternately arranged is disposed on the surface of the substrate, and includes:
epitaxially growing an N-type silicon material on the surface of the substrate to form the first N-type region;
photoetching to form etching patterns which are arranged at intervals on the first N-type region, and etching to form grooves in the first N-type region;
and filling the grooves with a P-type silicon material to form the P-type columns so as to obtain the first epitaxial layers with the P-type columns and the first N-type regions alternately arranged.
Optionally, the preparation method of the filling structure of the non-uniform trench comprises the following steps:
forming a top exposure pattern of the non-uniform groove on the surface of the second epitaxial layer by photoetching and etching the top exposure pattern so as to form the deep groove and the shallow groove simultaneously; the width of the top exposure pattern corresponding to the deep trench is larger than that of the top exposure pattern corresponding to the shallow trench;
forming an oxide layer on the inner wall of the non-uniform groove;
and depositing filling materials on the surface of the oxide layer, and filling the deep trench and the shallow trench to form a deep trench gate structure and a shallow trench gate structure.
Optionally, after forming the non-uniform trenches, further comprising:
forming a P-type base region inside the second epitaxial layer by adopting a self-alignment process and a high-temperature push-well process from the surface of one side of the second epitaxial layer far away from the first epitaxial layer, so that the second epitaxial layer comprises a second N-type region and the P-type base region;
forming N-type emitter regions on two sides of the horizontal direction of the top of the shallow trench from the surface of the P-type base region to the direction inside the P-type base region by adopting an ion implantation process;
forming a dielectric layer on the surface of one side of the second epitaxial layer far away from the first epitaxial layer;
etching the dielectric layer, and forming a through hole between two adjacent non-uniform grooves; wherein the through hole exposes the N-type emission region;
depositing an emitter metal layer on the surface of one side of the dielectric layer far away from the N-type emission region;
and thinning the surface of one side of the substrate far away from the first epitaxial layer, and forming a collector metal layer through ion implantation and metal deposition.
According to the technical scheme, the structure of the super-junction IGBT power device is formed by forming the first epitaxial layers with the plurality of P-type columns and the first N-type regions alternately arranged on one side of the substrate and forming the second epitaxial layers on one side of the first epitaxial layers away from the substrate. A plurality of non-uniform groove structures are formed by extending the surface of one side of the second epitaxial layer far away from the first epitaxial layer towards the inside of the second epitaxial layer, so that a multichannel super-junction IGBT device structure is formed, and the forward conduction voltage drop of the power device can be effectively reduced. The non-uniform groove comprises a deep groove and a shallow groove, and the width and the depth of the deep groove are larger than those of the shallow groove, and the bottom of the deep groove is contacted with the P-type column in the first epitaxial layer, so that the Miller capacitance of the power device can be effectively reduced under the condition that the forward conduction voltage drop of the super-junction IGBT power device is not influenced, and the switching speed of the device is improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a super-junction IGBT power device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a cell structure in a dashed box provided in the embodiment of FIG. 1 according to the present invention;
fig. 3 is a schematic diagram of a cell structure of another super-junction IGBT power device according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of yet another super-junction IGBT power device according to an embodiment of the invention;
fig. 5 is a schematic diagram of a cell structure of another super-junction IGBT power device according to an embodiment of the invention;
fig. 6 is a schematic flow chart of a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention;
fig. 7 is a schematic structural diagram corresponding to each step of a preparation method of a super-junction IGBT power device according to an embodiment of the invention;
fig. 8 is a schematic diagram of a specific flow of step S102 in a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention;
fig. 9 is a schematic structural diagram corresponding to a specific step of step S102 in a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention;
fig. 10 is a schematic diagram of a specific flow of step S104 in a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention;
fig. 11 is a schematic structural diagram corresponding to a specific step of step S104 in a preparation method of a super-junction IGBT power device according to an embodiment of the invention;
fig. 12 is a schematic diagram of a specific flow of a preparation method of another super-junction IGBT power device according to an embodiment of the invention;
fig. 13 is a schematic structural diagram corresponding to a preparation method of a super-junction IGBT power device according to an embodiment of the invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, there are two basic structures of super-junction IGBT power devices according to the difference of P column potentials that are sequentially arranged. The super-junction IGBT with the P column connected with the P-type base region is adopted. Because the P column is connected with the P-type base region, when the device is conducted in the forward direction, hole carriers injected from the back are basically collected by the P column and flow out of the device through the P-type base region, so that the conductivity modulation level of the IGBT device is weakened, and the super-junction IGBT power device has poor performance. The other type is a super-junction IGBT with a P column and a P type base region which are not connected. Through floating the P column, an extra parasitic PNP triode is formed, a loss channel of holes is blocked, and the advantage of low forward conduction voltage drop of the IGBT device is ensured. Based on the super-junction IGBT device with the second type of structure, the multichannel super-junction IGBT device can cause the increase of the Miller capacitance by arranging a plurality of gate grooves in a single unit cell, so that the switching speed of the super-junction IGBT device is reduced.
Based on the technical problems, the embodiment of the invention provides the following technical scheme:
the embodiment of the invention provides a super-junction IGBT power device. Fig. 1 is a schematic structural diagram of a super-junction IGBT power device according to an embodiment of the present invention. As shown in fig. 1, the super-junction IGBT power device includes: a substrate 10, a first epitaxial layer 20, a second epitaxial layer 30, and a non-uniform trench 40; the first epitaxial layer 20 is disposed on the front surface of the substrate 10, the second epitaxial layer 30 is disposed on a side of the first epitaxial layer 20 away from the substrate 10, and the non-uniform trench 40 extends along the surface of the second epitaxial layer 30 away from the first epitaxial layer 20 toward the inside of the second epitaxial layer 30.
The first epitaxial layer 20 includes: at least one first N-type region 21 and P-type column 22; the P-type pillars 22 alternate with the first N-type regions 21.
The non-uniform trenches 40 include: deep trenches 41 and shallow trenches 42; the deep trenches 41 and the shallow trenches 42 are alternately arranged, the width of the deep trenches 41 is larger than that of the shallow trenches 42, the deep trenches 41 penetrate through the second epitaxial layer 30, and the bottoms of the deep trenches 41 are in contact with the P-type columns 22.
Specifically, the substrate 10 may be a P-type silicon substrate, and the resistivity may be 2 to 40 Ω·cm. Illustratively, taking an N-type superjunction IGBT power device as an example, the first epitaxial layer 20 is provided with a plurality of first N-type regions 21 and P-type pillars 22, and the first N-type regions 21 and the P-type pillars 22 are alternately arranged in sequence, thereby forming a basic structure of the superjunction IGBT power device. It should be noted that, the thickness and resistivity of the first N-type region 21, the width and depth of the P-type column 22, and the doping concentration of the filled material are all related to the breakdown voltage of the superjunction IGBT power device, and the above parameters of the first N-type region 21 and the P-type column 22 can be set according to the actual design requirement of the superjunction IGBT power device, and the values of the parameters are not limited.
The non-uniform trench 40 is a trench having different widths and depths, and the non-uniform trench 40 includes a deep trench 41 and a shallow trench 42, for example. That is, the width and depth of the deep trench 41 are both larger than the width and depth of the shallow trench 42. The deep trench 41 penetrates through the whole second epitaxial layer 30, and the bottom of the deep trench 41 is in contact with the P-type column 22 in the first epitaxial layer 20. Illustratively, the bottom of the deep trench 41 may just contact the top of the P-type pillar 22 or may be embedded within the P-type pillar 22 a distance, without limitation. Therefore, the depth of the deep trench 41 is only required to be greater than or equal to the thickness of the second epitaxial layer 30, and is not limited in any way.
In addition, the deep trenches 41 and the shallow trenches 42 are alternately arranged at the same interval, fig. 1 shows a device structure in which only one shallow trench 42 is arranged between two adjacent deep trenches 41, and by arranging the shallow trenches 42, the forward conduction voltage drop of the super-junction IGBT power device can be reduced.
According to the technical scheme, the structure of the super-junction IGBT power device is formed by forming the first epitaxial layers with the plurality of P-type columns and the first N-type regions alternately arranged on one side of the substrate and forming the second epitaxial layers on one side, away from the substrate, of the first epitaxial layers. A plurality of non-uniform groove structures are formed by extending the surface of one side of the second epitaxial layer far away from the first epitaxial layer towards the inside of the second epitaxial layer, so that a multichannel super-junction IGBT device structure is formed, and the forward conduction voltage drop of the power device can be effectively reduced. The non-uniform groove comprises a deep groove and a shallow groove, and the width and the depth of the deep groove are larger than those of the shallow groove, and the bottom of the deep groove is contacted with the P-type column in the first epitaxial layer, so that the Miller capacitance of the power device can be effectively reduced under the condition that the forward conduction voltage drop of the super-junction IGBT power device is not influenced, and the switching speed of the device is improved.
Optionally, fig. 2 is a schematic cell structure diagram of a superjunction IGBT power device provided by the embodiment of the invention, and fig. 3 is a schematic cell structure diagram of another superjunction IGBT power device provided by the embodiment of the invention. On the basis of the above embodiments, referring to fig. 1 and 2, the power device includes at least one cell 01; in each cell 01, deep trenches 41 are arranged at two side edges of the cell 01, and shallow trenches 42 are arranged between the two deep trenches 41; the non-uniform trenches 40 include: an oxide layer 43 and a filler 44; the oxide layer 43 is disposed on the inner wall of the non-uniform trench 40, and the filling material 44 fills the non-uniform trench 40.
Specifically, the non-uniform trenches 40 include an oxide layer 43 and a filler material 44, and the oxide layer 43 is disposed along the inner wall of each non-uniform trench 40 to separate the filler material 44 from the epitaxial material of the second epitaxial layer 30 for insulation. A filler material 44 is deposited in each of the non-uniform trenches 40 having an inner wall provided with a uniform oxide layer 43, thereby forming a deep trench gate structure and a shallow trench gate structure. Illustratively, the fill material 44 is heavily doped polysilicon. The heavily doped polysilicon may include N-type heavily doped polysilicon and P-type heavily doped polysilicon, without limitation.
The super-junction IGBT power device comprises a plurality of cells 01 which have the same structure and are arranged in sequence, namely, the cells 01 are the minimum periodic repeated unit structures forming the power device. Illustratively, referring to fig. 1, the portion of the dashed box represents one cell 01 in the power device. In each cell 01, the first epitaxial layer 20 includes a P-type pillar 22 and the second epitaxial layer 30 includes a deep trench 41 and a shallow trench 42. The P-type pillars 22 are disposed at two side edges of the first epitaxial layer 20, the deep trenches 41 are disposed at two side edges of the second epitaxial layer 30, and bottoms of the deep trenches 41 are in contact with the corresponding P-type pillars 22, so that the miller capacitance of the device is reduced, and the switching speed of the device is increased.
It should be noted that, one shallow trench 42 may be included between two adjacent deep trenches 41 in the power device, and a plurality of shallow trenches 42 may also be included. That is, one shallow trench 42 may be provided in each cell 01, or a plurality of shallow trenches 42 may be provided. Illustratively, fig. 3 shows a structure including three shallow trenches 42 in one cell 01 of the power device. Referring to fig. 3, three shallow trenches 42 are arranged at intervals between two deep trenches 41. The shallow trench point positions additionally arranged can be connected with gate potential and emitter potential. Providing a plurality of shallow trenches 42 may increase minority carrier concentration at the emitter side of the power device, further reducing forward conduction voltage drop of the power device.
Optionally, fig. 4 is a schematic structural diagram of another super-junction IGBT power device provided by the embodiment of the invention, and fig. 5 is a schematic cellular structural diagram of another super-junction IGBT power device provided by the embodiment of the invention. On the basis of the above embodiments, as shown in fig. 4, the second epitaxial layer 30 includes: a second N-type region 31, a P-type base region 32 and an N-type emitter region 33.
The P-type base region 32 is disposed at one side of the second N-type region 31 away from the first epitaxial layer 20, and is disposed between the adjacent deep trench 41 and shallow trench 42; the second N-type region 31 is disposed between two adjacent deep trenches 41, and the bottom of the shallow trench 42 extends into the second N-type region 31; the N-type emitter region 33 is disposed on two sides of the top of the shallow trench 42, and the thickness of the N-type emitter region 33 is smaller than that of the P-type base region 32.
Specifically, for an N-type superjunction IGBT power device, the second epitaxial layer 30 is an N-type epitaxial layer prior to forming the non-uniform trenches 40. After the non-uniform trenches 40 are etched, P-type base regions 32 are formed inside the second epitaxial layer 30 on the surface of the second epitaxial layer 30 away from the first epitaxial layer 20 by ion implantation, and N-type emitter regions 33 are disposed on both sides of the top of the shallow trenches 42. For example, when a plurality of shallow trenches 42 are included in one cell 01, referring to fig. 5, N-type emitter regions 33 are provided in the second epitaxial layer 30 only on the top two sides of the shallow trench gate structure. The shallow trench 42 extends through the P-type base region 32 in the second epitaxial layer 30 to the second N-type region 31. The shallow trenches 42 are illustratively 4-6 μm deep.
Optionally, with continued reference to fig. 4 and fig. 5, based on the foregoing embodiments, the super junction IGBT power device further includes: a collector metal layer 50, an emitter metal layer 60, and a dielectric layer 70.
The collector metal layer 50 is disposed on a side of the substrate 10 away from the first epitaxial layer 20; the dielectric layer 70 is disposed on a side of the second epitaxial layer 30 away from the first epitaxial layer 20, and the dielectric layer 70 is provided with a plurality of through holes 71 at intervals, wherein the through holes 71 expose a side surface of the N-type emitter region 33; the emitter metal layer 60 is disposed on a side of the dielectric layer 70 away from the second epitaxial layer 30, and the emitter metal layer 60 is filled in the via 71.
Specifically, a dielectric layer 70 is further disposed between the emitter metal layer 60 and the second epitaxial layer 30, and the dielectric layer 70 can insulate the P-type base region 32 of the second epitaxial layer 30 far from the first epitaxial layer 20 from the emitter metal layer 60, planarize the surface of the second epitaxial layer 30, and facilitate the disposition of the emitter metal layer 60. Illustratively, the dielectric layer 70 may be borophosphosilicate glass. The dielectric layer 70 is provided with a plurality of through holes 71, and the emitter metal layer 60 is filled in the through holes 71 to be in contact with the N-type emitter region 33 and the P-type base region 32 through the through holes 71. It should be noted that, in the case where one cell 01 includes only one shallow trench, referring to fig. 4, the via 71 is disposed between the adjacent deep trench 41 and the shallow trench 42, and exposes the N-type emitter 33. For the case that one cell 01 includes a plurality of shallow trenches, referring to fig. 5, the through hole 71 is disposed not only between the adjacent deep trench 41 and the shallow trench 42, but also directly above the shallow trench 42 connected to the emitter potential in the plurality of shallow trenches 42, exposing the heavily doped polysilicon material filled in the shallow trench 42 to achieve the connection of the shallow trench 42 and the emitter metal layer 60. A collector metal layer 50 is provided on the back surface of the substrate 10 as a collector of the superjunction IGBT power device.
In addition, referring to fig. 5, a buffer layer 80 is disposed between the substrate 10 and the first epitaxial layer 20 by high-energy ion implantation in a direction of the first epitaxial layer 20 on a surface, i.e., a back surface, of the substrate 10 away from the first epitaxial layer 20, so as to effectively improve the switching speed of the super-junction IGBT power device and reduce the oscillation problem of the device.
The embodiment of the invention also provides a preparation method of the super-junction IGBT power device. Fig. 6 is a schematic flow chart of a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention, and fig. 7 is a schematic structural diagram corresponding to each step of the method for manufacturing a super-junction IGBT power device according to an embodiment of the invention. Referring to fig. 6 and 7, the preparation method of the super junction IGBT power device includes:
s101, providing a substrate 10;
s102, forming first epitaxial layers 20 with P-type columns 22 and first N-type regions 21 alternately arranged on the surface of a substrate 10;
s103, forming a second epitaxial layer 30 on one side of the first epitaxial layer 20 away from the substrate 10;
s104, forming non-uniform grooves 40 which are alternately arranged from the surface of the second epitaxial layer 30, which is far away from the first epitaxial layer 20, to the inside of the second epitaxial layer 30; wherein the non-uniform trench 40 includes a deep trench 41 and a shallow trench 42, and the bottom of the deep trench 41 is in contact with the P-type column 22.
According to the preparation method of the super-junction IGBT power device, the first epitaxial layers with the P-type columns and the first N-type regions alternately arranged are formed on the surface of the substrate, so that the basic structure of the super-junction IGBT power device is formed. And forming a plurality of deep trenches and shallow trenches on the surface of the second epitaxial layer inwards, wherein the deep trenches and the shallow trenches are alternately arranged, so that the forward conduction voltage drop of the super-junction IGBT power device is reduced. The bottom of the deep trench is contacted with the P-type column in the first epitaxial layer, so that the Miller capacitance is effectively reduced, and the switching speed of the super-junction IGBT power device is improved.
Optionally, fig. 8 is a specific flow schematic diagram of step S102 in a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention, and fig. 9 is a structural schematic diagram corresponding to a specific step of step S102 in a method for manufacturing a super-junction IGBT power device according to an embodiment of the invention. On the basis of the above embodiment, referring to fig. 8 and 9, a first epitaxial layer in which P-type pillars and N-type regions are alternately arranged is provided on a surface of a substrate, including:
and S1021, epitaxially growing an N-type silicon material on the surface of the substrate 10 to form a first N-type region 21.
S1022, forming etching patterns on the first N-type region 21 in a photolithography manner, and etching the first N-type region 21 to form the trench 211.
Specifically, a hard mask is deposited on the surface of the first N-type region, a pattern on the hard mask is formed by exposure, and a groove with a certain depth is formed by etching the pattern on the surface of the first N-type region inwards.
S1023, filling the grooves 211 with a P-type silicon material to form P-type columns 22, so as to obtain the first epitaxial layers 20 with the P-type columns 22 and the first N-type regions 21 alternately arranged.
Specifically, P-type silicon with a certain thickness is deposited on the surface of the first N-type region with the groove, so that the etched groove is filled. In addition, when the groove is filled to form the P-type column, a process combining multilayer epitaxial growth and ion implantation can be adopted to obtain the P-type column. And then flattening the surface of the first N-type region by adopting a chemical mechanical polishing process to obtain a first epitaxial layer with P-type columns and the first N-type regions alternately arranged.
Optionally, fig. 10 is a specific flow schematic diagram of step S104 in the method for manufacturing a super-junction IGBT power device according to the embodiment of the invention, and fig. 11 is a structural schematic diagram corresponding to the specific step of step S104 in the method for manufacturing a super-junction IGBT power device according to the embodiment of the invention. On the basis of the above embodiments, referring to fig. 10 and 11, a method for preparing a filling structure of a non-uniform trench includes:
s1041, forming a top exposure pattern of the non-uniform groove 40 on the surface of the second epitaxial layer 30 by photoetching and etching to form a deep groove 41 and a shallow groove 42 at the same time; wherein, the width of the top exposure pattern corresponding to the formation of the deep trench 41 is larger than the width of the top exposure pattern corresponding to the formation of the shallow trench 42.
Specifically, a hard mask is deposited on the surface of one side of the second epitaxial layer far away from the first epitaxial layer, a top exposure pattern of the deep trench and a top exposure pattern of the shallow trench are formed through exposure, and the size of the top exposure pattern of the deep trench is larger than that of the top exposure pattern of the shallow trench. Based on the 'loading effect' of ion etching, the top exposure pattern is etched simultaneously, and deep trenches and shallow trenches with different depths can be obtained through one-time etching process, so that the preparation process is simplified, and the cost is reduced.
S1042, forming an oxide layer 43 on the inner wall of the non-uniform trench 40.
Specifically, an oxide layer is grown on the surface of the second epitaxial layer, which is far away from the first epitaxial layer, by adopting a thermal oxidation method, so that the material in the groove and the material outside the groove are insulated.
S1043, depositing a filling material 44 on the surface of the oxide layer 43 to fill the deep trench 41 and the shallow trench 42, thereby forming a deep trench gate structure and a shallow trench gate structure.
Specifically, a filler material, which may be, for example, heavily doped polysilicon, is deposited on the oxide layer surface to fill the deep trenches and shallow trenches. And then carrying out back etching to planarize the non-uniform groove surface and the second epitaxial layer surface to obtain the deep groove gate structure and the shallow groove gate structure.
Optionally, fig. 12 is a specific flow diagram of a preparation method of another super-junction IGBT power device according to an embodiment of the invention, and fig. 13 is a corresponding structural diagram of the preparation method of another super-junction IGBT power device according to an embodiment of the invention. On the basis of the above embodiment, referring to fig. 12 and 13, after forming the non-uniform trenches, it further includes:
s105, a self-alignment process and a high-temperature push-well process are adopted, and a P-type base region 32 is formed from the surface of the second epitaxial layer 30, which is far away from the first epitaxial layer 20, to the inside of the second epitaxial layer 30, so that the second epitaxial layer 30 comprises a second N-type region 31 and the P-type base region 32.
Specifically, a self-alignment process is adopted to implant P-type ions into one side of the second epitaxial layer far away from the first epitaxial layer, and then a high-temperature push-well process is adopted to form a P-type base region. By way of example, the temperature employed by the high temperature push-well process may be 1100 ℃. Through the process operation, one side of the second epitaxial layer, which is close to the first epitaxial layer, is a second N-type region, and one side of the second epitaxial layer, which is far away from the first epitaxial layer, is a P-type base region.
S106, forming N-type emitter regions 33 from the surface of the P-type base region 32 to the inner direction of the P-type base region 32 by adopting an ion implantation process at two sides of the top horizontal direction of the shallow trench 42.
Specifically, exposure patterns are formed on two sides of the shallow trench through photoetching, and N-type ions are implanted into the exposure patterns on two sides of the shallow trench by adopting an ion implantation process, so that an N-type emission region is formed.
S107, a dielectric layer 70 is formed on the surface of the second epitaxial layer 30 on the side away from the first epitaxial layer 20.
Specifically, a dielectric material is deposited on the side of the second epitaxial layer away from the first epitaxial layer to form a dielectric layer. Illustratively, the dielectric layer may be borophosphosilicate glass.
S108, etching the dielectric layer 70 to form a through hole 71 between two adjacent non-uniform trenches 40; wherein the via 71 exposes the N-type emitter region 33.
Specifically, corresponding exposure areas are formed at positions between two adjacent non-uniform grooves on the dielectric layer through photoetching, and one side of each exposure area corresponds to one side of the N-type emission area away from the shallow groove. Etching the exposure region to form a through hole penetrating through the dielectric layer, wherein one side of the through hole exposes the N-type emission region.
And S109, depositing an emitter metal layer 60 on the surface of the dielectric layer 70 on the side far away from the N-type emitting region 33.
Specifically, metal aluminum is deposited on the surface of the dielectric layer, and is filled into the through hole, so that an emitter metal layer is formed and used as an emitter of the super-junction IGBT power device.
S110, thinning a surface of the substrate 10 away from the first epitaxial layer 20, and forming the collector metal layer 50 by ion implantation and metal deposition.
Specifically, the surface of the substrate, which is far away from the first epitaxial layer, is thinned, namely the back surface of the substrate is thinned. And then implanting P-type ions into the back surface of the substrate, and performing laser annealing to form a P-type collector region and ohmic contact. And after the back surface treatment of the substrate is finished, depositing metal on the back surface of the substrate to form a collector metal layer which is used as a collector of the super-junction IGBT power device.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A superjunction IGBT power device, comprising: the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer and a non-uniform groove; the first epitaxial layer is arranged on the front surface of the substrate, the second epitaxial layer is arranged on one side, far away from the substrate, of the first epitaxial layer, and the non-uniform groove extends towards the inside of the second epitaxial layer along the surface, far away from the first epitaxial layer, of the second epitaxial layer;
the first epitaxial layer includes: at least one first N-type region and a P-type column; the P-type columns and the first N-type regions are alternately arranged;
the non-uniform trench includes: deep trenches and shallow trenches; the deep trenches and the shallow trenches are alternately arranged, the width of the deep trenches is larger than that of the shallow trenches, the deep trenches penetrate through the second epitaxial layer, and the bottoms of the deep trenches are contacted with the P-type columns;
the power device includes at least one cell; in each cell, the deep trenches are arranged at the edges of two sides of the cell, and the shallow trenches are arranged between the two deep trenches; at least one shallow trench is arranged in each cell.
2. The super-junction IGBT power device of claim 1, wherein,
the non-uniform trench includes: an oxide layer and a filler material; the oxide layer is arranged on the inner wall of the non-uniform groove, and the filling material fills the non-uniform groove.
3. The super junction IGBT power device of claim 2 wherein the filler material is heavily doped polysilicon.
4. The superjunction IGBT power device of claim 1 wherein the second epitaxial layer comprises: the second N-type region, the P-type base region and the N-type emitter region;
the P-type base region is arranged on one side, away from the first epitaxial layer, of the second N-type region and is arranged between the adjacent deep trench and the shallow trench; the second N-type region is arranged between two adjacent deep trenches, and the bottom of the shallow trench extends to the inside of the second N-type region;
the N-type emitter regions are arranged on two sides of the top of the shallow trench, and the thickness of the N-type emitter regions is smaller than that of the P-type base region.
5. The super-junction IGBT power device of claim 4 wherein the shallow trench has a depth of 4 to 6 μm.
6. The superjunction IGBT power device of claim 4, further comprising: a collector metal layer, an emitter metal layer, and a dielectric layer;
the collector metal layer is arranged on one side of the substrate far away from the first epitaxial layer;
the dielectric layer is arranged on one side, far away from the first epitaxial layer, of the second epitaxial layer, and a plurality of through holes are formed in the dielectric layer at intervals, and the through holes expose the side face of the N-type emission region;
the emitter metal layer is arranged on one side, far away from the second epitaxial layer, of the dielectric layer, and the through hole is filled with the emitter metal layer.
7. The preparation method of the super-junction IGBT power device is characterized by comprising the following steps of:
providing a substrate;
forming a first epitaxial layer with alternately arranged P-type columns and first N-type regions on the surface of the substrate;
forming a second epitaxial layer on one side of the first epitaxial layer away from the substrate;
forming non-uniform grooves which are alternately arranged from the surface of the second epitaxial layer, which is far away from the first epitaxial layer, to the inside of the second epitaxial layer; the non-uniform groove comprises a deep groove and a shallow groove, and the bottom of the deep groove is contacted with the P-type column; the power device includes at least one cell; in each cell, the deep trenches are arranged at the edges of two sides of the cell, and the shallow trenches are arranged between the two deep trenches; at least one shallow trench is arranged in each cell.
8. The method for manufacturing a super-junction IGBT power device according to claim 7, wherein the disposing a first epitaxial layer having P-type columns and N-type regions alternately arranged on the surface of the substrate comprises:
epitaxially growing an N-type silicon material on the surface of the substrate to form the first N-type region;
photoetching to form etching patterns which are arranged at intervals on the first N-type region, and etching to form grooves in the first N-type region;
and filling the grooves with a P-type silicon material to form the P-type columns so as to obtain the first epitaxial layers with the P-type columns and the first N-type regions alternately arranged.
9. The method for manufacturing the super-junction IGBT power device according to claim 8, wherein the method for manufacturing the filling structure of the non-uniform trench comprises:
forming a top exposure pattern of the non-uniform groove on the surface of the second epitaxial layer by photoetching and etching the top exposure pattern so as to form the deep groove and the shallow groove simultaneously; the width of the top exposure pattern corresponding to the deep trench is larger than that of the top exposure pattern corresponding to the shallow trench;
forming an oxide layer on the inner wall of the non-uniform groove;
and depositing filling materials on the surface of the oxide layer, and filling the deep trench and the shallow trench to form a deep trench gate structure and a shallow trench gate structure.
10. The method of fabricating a superjunction IGBT power device of claim 7 further comprising, after forming the non-uniform trench:
forming a P-type base region inside the second epitaxial layer by adopting a self-alignment process and a high-temperature push-well process from the surface of one side of the second epitaxial layer far away from the first epitaxial layer, so that the second epitaxial layer comprises a second N-type region and the P-type base region;
forming N-type emitter regions on two sides of the horizontal direction of the top of the shallow trench from the surface of the P-type base region to the direction inside the P-type base region by adopting an ion implantation process;
forming a dielectric layer on the surface of one side of the second epitaxial layer far away from the first epitaxial layer;
etching the dielectric layer, and forming a through hole between two adjacent non-uniform grooves; wherein the through hole exposes the N-type emission region;
depositing an emitter metal layer on the surface of one side of the dielectric layer far away from the N-type emission region;
and thinning the surface of one side of the substrate far away from the first epitaxial layer, and forming a collector metal layer through ion implantation and metal deposition.
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