CN116347885B - SRAM and manufacturing method thereof - Google Patents

SRAM and manufacturing method thereof Download PDF

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Publication number
CN116347885B
CN116347885B CN202310631127.2A CN202310631127A CN116347885B CN 116347885 B CN116347885 B CN 116347885B CN 202310631127 A CN202310631127 A CN 202310631127A CN 116347885 B CN116347885 B CN 116347885B
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pull
region
control switch
sram
gate
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CN116347885A (en
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陈兴
黄普嵩
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • High Energy & Nuclear Physics (AREA)
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  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application provides an SRAM and a manufacturing method thereof, wherein an active region comprises a first region, a second region, a third region and a fourth region which are arranged at intervals along a first direction; the SRAM units are arranged on the active area along a second direction, two adjacent SRAM units are in mirror symmetry along a first direction, and the first direction is perpendicular to the second direction; the first pull-down pipe and the first control switch are arranged in the first area along the second direction, and the second pull-down pipe and the second control switch are arranged in the fourth area along the second direction; the distance between the gates of two adjacent first control switches (or second control switches) is a first distance, and in the SRAM cell, the distance between the first control switch (or second control switch) and the gate of the first pull-down tube (or second pull-down tube) is a second distance, where the second distance is greater than the first distance. The SRAM read-write noise margin is improved under the condition of not changing the prior art.

Description

SRAM and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an SRAM (Static Random-Access Memory) and a method for manufacturing the same.
Background
During SRAM read and write operations, the saturation current (I) of PG (Pass Gate, control switch) is required dsat ) The sizes are different to ensure the noise margin of the SRAM during the read and write operations. The existing SRAM structure can not meet different I in read-write process dsat The requirements result in a SRAM with poor immunity to interference.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main purpose of the application is to provide an SRAM and a manufacturing method thereof, so as to solve the problem of poor anti-interference capability caused by lower noise margin in the read-write process of the existing SRAM structure.
In order to achieve the object, according to one aspect of the present application, there is provided an SRAM including an active region and a plurality of SRAM cells, the SRAM cells including a first pull-down pipe, a first pull-up pipe, a first control switch, a second pull-down pipe, a second pull-up pipe, and a second control switch, wherein a source region or a drain region of the first pull-down pipe is in contact with the source region or the drain region of the first control switch, the first pull-down pipe shares a gate with the first pull-up pipe, a source region or a drain region of the second pull-down pipe is in contact with the source region or the drain region of the second control switch, the second pull-down pipe shares a gate with the second pull-up pipe, and the active region includes a first region, a second region, a third region, and a fourth region arranged at intervals along a first direction; a plurality of SRAM cells are arranged on the active area along a second direction, and two adjacent SRAM cells are in mirror symmetry along the first direction, wherein the first direction is perpendicular to the second direction; wherein the first pull-down tube and the first control switch are arranged in the first region along the second direction, the first pull-up tube is located in the second region, the second pull-up tube is located in the third region, and the second pull-down tube and the second control switch are arranged in the fourth region along the second direction; the distance between the grids of the adjacent two first control switches and the distance between the grids of the adjacent two second control switches are both first distances, and in the SRAM unit, the distance between the first control switch and the grid of the first pull-down tube and the distance between the second control switch and the grid of the second pull-down tube are both second distances, and the second distances are larger than the first distances.
Optionally, the distance between the gates of the adjacent two first pull-down tubes and the distance between the gates of the adjacent two second pull-down tubes are the second distances, respectively.
Optionally, the gate of the first control switch is a first gate, the gate of the second control switch is a second gate, the widths of the first gate and the second gate are the first width, the gate of the first pull-down tube is a third gate, the gate of the second pull-down tube is a fourth gate, the widths of the third gate and the fourth gate are the second width, the first width is greater than the second width, the width direction is parallel to the second direction, the surface of the first gate close to the third gate is a first surface, the surface of the fourth gate close to the second gate is a second surface, the first surface and the second surface are in the same plane, the surface of the third gate close to the first gate is a third surface, the surface of the second gate close to the fourth gate is a fourth surface, and the third surface and the fourth surface are in the same plane.
Optionally, the active region further includes a fifth region and a sixth region, the fifth region is located on a side of the first region away from the second region, the sixth region is located on a side of the fourth region away from the third region, the SRAM cell further includes a third control switch and a fourth control switch, the third control switch is located in the fifth region, the fourth control switch is located in the sixth region, the third control switch shares a gate with the first control switch, and the fourth control switch shares a gate with the second control switch.
Optionally, the second region includes a plurality of first sub-regions arranged at intervals along the second direction, the first pull-up tubes in two adjacent SRAM cells are located in the same first sub-region, the third region includes a plurality of second sub-regions arranged at intervals along the second direction, and the second pull-up tubes in two adjacent SRAM cells are located in the same second sub-region.
Optionally, the distance between the gates of the two adjacent first pull-down tubes and the distance between the gates of the two adjacent second pull-down tubes are both a third distance, and the third distance is greater than the first distance and less than the second distance.
Optionally, the widths of the gates of the first control switch, the second control switch, the first pull-up tube, the second pull-up tube, the first pull-down tube, and the second pull-down tube are all the same, and the width direction is parallel to the second direction.
According to another aspect of the present application, there is provided a method for manufacturing an SRAM, including: and performing ion implantation on a source region and a drain region corresponding to the first pull-down tube, the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube and the second control switch of any SRAM, wherein the areas of the source region and the drain region are in direct proportion to implantation concentration, and a final SRAM structure is obtained.
Optionally, ion implantation is performed on the source region and the drain region corresponding to the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube and the second control switch, including: forming a first mask structure on the surfaces of the first pull-up tube and the second pull-up tube; performing ion implantation on the SRAM covered with the first mask structure to dope the source region and the drain region of the first control switch, the second control switch, the first pull-down tube and the second pull-down tube; forming a second mask structure on the surfaces of the first control switch, the first pull-down pipe, the second control switch and the second pull-down pipe; and performing ion implantation on the SRAM covered with the second mask structure to dope the source region and the drain region of the first pull-up tube and the second pull-up tube.
Optionally, the ion implantation is HALO (HALO) ion implantation.
By applying the technical scheme of the application, unexpected technical effects which can be achieved by the application include:
1. in the SRAM, the source region or the drain region shared by two adjacent first control switches (or second control switches) is a first doped region, the source region or the drain region shared by the first control switches (or second control switches) and the adjacent first pull-down tube (or second pull-down tube) is a second doped region, and the surface area of the second doped region is larger than that of the first doped region, so that the doping concentration of the second doped region is larger than that of the first doped region under the same ion implantation condition when the ion implantation is performed on the SRAM in the application through the existing manufacturing process, and the asymmetry of the source end and the drain end of the first control switch (or the second control switch) is realized.
2. Because the doping concentration of the second doping region is larger than that of the first doping region, under the condition that the manufacturing process of the SRAM is not changed, the current flowing to the second doping region from the first doping region is small when the manufactured SRAM performs the read operation, the noise margin of the SRAM during the read operation can be ensured to be higher, and the noise margin of the SRAM is higher when the read operation is performed, so that the integral anti-interference capability of the SRAM is ensured to be stronger.
3. When the write operation is executed, the current flowing to the first doped region from the second doped region is large, so that the noise margin of the SRAM in the write operation is high, and the integral anti-interference capability of the SRAM is high.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 shows a layout schematic of an SRAM according to an embodiment of the present application;
FIG. 2 shows yet another layout schematic of an SRAM in accordance with an embodiment of the present application;
FIG. 3 illustrates a schematic diagram of ion implantation of the SRAM layout of FIG. 1 in accordance with one embodiment of the present application;
FIG. 4 illustrates a schematic diagram of ion implantation of the SRAM layout of FIG. 1 in accordance with another embodiment of the present application;
FIG. 5 illustrates a schematic diagram of ion implantation of the SRAM layout of FIG. 1 in accordance with yet another embodiment of the present application;
FIG. 6 shows an equivalent circuit diagram of the SRAM cell of FIG. 1;
FIG. 7 illustrates a schematic diagram of ion implantation of the SRAM layout of FIG. 2 in accordance with one embodiment of the present application;
FIG. 8 illustrates a schematic diagram of ion implantation of the SRAM layout of FIG. 2 in accordance with another embodiment of the present application;
FIG. 9 shows an equivalent circuit diagram of the SRAM cell in FIG. 2;
fig. 10 shows a schematic structural diagram of a mobile phone according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
20. an SRAM cell; 18. a final SRAM structure; 21. a mobile phone; 100. a first region; 101. a second region; 102. a third region; 103. a fourth region; 104. a fifth region; 105. a sixth region; 200. a first gate; 201. a second gate; 202. a third gate; 203. a fourth gate; 204. a fifth gate; 205. a sixth gate; 206. a seventh gate; 207. an eighth gate; 300. a first control switch; 301. a second control switch; 302. a third control switch; 303. a fourth control switch; 304. a first inverter; 305. a second inverter; 306. a first pull-up tube; 307. a first pull-down tube; 308. a second pull-up tube; 309. a second pull-down tube; 1011. a first sub-region; 1021. a second sub-region; 1041. a third subregion; 1051. and a fourth subregion.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the noise margin of the read-write process of the conventional SRAM structure is low, so that the anti-interference capability is poor.
According to an exemplary embodiment of the present application, there is provided an SRAM as shown in fig. 1 and 2, where the SRAM includes an active region and a plurality of SRAM cells 20, the SRAM cells 20 include a first pull-down pipe, a first pull-up pipe, a first control switch, a second pull-down pipe, a second pull-up pipe, and a second control switch, where a source region or a drain region of the first pull-down pipe is in contact with the source region or the drain region of the first control switch, the first pull-down pipe is in contact with a gate common to the first pull-up pipe, a source region or the drain region of the second pull-down pipe is in contact with the source region or the drain region of the second control switch, the second pull-down pipe is in contact with the gate common to the second pull-up pipe, and the active region includes a first region 100, a second region 101, a third region 102, and a fourth region 103 arranged at intervals along a first direction; the plurality of SRAM cells 20 are arranged on the active area along a second direction, and two adjacent SRAM cells 20 are mirror-symmetrical along the first direction, wherein the first direction is perpendicular to the second direction; wherein the first pull-down pipe and the first control switch are arranged in the first region 100 along the second direction, the first pull-up pipe is located in the second region 101, the second pull-up pipe is located in the third region 102, and the second pull-down pipe and the second control switch are arranged in the fourth region 103 along the second direction; the distance between the gates of the adjacent two first control switches and the distance between the gates of the adjacent two second control switches are both a first distance h1, and in the SRAM cell 20, the distance between the first control switch and the gate of the first pull-down tube and the distance between the second control switch and the gate of the second pull-down tube are both a second distance h2, where the second distance h2 is greater than the first distance h1.
In the above-mentioned SRAM, a plurality of SRAM cells are arranged on the active region along the second direction, and two adjacent SRAM cells are mirror-symmetrical along the first direction perpendicular to the second direction; in the SRAM unit, the first pull-down tube and the first control switch are arranged in a first area along a second direction, the first pull-up tube is positioned in a second area, the second pull-up tube is positioned in a third area, the second pull-down tube and the second control switch are arranged in a fourth area along the second direction, that is, two sides of one first control switch are respectively provided with the first pull-down tube and the other first control switch, and two sides of one second control switch are respectively provided with the second pull-down tube and the other second control switch; the distance between the grids of two adjacent first control switches is the same as the distance between the grids of two adjacent second control switches, and is the first distance, the distance between the grid of the first control switch and the grid of the adjacent first pull-down tube is the same as the distance between the grid of the second control switch and the grid of the adjacent second pull-down tube, and is the second distance, namely the distance between the grids of two adjacent first control switches (or second control switches) in the second direction is the first distance, the distance between the grid of the first pull-down tube (or second pull-down tube) and the grid of the adjacent first control switch (or second control switch) in the second direction is the second distance, and the first length is smaller than or equal to the third length, and the second length is smaller than or equal to the fourth length, so that the second distance is larger than the first distance and is equal to the surface area of the second doping region. In addition, the doping concentration of the second doping region is larger than that of the first doping region, so that under the condition that the manufacturing process of the SRAM is not changed, when the manufactured SRAM performs a read operation, the current flowing to the second doping region from the first doping region is small, and the noise margin of the SRAM during the read operation can be ensured to be higher; when the write operation is executed, the current flowing to the first doped region from the second doped region is large, so that the noise margin of the SRAM is high during the write operation, the noise margin of the SRAM is high no matter the write operation or the read operation, and the integral anti-interference capability of the SRAM is high.
In practical application, during SRAM read operation, PG is required to be I dsat Small, thus ensuring high SNM (Static Noise Margin ); during SRAM write operation, PG I is required dsat Large, thus ensuring that WM (Write Margin) is high. A PG with a particular asymmetry may give the SRAM optimal performance. And, although asymmetric compared to the control switch, during read operation, the PG has I dsat Large, while in write operation, PG is I dsat In the SRAM, the doping concentration of one end of the control switch connected with the pull-down tube is larger than that of one end of the control switch connected with the other control switch, so that asymmetry of the control switch is consistent with that required by the optimal read-write operation of the SRAM, and the performance of the SRAM is good.
According to a specific embodiment of the present application, as shown in fig. 1, the distance between the gates of two adjacent first pull-down tubes and the distance between the gates of two adjacent second pull-down tubes are the second distance h2. In this embodiment, the distance between the gates of the first control switch (or the second control switch) and the first pull-down tube (or the second pull-down tube) and the distance between the gates of two adjacent first pull-down tubes (or the second pull-down tubes) are the same, and the first pull-down tube (or the second pull-down tube) and the first pull-up tube (or the second pull-up tube) share the gates, which means that the source area and the drain area of the first pull-down tube (or the second pull-down tube) and the first pull-up tube (or the second pull-up tube) are symmetrical, the SRAM of the present application designs the source-drain symmetry of the pull-up tube and the pull-down tube while designing the source-drain asymmetry of the control switch, so that under the same area condition, as many SRAM cells can be arranged as possible, thereby ensuring that the occupied area of the whole SRAM structure is small.
In order to further solve the problem of poor noise margin in the conventional SRAM structure read/write process, as shown in fig. 1, in another embodiment of the present application, the gate of the first control switch is a first gate 200, the gate of the second control switch is a second gate 201, the widths of the first gate 200 and the second gate 201 are a first width W1, the gate of the first pull-down tube is a third gate 202, the gate of the second pull-down tube is a fourth gate 203, the widths of the third gate 202 and the fourth gate 203 are a second width W2, the first width W1 is greater than the second width W2, the width direction is parallel to the second direction, the surface of the first gate close to the third gate is a first surface, the surface of the fourth gate close to the second gate is a second surface, the first surface is on the same plane AA as the second surface, the widths of the third gate 202 and the fourth gate 203 are the widths of the third gate and the fourth surface is on the same plane as the fourth surface of the fourth gate. By setting the first width to be larger than the second width, setting the first surface and the second surface to be in the same plane, and setting the third surface and the fourth surface to be in the same plane, the surface areas of the source region and the drain region of the control switch in the obtained SRAM can be further ensured to be different, and the source region and the drain region of the control switch are further ensured to be asymmetric, so that the asymmetry of the source end and the drain end of the control switch is further ensured to meet the saturated current size required by the read-write operation of the SRAM, and the higher noise margin of the SRAM in the read-write process is further realized.
Of course, the positional relationship and the width relationship of the first gate, the second gate, the third gate, and the fourth gate are not limited to the above-described relationship, that is, the first surface and the second surface may not be located on the same surface, the third surface and the fourth surface may not be located on the same surface, the first width may not be greater than the second width, and the positions and the widths of the first gate, the second gate, the third gate, and the fourth gate may be flexibly set by a person skilled in the art as long as the distance between the first gate and the third gate is ensured to be greater than the distance between the adjacent first gates.
The SRAM may be a single-port SRAM or a multi-port SRAM, and in one embodiment of the present application, each SRAM cell includes at least 8 transistors, as shown in fig. 1, the active region further includes a fifth region 104 and a sixth region 105, the fifth region 104 is located on a side of the first region 100 away from the second region 101, the sixth region 105 is located on a side of the fourth region 103 away from the third region 102, the SRAM cell further includes a third control switch and a fourth control switch, the third control switch is located in the fifth region 104, the fourth control switch is located in the sixth region 105, the third control switch shares a gate with the first control switch, and the fourth control switch shares a gate with the second control switch. The third control switch and the first control switch share a gate, and the fourth control switch and the second control switch share a gate, and therefore the third control switch also has the same asymmetry as the first control switch, and the fourth control switch has the same asymmetry as the second control switch.
As shown in fig. 1, the gate of the first pull-up tube is a fifth gate 204, the gate of the second pull-up tube is a sixth gate 205, the gate of the third control switch is a seventh gate 206, and the gate of the fourth control switch is an eighth gate 207. The first gate 200 and the seventh gate 206 are gates formed of the same polysilicon, and thus the third control switch and the first control switch share a gate; the second gate 201 and the eighth gate 207 are gates formed of the same polysilicon, and thus the fourth control switch and the second control switch share a gate; the third gate 202 and the fifth gate 204 are gates formed of the same polysilicon, and thus the first pull-down pipe and the first pull-up pipe share a gate; the fourth gate 203 and the sixth gate 205 are gates formed of the same polysilicon, and thus the second pull-down pipe and the second pull-up pipe share a gate.
As shown in fig. 1, the fifth region 104 includes a plurality of third sub-regions 1041 arranged at intervals along the second direction, and the third control switches in two adjacent SRAM cells are located in the same third sub-region 1041. The sixth region 105 includes a plurality of fourth sub-regions 1051 arranged at intervals along the second direction, and the fourth control switches in the adjacent two SRAM cells are located in the same fourth sub-region 1051. The second region 101 includes a plurality of first sub-regions 1011 arranged at intervals along the second direction, the first pull-up transistors in two adjacent SRAM cells are located in the same first sub-region 1011, the third region 102 includes a plurality of second sub-regions 1021 arranged at intervals along the second direction, and the second pull-up transistors in two adjacent SRAM cells are located in the same second sub-region 1021.
In practical application, the schematic ion implantation diagrams corresponding to fig. 1 are shown in fig. 3, 4 and 5, and the equivalent circuit diagram of fig. 1 is shown in fig. 6, because the distances between the gates are different, the ion doses implanted into different regions will also be different. As shown in fig. 3 to 6, the ion dose between PG and PG (including two adjacent first gates 200 and two adjacent second gates 201) is low, and the ion dose between PG and PD (including two adjacent first gates 200 and third gates 202 and two adjacent second gates 201 and fourth gates 203) is high, so that the source end and the drain end of PG have asymmetry. In the SRAM of the present application, the source end and drain end of PG are defined as the common end of PG and PD (Pull Down tube), respectively, the source end of PG and Bit Line (BL) is defined as the common end of PG. For the first control switch (or the second control switch) and the third control switch (or the fourth control switch), the ion dosage of annular injection of the dry end is higher than that of the source end, so that the forward conduction current (the dry end flows to the source end) is large, and the reverse conduction current (the source end flows to the dry end) is small. The asymmetry of the on-current can improve noise margin in both SRAM read and write operations.
Of course, the ion implantation method is not limited to the annular ion implantation, and other implantation methods may be employed. The source and drain ends of the PG are opposite, and a common end of the PG and the PD can be set as a source end, and a connecting end of the PG and the bit line is a drain end of the PG.
The first control switch 300 and the third control switch 302 form PG0 in fig. 6, the second control switch 301 and the fourth control switch 303 form PG1 in fig. 6, wherein a gate of the first control switch 300 and a gate of the second control switch 301 are electrically connected to a Word Line (WL) respectively, and a gate of the third control switch 302 and a gate of the fourth control switch 303 are electrically connected to the word line respectively. The first pull-up tube and the first pull-down tube form a first inverter 304, and the second pull-up tube and the second pull-down tube form a second inverter 305. The first pull-up tube and the second pull-up tube are PMOS, and the first pull-down tube, the second pull-down tube, the first control switch and the second control switch are NMOS.
According to still another embodiment of the present application, as shown in fig. 2, the SRAM of the present application is a single-port SRAM, wherein each SRAM cell includes 6 transistors, and a distance between two adjacent gates of the first pull-down transistors (i.e., the third gate 202) and a distance between two adjacent gates of the second pull-down transistors (i.e., the fourth gate 203) are both a third distance h3, and the third distance h3 is greater than the first distance h1 and less than the second distance h2. Namely, the distance between the adjacent PDs is a third distance, the distance between the adjacent PDs and the PG is a second distance, the distance between the adjacent PG and the PG is a first distance, and the second distance > the third distance > the first distance is satisfied, so that the asymmetry of the PG source drain is realized, the asymmetry of the PD source drain is realized, and the asymmetry of the PG source drain is further ensured to meet the optimal read-write requirement of the SRAM.
Specifically, as shown in fig. 2, in the two SRAM cells adjacent in the first direction, the two second control switches share a gate, that is, the two second gates 201 are gates formed of the same polysilicon.
In order to further ensure the asymmetry of PG and further achieve the miniaturization of SRAM, in this embodiment of the present application, as shown in fig. 2, the widths of the gates of the first control switch, the second control switch, the first pull-up tube, the second pull-up tube, the first pull-down tube, and the second pull-down tube are all the same, where the width direction is parallel to the second direction.
In practical application, the schematic ion implantation diagrams corresponding to fig. 1 are shown in fig. 7 and 8, and the equivalent circuit diagram of fig. 2 is shown in fig. 9, because the distances between the gates are different, the ion doses implanted into different regions will also be different. As shown in fig. 7 to 9, the ion dose between PG and PG (including two adjacent first gates 200 and two adjacent second gates 201) is the lowest, and the ion dose between PG and PD (including two adjacent first gates 200 and third gates 202 and two adjacent second gates 201 and fourth gates 203) is the highest, so that the source end and the drain end of PG have asymmetry. Illustratively, in the SRAM of the present application, the source (source) end and drain (drain) end of PG and PD are defined as the shared end of PG and PD is the drain end, the connection end of PG and bit line is the source end of PG, and the connection end of PD and Vss is the source end of PD, respectively. For the first control switch (or the second control switch), the annular injection amount of ions at the drain terminal is higher than that at the source terminal, so that the forward conduction current (drain terminal flows to the source terminal) is large, and the reverse conduction current (source terminal flows to the drain terminal) is small. The asymmetry of the on-current can improve noise margin in both SRAM read and write operations. For the first pull-down tube (or the second pull-down tube), the ring-shaped implant ion dose at the drain end is higher than that at the source end, but since the source end is constantly connected with Vss, the on-current is always fixed from drain to source.
Of course, the ion implantation method is not limited to the annular ion implantation, and other implantation methods may be employed. The source and drain ends of the PG and the PD are opposite, and can be flexibly set by a person skilled in the art.
As shown in fig. 9, in the equivalent circuit diagram, the SRAM cell includes 6 transistors, the first pull-up transistor 306 and the first pull-down transistor 307 form a first inverter 304, and the second pull-up transistor 308 and the second pull-down transistor 309 form a second inverter 305. The first pull-up tube and the second pull-up tube are PMOS, and the first pull-down tube, the second pull-down tube, the first control switch and the second control switch are NMOS.
According to the embodiment of the application, a manufacturing method of the SRAM is also provided. The method comprises the following steps:
step S101, performing ion implantation on a source region and a drain region corresponding to any one of the first pull-down tube, the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube and the second control switch of the SRAM, wherein the areas of the source region and the drain region are in direct proportion to implantation concentration, and a final SRAM structure is obtained.
In the method for manufacturing the SRAM, the ion implantation is performed on the SRAM, the implantation concentration is in direct proportion to the area of the source drain region, in the structure of the SRAM, the source region or the drain region shared by two adjacent first control switches (or second control switches) is a first doped region, the source region or the drain region shared by the first control switch (or the second control switch) and the adjacent first pull-down tube (or the second pull-down tube) is a second doped region, the surface area of the second doped region is larger than the surface area of the first doped region, so that the doping concentration of the second doped region is larger than the doping concentration of the first doped region after the ion implantation, the asymmetry of the source end and the drain end of the first control switch (or the second control switch) of the SRAM is realized, and the doping concentration of the second doped region is larger than the doping concentration of the first doped region, so that under the condition of unchanged manufacturing process, the manufactured final SRAM structure has small current flowing to the second doped region when the first doped region performs the reading operation, and high tolerance of the final structure can be ensured when the reading operation is performed; when the write operation is executed, the second doped region flows to the first doped region with large current, so that the noise margin of the final SRAM structure is higher during the write operation, the noise margin of the final SRAM structure is higher no matter the write operation or the read operation, and the integral anti-interference capability of the final SRAM structure is higher.
Exemplary, ion implantation is performed on source and drain regions corresponding to the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube, and the second control switch, including: forming a first mask structure on the surface of the first pull-up tube and the second pull-up tube; ion implanting the SRAM covered with the first mask structure to dope the source region and the drain region of the first control switch, the second control switch, the first pull-down pipe, and the second pull-down pipe; forming a second mask structure on the surfaces of the first control switch, the first pull-down pipe, the second control switch and the second pull-down pipe; and performing ion implantation on the SRAM covered with the second mask structure to dope the source region and the drain region of the first pull-up tube and the second pull-up tube. In the method, the pull-down tube and the control switch share one mask structure, namely, the source-drain doping of the pull-down tube and the control switch can be realized by only one mask structure.
Alternatively, the ion implantation is halo ion implantation.
The embodiment of the application also provides electronic equipment, which comprises: the final SRAM structure is manufactured by the method.
The electronic equipment comprises the final SRAM structure, the asymmetry is introduced into the source-drain end of the control switch, and the noise margin of the read operation and the write operation of the SRAM can be improved simultaneously under the condition that the existing manufacturing process is not changed, so that the anti-interference capability of the electronic equipment is higher, and the performance is better.
In an embodiment of the present application, the electronic device includes at least one of the following: cell phone, desktop computer, tablet computer, notebook computer, server, vehicle-mounted equipment, wearable equipment, portable power source. In this embodiment, the memory adopting the semiconductor structure of the present application may be applied to any electronic device, and since the problem of breakdown of the semiconductor structure of the present application is late, the performance of the electronic device adopting the semiconductor structure is further improved. Fig. 10 shows a schematic structural diagram of a mobile phone according to an embodiment of the present application, and as shown in fig. 10, the mobile phone 21 includes a final SRAM structure 18 using the semiconductor structure of the present application.
From the above description, it can be seen that the above embodiments of the present application achieve the following unexpected technical effects:
1) In the SRAM described above, the source region or the drain region shared by two adjacent first control switches (or second control switches) is a first doped region, the source region or the drain region shared by the first control switch (or second control switch) and the adjacent first pull-down tube (or second pull-down tube) is a second doped region, and the surface area of the second doped region is larger than that of the first doped region, so that when the ion implantation is performed on the SRAM described above in the present application through the existing manufacturing process, the doping concentration of the second doped region can be larger than that of the first doped region under the same ion implantation condition, and the asymmetry of the source end and the drain end of the first control switch (or second control switch) is realized. In addition, the doping concentration of the second doping region is larger than that of the first doping region, so that under the condition that the manufacturing process of the SRAM is not changed, when the manufactured SRAM performs a read operation, the current flowing to the second doping region from the first doping region is small, and the noise margin of the SRAM during the read operation can be ensured to be higher; when the write operation is executed, the current flowing to the first doped region from the second doped region is large, so that the noise margin of the SRAM is high during the write operation, the noise margin of the SRAM is high no matter the write operation or the read operation, and the integral anti-interference capability of the SRAM is high.
2) In the method for manufacturing the SRAM, the ion implantation is performed on the SRAM, the implantation concentration is in direct proportion to the area of the source drain region, in the structure of the SRAM, the source region or the drain region shared by two adjacent first control switches (or second control switches) is a first doped region, the source region or the drain region shared by the first control switch (or the second control switch) and the adjacent first pull-down tube (or the second pull-down tube) is a second doped region, the surface area of the second doped region is larger than the surface area of the first doped region, so that the doping concentration of the second doped region is larger than the doping concentration of the first doped region after the ion implantation, the asymmetry of the source end and the drain end of the first control switch (or the second control switch) of the SRAM is realized, and in addition, under the condition that the manufacturing process of the SRAM is not changed, the current of the second doped region of the first doped region is small when the manufacturing final structure of the SRAM is used for executing the read operation, and the high read margin of the structure can be ensured finally; when the write operation is executed, the second doped region flows to the first doped region with large current, so that the noise margin of the final SRAM structure is higher during the write operation, the noise margin of the final SRAM structure is higher no matter the write operation or the read operation, and the integral anti-interference capability of the final SRAM structure is higher.
3) The electronic equipment comprises the final SRAM structure, the asymmetry is introduced into the source-drain end of the control switch, and the noise margin of the read operation and the write operation of the SRAM can be improved simultaneously under the condition that the existing manufacturing process is not changed, so that the anti-interference capability of the electronic equipment is higher, and the performance is better.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. An SRAM comprising an active region and a plurality of SRAM cells, the SRAM cells comprising a first pull-down tube, a first pull-up tube, a first control switch, a second pull-down tube, a second pull-up tube, and a second control switch, wherein a source or drain region of the first pull-down tube is in contact with a source or drain region of the first control switch, the first pull-down tube shares a gate with the first pull-up tube, a source or drain region of the second pull-down tube is in contact with a source or drain region of the second control switch, the second pull-down tube shares a gate with the second pull-up tube,
the active region comprises a first region, a second region, a third region and a fourth region which are arranged at intervals along a first direction;
a plurality of SRAM cells are arranged on the active area along a second direction, and two adjacent SRAM cells are in mirror symmetry along the first direction, wherein the first direction is perpendicular to the second direction;
wherein the first pull-down tube and the first control switch are arranged in the first region along the second direction, the first pull-up tube is located in the second region, the second pull-up tube is located in the third region, and the second pull-down tube and the second control switch are arranged in the fourth region along the second direction;
the distance between the gates of two adjacent first control switches and the distance between the gates of two adjacent second control switches are both first distances, in the SRAM cell, the distance between the first control switch and the gate of the first pull-down pipe and the distance between the second control switch and the gate of the second pull-down pipe are both second distances, the second distances are greater than the first distances, the length of the first region between the gates of two adjacent first control switches in the first direction is a first length, the length of the fourth region between the gates of two adjacent second control switches in the first direction is a second length, the length of the first region between the first control switch and the gate of the first pull-down pipe in the first direction is a third length, the length of the fourth region between the second control switch and the gate of the second pull-down pipe in the first direction is a fourth length, the length of the fourth region between the gates of the second control switch and the second pull-down pipe in the first direction is the fourth length, and the length of the fourth region between the gates of the second control switch and the second pull-down pipe is the fourth length or less.
2. The SRAM of claim 1, wherein a distance between gates of adjacent two of said first pull-down tubes and a distance between gates of adjacent two of said second pull-down tubes are said second distances, respectively.
3. The SRAM of claim 2, wherein the gate of the first control switch is a first gate, the gate of the second control switch is a second gate, the first gate and the second gate have a first width, the gate of the first pull-down tube is a third gate, the gate of the second pull-down tube is a fourth gate, the third gate and the fourth gate have a second width, the first width is greater than the second width, the width direction is parallel to the second direction,
the surface of the first grid electrode, which is close to the third grid electrode, is a first surface, the surface of the fourth grid electrode, which is close to the second grid electrode, is a second surface, the first surface and the second surface are located on the same plane, the surface of the third grid electrode, which is close to the first grid electrode, is a third surface, the surface of the second grid electrode, which is close to the fourth grid electrode, is a fourth surface, and the third surface and the fourth surface are located on the same plane.
4. The SRAM of any one of claims 1-3, wherein said active region further comprises a fifth region and a sixth region, said fifth region being located on a side of said first region remote from said second region, said sixth region being located on a side of said fourth region remote from said third region, said SRAM cell further comprising a third control switch and a fourth control switch, said third control switch being located in said fifth region, said fourth control switch being located in said sixth region, said third control switch sharing a gate with said first control switch, said fourth control switch sharing a gate with said second control switch.
5. The SRAM of any one of claims 1 to 3, wherein said second region comprises a plurality of first sub-regions spaced apart along said second direction, said first pull-up tubes in adjacent two of said SRAM cells being located in a same said first sub-region, said third region comprises a plurality of second sub-regions spaced apart along said second direction, said second pull-up tubes in adjacent two of said SRAM cells being located in a same said second sub-region.
6. The SRAM of claim 1, wherein a distance between gates of two adjacent first pull-down tubes and a distance between gates of two adjacent second pull-down tubes are each a third distance, the third distance being greater than the first distance and less than the second distance.
7. The SRAM of claim 6, wherein the first control switch, the second control switch, the first pull-up tube, the second pull-up tube, the first pull-down tube, and the second pull-down tube have the same gate width, and a width direction is parallel to the second direction.
8. A method for manufacturing SRAM is characterized by comprising the following steps:
ion implanting the source and drain regions corresponding to the first pull-down tube, the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube, and the second control switch of the SRAM of any one of claims 1 to 7, wherein the areas of the source and drain regions are proportional to the implantation concentration, resulting in a final SRAM structure.
9. The method of claim 8, wherein implanting ions into the source and drain regions corresponding to the first pull-up tube, the first control switch, the second pull-down tube, the second pull-up tube, and the second control switch comprises:
forming a first mask structure on the surfaces of the first pull-up tube and the second pull-up tube;
performing ion implantation on the SRAM covered with the first mask structure to dope the source region and the drain region of the first control switch, the second control switch, the first pull-down tube and the second pull-down tube;
forming a second mask structure on the surfaces of the first control switch, the first pull-down pipe, the second control switch and the second pull-down pipe;
and performing ion implantation on the SRAM covered with the second mask structure to dope the source region and the drain region of the first pull-up tube and the second pull-up tube.
10. The method of claim 9, wherein the ion implantation is halo ion implantation.
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