CN116346554A - Duobinary data transmission device capable of controlling inter-code crosstalk - Google Patents
Duobinary data transmission device capable of controlling inter-code crosstalk Download PDFInfo
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
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Abstract
The invention discloses a duobinary data transmission device capable of controlling inter-code crosstalk, which comprises a transmitter and a receiver, wherein the transmitter comprises: the pre-coding module is used for eliminating the correlation between the front and rear symbols of the multipath parallel low-speed source signals through pre-coding; a feedforward equalizer FFE for performing channel loss compensation; the parallel-serial conversion module is used for synthesizing the multipath parallel low-speed source signals into a plurality of paths of serial high-speed signals with fewer numbers; the high-speed synthesizer is used for synthesizing the multi-path serial high-speed signals into one path of data stream; a transmission driving circuit for outputting the data stream in the form of duobinary data; and a clock unit for providing a clock signal based on an externally input clock source. The method introduces controllable intersymbol interference in a precoding mode in the transmission process, and has lower requirements on signal bandwidth and subsequent equalizer performance.
Description
Technical Field
The invention belongs to a high-speed serial interface technology in the technical field of integrated circuit design and data transmission, and particularly relates to a duobinary data transmission device capable of controlling inter-code crosstalk.
Background
In recent years, with the rapid development of high-performance computing, the data transmission rate has also been greatly improved. Serializer/deserializer (SerDes) is one of the mainstream technologies for high-speed serial data communication, with the advantages of low cost, high speed, strong anti-interference capability, and the like. However, with the increase of signal rate, channel attenuation and inter-symbol crosstalk occur during high-speed channel transmission in a back-plane transmission system of a data center, a high-performance computer and other applications, so that channel integrity is a problem to be solved. Due to the non-ideal nature of the channel, conventional non-return-to-zero (NRZ) modulation has a significant impact on channel attenuation in high speed serial port applications above 56 Gb/s. The industry has therefore proposed duobinary (Dou-Binary, DB) as an alternative to PAM4 and NRZ. Some solutions employ a transmitter to equalize the 56Gb/s NRZ signal to DB at the channel output by means of feed-forward equalization (FFE), where the receiver directly decodes without using adaptive equalization techniques, which limits the overall performance of the equalizer. In addition, the scheme adopts a transmitting end to directly perform DB coding, but the requirement on the performance of a subsequent equalizer is higher.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a duobinary data transmission device capable of controlling inter-code crosstalk, which introduces controllable inter-code interference in a precoding mode in the transmission process and has lower requirements on signal bandwidth and subsequent equalizer performance.
In order to solve the technical problems, the invention adopts the following technical scheme:
a duobinary data transmission apparatus for controllable inter-symbol interference, comprising a transmitter, the transmitter comprising:
the pre-coding module is used for eliminating the correlation between the front and rear symbols of the multipath parallel low-speed source signals through pre-coding;
a feedforward equalizer FFE for performing channel loss compensation;
the parallel-serial conversion module is used for synthesizing the multipath parallel low-speed source signals into a plurality of paths of serial high-speed signals with fewer numbers;
the high-speed synthesizer is used for synthesizing the multi-path serial high-speed signals into one path of data stream;
a transmission driving circuit for outputting the data stream in the form of duobinary data;
a clock unit for providing a clock signal based on an externally input clock source;
the device comprises a pre-coding module, a feedforward equalizer FFE, a parallel-serial conversion module, a high-speed synthesizer and a transmitting driving circuit, wherein the input end of the pre-coding module is used for being connected with a signal generating module, the output end of the transmitting driving circuit is used for outputting the duobinary data obtained after coding, and the output end of a clock unit is respectively connected with the pre-coding module, the feedforward equalizer FFE, the parallel-serial conversion module and the clock signal input end of the high-speed synthesizer.
Optionally, the parallel-serial conversion module is a 64:4 parallel-serial conversion module, and is used for synthesizing 64 paths of parallel low-speed source signals into 4 paths of serial high-speed signals; the high-speed synthesizer is a 4:1 high-speed synthesizer and is used for synthesizing 4 paths of serial high-speed signals into one path of data stream.
Optionally, the functional expression of the input and output of the feedforward equalizer FFE is:
in the above formula, y (n) is an output signal, x (n-i) is an input signal of the ith tap, C i For the i-th tap coefficient, N is the number of taps.
Optionally, the feedforward equalizer FFE is a 4-tap feedforward equalizer, and the 4-tap feedforward equalizer includes: four tail current sources and load resistor R L NMOS tube M with 4 groups of symmetrical structures 1 ～M 8 Differential output signal TX_OUT of pre-coding module P [n]、TX_OUT N [n]Respectively through a load resistor R L Is connected with a power supply VDD and is connected with an NMOS tube M 1 ～M 8 Is connected with the drain electrode of NMOS tube M 1 ～M 8 Each group of NMOS tubes is connected with a tail current source by taking the group as a unit, the tail current source is used for updating tap coefficients by changing the transconductance of the NMOS tubes of the corresponding group by changing the current magnitude, and the grid electrodes of the 4 groups of NMOS tubes are respectively connected with four paths of differential DATA signals DATA output by a pre-coding module P [n-2～n+1]And DATA N [n-2～n+1]One path of the N-channel metal oxide semiconductor (NMOS) transistors is connected, and the drains of the 4 groups of NMOS transistors are overlapped and then respectively pass through another load resistor R L Output FFE_OUT P [n],FFE_OUT N [n]Two differential signals.
Optionally, the clock unit includes a phase-locked loop PPL and 4 sets of two frequency dividers, where an input end of the phase-locked loop PPL is connected to an external clock source, an output end of the phase-locked loop PPL generates a 14G clock signal, 875M clock signals generated by the 4 frequency dividers are respectively connected to the pre-coding module, the feedforward equalizer FFE, and the parallel-serial conversion module, and an output end of the phase-locked loop PPL is connected to a clock signal input end of the high-speed synthesizer to provide the high-speed synthesizer with the 14G clock signal.
Optionally, the method further comprises a receiver, the receiver comprising:
a receiving driving circuit for input matching and electrostatic discharge;
a continuous time linear equalizer CTLE for implementing duobinary signal modulation in combination with a channel and providing equalization processing;
the variable gain amplifier VGA is used for adjusting the dynamic range of a signal, adjusting the amplitude of an output signal to be suitable for the working range of a subsequent decision feedback equalizer and realizing the function of stabilizing the power of the output signal;
the feedback weighing instrument DFE is used for carrying out equalization processing on the duobinary signal so as to eliminate residual inter-code crosstalk in post-label processing;
the slicer is used for judging the DFE output signal and inputting the DFE output signal as an ideal signal into the adaptive equalization algorithm to realize the adaptive updating of the tap coefficient of the decision feedback equalizer;
a clock recovery circuit for generating a clock signal;
the input end of the receiving driving circuit is connected with an input signal source, the output end of the receiving driving circuit sequentially outputs a decoding signal Dn to a corresponding signal receiving module through a continuous time linear equalizer CTLE, a variable gain amplifier VGA, a judgment feedback equalizer DFE and a slicer, and the output end of the clock recovery circuit is respectively connected with clock signal input ends of the judgment feedback equalizer DFE and the slicer.
Optionally, the continuous-time linear equalizer CTLE is a continuous-time linear equalizer CTLE with a complementary symmetrical structure, and the continuous-time linear equalizer CTLE with the complementary symmetrical structure includes a PMOS tube M p1 ～M p4 NMOS tube M n1 ～M n4 Adjustable degenerated resistance R S Degradation capacitance C S For generating bias voltage V BP And bias voltage V Bn Bias voltage generating circuit of PMOS tube M p3 PMOS tube M p1 NMOS tube M n1 NMOS tube M n3 The PMOS tube M is connected in series between the power supply VDD and the ground GND through the end-to-end connection of the source electrode and the drain electrode p4 PMOS tube M p2 NMOS tube M n2 NMOS tube M n4 The PMOS tube M is connected in series between the power supply VDD and the ground GND through the end-to-end connection of the source electrode and the drain electrode p3 And PMOS tube M p4 The grid electrode of the two is connected with the bias voltage V BP A group of adjustable drains are connected in parallel betweenDegradation resistor R S And a degenerate capacitance C S PMOS tube M p1 NMOS tube M n1 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IP PMOS tube M p2 NMOS tube M n2 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IN NMOS tube M n3 And NMOS tube M n4 The grid electrode of the two is connected with the bias voltage V Bn Another group of adjustable degenerated resistors R are connected in parallel between the drain electrodes S And a degenerate capacitance C S The adjustable degeneration resistor R S The resistor comprises a plurality of resistor branches which are connected in parallel and have different resistance values, wherein each resistor branch comprises a switching tube and resistors which are connected in series at two sides of the switching tube and have the same resistance value.
Optionally, the bias voltage generating circuit comprises a resistor R, NMOS pipe M 5 ～M 8 And M 12 PMOS tube M 9 ～M 11 Current source I bias PMOS tube M 10 And PMOS tube M 9 One end of the resistor is connected with the power supply VDD through series connection, and the other end sequentially passes through the resistor R, NMOS tube M 7 And NMOS tube M 5 The path formed by connecting the source electrode and the drain electrode in series is grounded, and the current source I bias Is connected with the power supply VDD and the output end outputs the bias voltage V Bn And respectively with NMOS tube M 5 ～M 6 And M 12 Is connected with the grid electrode of NMOS tube M 12 Source drain electrode of (2) is grounded, PMOS tube M 11 The source and drain electrodes of the transistor are connected with the power supply VDD, the grid electrode and the PMOS tube M 10 Connected to the gate of (C) and outputting a bias voltage V BP NMOS tube M 7 And M 8 PMOS tube M 9 The grid electrode of (C) is respectively connected with a power supply V CM Connected with PMOS tube M 11 The grid electrode of (C) is also connected with the PMOS tube M 9 Is connected to the drain of the transistor.
Optionally, the method further comprises a first adaptive circuit for updating the bias voltage of the continuous-time linear equalizer CTLE to realize adaptive channel shaping, wherein the first adaptive circuit updates the function expression of the bias voltage of the continuous-time linear equalizer CTLE as follows:
dlev(n+1)＝dlev(n)+ CTLE e(n)·d()，
in the above formula, dlev (n+1) is the bias voltage at time n+1, dlev (n) is the bias voltage at time n, μ CTLE As the iteration factor, d (n) is the ideal signal replaced after the feedback equalizer DFE is judged at the moment of n, and e (n) is the error signal of the output result of the continuous time linear equalizer CTLE at the moment of n.
Optionally, the method further comprises a second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE, wherein the second adaptive circuit updates the functional expression of the tap coefficients of the decision feedback equalizer DFE as follows:
in the above formula, w (n+1) is the tap coefficient at time n+1, w (n) is the tap coefficient at time n, μ DFE As a result of the iteration factor,
and E (n) is an error signal between d (n) at the time of n and an output result of the continuous time linear equalizer CTLE, d (n-1) is an ideal replacing signal judged by the feedback equalizer DFE at the time of n-1, and d (n) is an ideal replacing signal judged by the feedback equalizer DFE at the time of n.
Optionally, the feedback equalizer DFE is a two-tap half-rate feedback equalizer DFE, the two-tap half-rate feedback equalizer DFE includes a combiner MUX, a buffer, and two half-rate data paths, each half-rate data path is serially connected with an adder and two cascaded master-slave D flip-flops, and each half-rate data path is further provided with a first multiplier for integrating the tap coefficient C 2 And the output of the second master-slave D flip-flop after the delay is multiplied by a second input of the adder, a second multiplier for multiplying the tap coefficient C 1 The output of the first master-slave D trigger after time delay is multiplied by a third input of an adder as another half-rate data path, and the first input of the adder is a two-tap half-rate judgment feedback weighing instrument DAnd the adder sums three paths of inputs to serve as the input of a first master-slave D trigger, obtains an Odd signal Odd and an Even signal Even through a second master-slave D trigger of the two half-rate data paths respectively, synthesizes the Odd signal Odd and the Even signal Even through a combiner MUX in a 2:1 mode, and then buffers and outputs the signals through a buffer.
Compared with the prior art, the invention has the following advantages:
1. the invention designs a 56Gbp transceiver system (at least comprising a transmitter) based on a duobinary Data (DB) coding technology aiming at a channel with attenuation greater than 35dB at a Nyquist frequency, and can realize reliable transmission of the duobinary data.
2. The invention comprises a pre-coding module to eliminate the correlation between the front and rear symbols of the multipath parallel low-speed source signals through pre-coding, and introduces controllable inter-code crosstalk by combining the adjustment of the equalizer on the basis of the pre-coding module, so that the channel and the equalizer can work cooperatively, part of channel loss becomes a part of generating duobinary data signals, the requirements on signal bandwidth and the performance of the subsequent equalizer are effectively reduced, and the problems of complex traditional blind self-adaptive algorithm and low equalization intensity can be solved.
Drawings
Fig. 1 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a feedforward equalizer FFE according to an embodiment of the present invention.
Fig. 3 is a schematic circuit diagram of a continuous-time linear equalizer CTLE according to an embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a bias voltage generating circuit according to an embodiment of the invention.
Fig. 5 shows the amplitude-frequency characteristic of CTLE under different Rs in the embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of an adjustable degeneration resistor Rs according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of an adaptive adjustment circuit according to an embodiment of the invention.
Fig. 8 is a schematic diagram of a two-tap half-rate decision feedback equalizer DFE according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a channel return loss (S11) according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of channel insertion loss (S21) in an embodiment of the invention.
Fig. 11 is an output eye diagram of a signal after passing through a channel in an embodiment of the present invention.
FIG. 12 shows an adjustable degeneration resistor R in accordance with an embodiment of the present invention S Is a convergence curve of (a).
Fig. 13 is a convergence curve of DFE tap coefficients in an embodiment of the invention.
Fig. 14 is a signal waveform before CTLE equalization of a continuous-time linear equalizer according to an embodiment of the present invention.
Fig. 15 is a signal waveform of CTLE equalized by continuous time linear equalizer according to an embodiment of the present invention.
Fig. 16 is an eye diagram of signals before and after CTLE equalization of a continuous-time linear equalizer according to an embodiment of the present invention.
Detailed Description
Duobinary Data (DB) is essentially a three-level modulation scheme, which was first proposed by Lender in 1963, developed rapidly in the next few decades, and has received much attention to date, and has received much attention in the optical field. In order to convert the NRZ signal into the DB signal, it is necessary to delay-add the current NRZ symbol ("+1" or "-1") to the previous symbol, following the function H (z) =1+z -1 The DB signal is generated with three levels ("-1", "0" and "+1") and the signal jumps from "+1" to "+1" must pass through the intermediate "0" level signal and vice versa. Thus, the fastest rising and falling edges of the signal are eliminated, and the bandwidth of the signal is reduced to half that of the NRZ signal. In order to reduce power consumption and meet the requirement of a high-loss channel, the embodiment provides a 56 Gb/s-based duobinary coding technology. As shown in fig. 1, the duobinary data transmission apparatus for controlling inter-code crosstalk of this embodiment includes a transmitter, where the transmitter includes:
the pre-coding module is used for eliminating the correlation between the front and rear symbols of the multipath parallel low-speed source signals through pre-coding;
a feedforward equalizer FFE for performing channel loss compensation;
the parallel-serial conversion module is used for synthesizing the multipath parallel low-speed source signals into a plurality of paths of serial high-speed signals with fewer numbers;
the high-speed synthesizer is used for synthesizing the multi-path serial high-speed signals into one path of data stream;
a transmission driving circuit for outputting the data stream in the form of duobinary data;
a clock unit for providing a clock signal based on an externally input clock source;
the device comprises a pre-coding module, a feedforward equalizer FFE, a parallel-serial conversion module, a high-speed synthesizer and a transmitting driving circuit, wherein the input end of the pre-coding module is used for being connected with a signal generating module, the output of the transmitting driving circuit is used for outputting the duobinary data obtained after coding, and the output end of a clock unit is respectively connected with the clock signal input ends of the pre-coding module, the feedforward equalizer FFE, the parallel-serial conversion module and the high-speed synthesizer.
The signal generating module in fig. 1 is a signal source of the transmitter, which may be integrated in the transmitter or may be independent from the transmitter, and is only shown in this embodiment as being integrated in the transmitter.
In this embodiment, the parallel-serial conversion module is a 64:4 parallel-serial conversion module, so as to synthesize 64 parallel low-speed source signals into 4 serial high-speed signals; the high-speed synthesizer is a 4:1 high-speed synthesizer and is used for synthesizing 4 paths of serial high-speed signals (14 Gb/s high-speed serial signals) into one path of data stream (56 Gb/s Pre_DB signals).
In this embodiment, the functional expression of the input and output of the feedforward equalizer FFE is:
in the above formula, y (n) is an output signal, x (n-i) is an input signal of the ith tap, C i For the i-th tap coefficient, N is the number of taps.
The feedforward equalizer FFE is a linear equalizer that functions like an FIR filter and corrects a signal by superposition of components of the waveform itself. FFE has the advantages of simple structure and noiseless amplification; the disadvantages are that it attenuates low frequency components and that it has limited ability to cancel severe intersymbol interference. The functional expression of the feed forward equalizer FFE inputs and outputs is:
in the above, C i Is the tap coefficient of FFE. The input signal x (n) is after a series of delays, the delayed input signal x (n-i) is multiplied by the tap coefficient C i () And finally, summing to obtain an output y ().
As shown in fig. 2, the feedforward equalizer FFE in the present embodiment is a 4-tap feedforward equalizer, which is implemented by a voltage-mode logic circuit CML, and the 4-tap feedforward equalizer includes: four tail current sources and load resistor R L NMOS tube M with 4 groups of symmetrical structures 1 ～M 8 Differential output signal TX_OUT of pre-coding module P [n]、TX_OUT N [n]Respectively through a load resistor R L Is connected with a power supply VDD and is connected with an NMOS tube M 1 ～M 8 Is connected with the drain electrode of NMOS tube M 1 ～M 8 Each group of NMOS tubes is connected with a tail current source by taking the group as a unit, the tail current source is used for updating tap coefficients by changing the transconductance of the NMOS tubes of the corresponding group by changing the current magnitude, and the grid electrodes of the 4 groups of NMOS tubes are respectively connected with four paths of differential DATA signals DATA output by a pre-coding module P [n-2～n+1]And DATA N [n-2～n+1]One path of the N-channel metal oxide semiconductor (NMOS) transistors is connected, and the drains of the 4 groups of NMOS transistors are overlapped and then respectively pass through another load resistor R L Output FFE_OUT P [n],FFE_OUT N [n]Two differential signals.
In this embodiment, the clock unit includes a pll PPL and 4 sets of divide-by-two dividers, where an input end of the pll PPL is connected to an external clock source, an output end of the pll generates a 14G clock signal, and 4 divide-by-two dividers generate 875M clock signals, which are respectively connected to the pre-coding module and the front partThe feed equalizer FFE, the parallel to serial conversion module are connected and the output of the phase locked loop PPL is connected to the clock signal input of the high speed synthesizer for providing the high speed synthesizer with a 14G clock signal. The input signal of the 4-tap feedforward equalizer at the current time t is V i (t) the output signal is V o (t) the output signal can be expressed as:
V o ()＝[g 3 V i (+T)+g 2 V i ()+g 1 V i (-T)+g 0 V i (-2T)]R L ，
in the above, g 0 ～g 3 Transconductance values of MOS tubes, V i (+T) is the input signal at time t+T, V i (-T) is the input signal at time T-T, V i (-2T) is the input signal at time T-2T, R L Is a load resistance; r is R L Substituting the above formula, there are:
V o ()＝C 3 V i (+T)+C 2 V i ()+C 1 V i (-T)+C 0 V i (-2T)，
in the above, C 0 ～C 3 Tap coefficients of the 4-tap feedforward equalizer are respectively changed by controlling the current magnitudes of four tail current sources to change the value of the transconductance of the triode, so that the tap coefficient C of the 4-tap feedforward equalizer can be changed 0 ～C 3 。
Referring to fig. 1, the present embodiment further includes a receiver, including:
a receiving driving circuit for input matching and electrostatic discharge;
a continuous time linear equalizer CTLE for implementing duobinary signal modulation in combination with a channel and providing equalization processing;
the variable gain amplifier VGA is used for adjusting the dynamic range of a signal, adjusting the amplitude of an output signal to be suitable for the working range of a subsequent decision feedback equalizer and realizing the function of stabilizing the power of the output signal;
the feedback weighing instrument DFE is used for carrying out equalization processing on the duobinary signal so as to eliminate residual inter-code crosstalk in post-label processing;
the slicer is used for judging the DFE output signal and inputting the DFE output signal as an ideal signal into the adaptive equalization algorithm to realize the adaptive updating of the tap coefficient of the decision feedback equalizer;
a clock recovery circuit for generating a clock signal;
the input end of the receiving driving circuit is connected with an input signal source, the output end of the receiving driving circuit sequentially outputs a decoding signal Dn to a corresponding signal receiving module through a continuous time linear equalizer CTLE, a variable gain amplifier VGA, a judgment feedback equalizer DFE and a slicer, and the output end of the clock recovery circuit is respectively connected with clock signal input ends of the judgment feedback equalizer DFE and the slicer.
The continuous-time linear equalizer CTLE is an analog equalization mode frequently used by the receiving end, and because the channel has a low-pass characteristic, the continuous-time linear equalizer CTLE belongs to a high-pass filter, so that the continuous-time linear equalizer CTLE equalizes signals by attenuating low frequencies and increasing high frequencies, and the characteristic opposite to the channel characteristic can be utilized to compensate the channel bandwidth and offset the channel attenuation. Since the conventional continuous-time linear equalizer CTLE changes the gain range by adjusting the degeneration resistor Rs and the degeneration capacitor Cs, the CTLE of the source degeneration CML structure composed of only NMOS cannot provide a larger transconductance gm, and the equalization strength is insufficient in a high-loss channel smaller than-35 dB. In view of the above, the continuous-time linear equalizer CTLE of the present embodiment is a continuous-time linear equalizer CTLE with a complementary symmetrical structure.
As shown in FIG. 3, the CTLE of the continuous-time linear equalizer with the complementary symmetrical structure comprises a PMOS tube M p1 ～M p4 NMOS tube M n1 ～M n4 Adjustable degenerated resistance R S Degradation capacitance C S For generating bias voltage V BP And bias voltage V Bn Bias voltage generating circuit of PMOS tube M p3 PMOS tube M p1 NMOS tube M n1 NMOS tube M n3 The PMOS tube M is connected in series between the power supply VDD and the ground GND through the end-to-end connection of the source electrode and the drain electrode p4 PMOS tube M p2 NMOS tube M n2 NMOS tube M n4 By source and drainThe PMOS tube M is connected end to end and connected in series between the power supply VDD and the ground GND p3 And PMOS tube M p4 The grid electrode of the two is connected with the bias voltage V BP A group of adjustable degenerated resistors R are connected in parallel between the drain electrodes S And a degenerate capacitance C S PMOS tube M p1 NMOS tube M n1 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IP PMOS tube M p2 NMOS tube M n2 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IN NMOS tube M n3 And NMOS tube M n4 The grid electrode of the two is connected with the bias voltage V Bn Another group of adjustable degenerated resistors R are connected in parallel between the drain electrodes S And a degenerate capacitance C S 。
PMOS tube M p1 ～M p4 NMOS tube M n1 ～M n4 Adjustable degenerated resistance R S Degradation capacitance C S The transconductance is increased and the gain of the equalizer is improved by the combination of the PMOS and NMOS differential transistor pairs. As shown in FIG. 3, left complement g m The circuit is composed of PMOS and NMOS differential transistor pairs to increase the total g m . In order to make CTLE have good linearity, the transconductance values of PMOS and NMOS should be kept close during design. Bias voltage generating circuit with CTLE on right side provides proper bias voltage for CTLE circuit with complementary symmetrical structure, g mn1 Transconductance of NMOS, g mp1 Is the transconductance of PMOS. When g mn1 ＝g mp1 ＝g m When the CTLE output function of the complementary symmetrical structure is expressed as:
in the above, g m Representing the transconductance of MOS tube, R S And C S Respectively represents an adjustable degradation resistance and a degradation capacitance, C L And R is L Respectively represent load resistance and load capacitance, L S Indicating the magnitude of the inductive peaking inductance.
As shown in fig. 4, the bias voltage generating circuit includes a resistor R, NMOS pipe M 5 ～M 8 And M 12 PMOS tube M 9 ～M 11 Current source I bias PMOS tube M 10 And PMOS tube M 9 One end of the resistor is connected with the power supply VDD through series connection, and the other end sequentially passes through the resistor R, NMOS tube M 7 And NMOS tube M 5 The path formed by connecting the source electrode and the drain electrode in series is grounded, and the current source I bias Is connected with the power supply VDD and the output end outputs the bias voltage V Bn And respectively with NMOS tube M 5 ～M 6 And M 12 Is connected with the grid electrode of NMOS tube M 12 Source drain electrode of (2) is grounded, PMOS tube M 11 The source and drain electrodes of the transistor are connected with the power supply VDD, the grid electrode and the PMOS tube M 10 Connected to the gate of (C) and outputting a bias voltage V BP NMOS tube M 7 And M 8 PMOS tube M 9 The grid electrode of (C) is respectively connected with a power supply V CM Connected with PMOS tube M 11 The grid electrode of (C) is also connected with the PMOS tube M 9 Is connected to the drain of the transistor.
In this embodiment, the complementary topology of the continuous time linear equalizer CTLE with complementary symmetrical structure requires a higher power supply voltage, but the power consumption can be reduced by 1/2 because the current flowing through the NMOS and PMOS transistors is the same. This scheme requires 20% higher supply voltage than the NMOS only scheme to keep both devices in saturation. Combining lower current with higher supply voltage saves about 40% of power. The output of the resistor array can be adaptively controlled to realize the adjustment of the equalization intensity, and the capacitor array can be manually controlled. However, at a high-speed data of 56Gbps, when the data frequency of the receiving end is not changed, the value of the degradation capacitor Cs is not changed. Fig. 5 shows the amplitude-frequency characteristic of CTLE at different resistance values.
In this embodiment, the adjustable degeneration resistor R S The resistor comprises a plurality of resistor branches which are connected in parallel and have different resistance values, wherein each resistor branch comprises a switching tube and resistors which are connected in series at two sides of the switching tube and have the same resistance value. As shown in FIG. 6, wherein (a) is a PMOS tube M p3 And PMOS tube M p4 The grid electrode of the two is connected with the bias voltage V BP Adjustable degenerated resistance R connected in parallel between drain electrodes S Switch tube R S <0>～R S <3>The resistance values of the two sides are the sameThe resistances are respectively 50, 100, 200 and 400 ohms, and correspond to four resistance values of 100, 200, 400 and 800 ohms. (b) Is NMOS tube M n3 And NMOS tube M n4 Another group of adjustable degenerated resistors R connected in parallel between the two drains S Switch tube-! R is R S <0>～R S <3>The resistances with the same resistance values at two sides are respectively 50, 100, 200 and 400 ohms, and correspond to 100, 200, 400 and 800 ohms. Switch tube-! R is R S <0>～R S <3>And a switching tube R S <0>～R S <3>Is opposite to the control level of (c).
As shown in fig. 1, the present embodiment further includes a first adaptive circuit for updating the bias voltage of the continuous-time linear equalizer CTLE to implement adaptive channel shaping, where the first adaptive circuit updates the bias voltage of the continuous-time linear equalizer CTLE as a function expression:
dlev(n+1)＝dlev(n)+ CTLE e(n)·d()，
in the above formula, dlev (n+1) is the bias voltage at time n+ 1, dlev (n) is the bias voltage at time n, μ CTLE As the iteration factor, d (n) is the ideal signal replaced after the feedback equalizer DFE is judged at the moment of n, and e (n) is the error signal of the output result of the continuous time linear equalizer CTLE at the moment of n. In this embodiment, when a signal arrives at a receiving end through a channel, output results "2", "1" and "0" signals are determined by a judgment feedback equalizer DFE, and an error signal e (n) is calculated, and the processing method does not need to obtain an accurate value of the data of the receiving end, only needs to make the processed data satisfy the judgment result, and can be expressed as:
where x (n) represents the output of the continuous time linear equalizer CTLE.
As shown in fig. 1, the present embodiment further includes a second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE, where the functional expression of the second adaptive circuit for updating the tap coefficients of the decision feedback equalizer DFE is:
in the above formula, w (n+1) is the tap coefficient at time n+ 1, w (n) is the tap coefficient at time n, μ DFE As a result of the iteration factor,
and E (n) is an error signal between d (n) at the time of n and an output result of the continuous time linear equalizer CTLE, d (n-1) is an ideal replacing signal judged by the feedback equalizer DFE at the time of n-1, and d (n) is an ideal replacing signal judged by the feedback equalizer DFE at the time of n.
The output y (n) of the decision feedback equalizer DFE at time n can be expressed as:
y(n)＝x(n)-d(n-1)w(n-1)，
in the above formula, x (n) is an input signal for judging the feedback weighing apparatus DFE at the time n, d (n-1) is an ideal replacement signal after the feedback weighing apparatus DFE is judged at the time n-1, and w (n-1) is a tap coefficient for judging the feedback weighing apparatus DFE at the time n-1.
Thus, the error signal E (n) between d (n) at time n and the output result of the decision feedback equalizer DFE can be expressed as:
E(n)＝d()-y(n)＝d()-x(n)+d(-1)(-1)，
the gradient of the mean square error function can be expressed as:
according to the steepest descent method, the weight coefficient vector of the "next moment" should be equal to the proportional term of the weight vector of the "current moment" plus a negative mean square error gradient, then there are:
the formula for updating the tap coefficients can thus be written as:
the mean square error is a quadratic function of a weight coefficient vector, which is a concave paraboloid with a unique minimum value, and the wiener optimal solution of the decision feedback equalizer DFE can be obtained by using the steepest descent method.
As shown in fig. 7, the decision feedback equalizer DFE in this embodiment is two-tap (including tap coefficient w 1 、w 2 ) Thus the first adaptive circuit is shown in fig. 7 (a) and the second adaptive circuit is shown in fig. 7 (b).
As shown in fig. 7 (a), the first adaptive circuit calculates μ by two multipliers CTLE e (n) d (n), and mu CTLE e (n) d (n) is summed with the bias voltage at time n by an adder to obtain the bias voltage at time n+ 1.
The output y (n) of the decision feedback equalizer DFE at time n can be expressed as:
y(n)＝(n)-(n-1)w 1 (n-1)-(n-2)w 2 (n-2)，
in the above, x (n) is a signal for judging the feedback weighing instrument DFE at the time n, d (n-1) and d (n-2) are ideal replacing signals after the feedback weighing instrument DFE is judged at the time n-1 and the time n-2 respectively, and w 1 (-1) determining the tap coefficient, w, of the feedback equalizer DFE at time n-1 2 (-2) determining the tap coefficient of the feedback equalizer DFE at the time n-2;
as shown in fig. 7 (b), the second adaptive circuit first calculates d (n) at time n by a subtractor, error signal E (n) between the output results of decision feedback equalizer DFE, and then each and the iteration factor (μ) by a multiplier, respectively DFE1 Sum mu DFE2 ) Multiplying, multiplying the multiplied signal with a substitute ideal signal d (n-1) judged by the DFE at the moment of n-1 through a multiplier, finally, the tap coefficient at time n+1 is obtained by summing the tap coefficient at time n by an adder, which can be expressed as:
w 1 (n+1)＝ 1 ()-2 DFE1 E(n)d(n-1)，
w 2 (n+1)＝ 2 ()-2 DFE2 E(n)d(n-1)，
in the above, w 1 (n+1)、w 2 (n+1) each represents two tap coefficients, w, at the next time 1 (n)、w 2 (n) is two tap coefficients, μ at the current time DFE And E (n) is an error signal between d (n) at the moment n and an output result of the decision feedback equalizer DFE, and d (n-1) is an ideal signal replaced by the decision of the decision feedback equalizer DFE at the moment n-1. Different from FFE and CTLE, the judgment feedback equalizer DFE belongs to a nonlinear equalizer, can effectively eliminate the post-label, and has strong anti-noise and anti-crosstalk capabilities. As shown in fig. 8, the feedback equalizer DFE is a two-tap half-rate feedback equalizer DFE in this embodiment, the two-tap half-rate feedback equalizer DFE includes a combiner MUX, a buffer and two half-rate data paths (the working frequency is half of the data rate), each half-rate data path is serially provided with an adder and two cascaded master-slave D flip-flops, and each half-rate data path is further provided with a first multiplier for integrating the tap coefficient C 2 And the output of the second master-slave D flip-flop after the delay is multiplied by a second input of the adder, a second multiplier for multiplying the tap coefficient C 1 The output of the first master-slave D trigger after time delay is multiplied by a third input of an adder serving as the other half-rate data path, the first input of the adder is an original input signal of the two-tap half-rate judgment feedback weighing instrument DFE, the adder sums the three inputs to serve as the input of the first master-slave D trigger, an Odd signal Odd and an Even signal Even are respectively obtained through the second master-slave D trigger of the two half-rate data paths, the Odd signal Odd and the Even signal Even are synthesized through a combiner MUX in a 2:1 mode, and then are buffered and output through a buffer, and clk is a clock signal of the master-slave D trigger.
In order to verify the performance of the equalizer, in this embodiment, models are built in MATLAB and Cadence, respectively, for simulation and verification. The invention is based on TSMC 28nm technology, and build the circuit shown in fig. 1 under Cadence IC software platform. The actual-35 dB channel parameters were introduced for verification, and the channel return loss (S11) and insertion loss (S21) among the channel parameters are shown in fig. 9 and 10. The PRBS generator of the transmitter generates an NRZ signal at a rate of 56Gb/s, enters the pre-coding module before passing through the channel module, is pre-emphasized by the FFE of the transmitter, and is sampled and output by the DAC. The eye diagram after the signal passes through the channel is shown in fig. 11, where (a) is the Matlab output eye diagram and (b) is the Cadence output eye diagram. The signal at the receiver generates a DB signal by adaptive CTLE. As shown in fig. 12 and 13, the bias voltage dlev of the CTLE of the conventional continuous-time linear equalizer controls the adjustable degeneration resistor R S Adjustable degenerated resistance R S Stable at around 300 ohms. The tap coefficients of the feedback equalizer DFE are judged to converge within 0.35 us. The waveforms of signals before and after passing through the continuous-time linear equalizer CTLE of this embodiment are shown in fig. 14 and 15, where fig. 14 is a signal waveform before equalization and fig. 15 is a signal waveform after equalization. The eye diagram after CTLE processing of the continuous-time linear equalizer of this embodiment is shown in fig. 16, where (a) is Matlab output eye diagram and (b) is Cadence output eye diagram. The obvious duobinary signal can be seen to indicate that the channel shaping is completed, and the system error rate is 4e-12 after PRBS7 test is carried out by the signal receiving module.
In summary, the duobinary data transmission apparatus with controllable inter-code crosstalk of the present embodiment uses 4-tap FFE for pre-emphasis at the transmitter, and the receiver equalization is composed of a continuous-time linear equalizer (CTLE) with complementary symmetric structure and a Decision Feedback Equalizer (DFE). The gain is changed by adjusting CTLE degeneration resistance and may be combined with partial channel loss for DB signal generation and then into DFE to further cancel inter-symbol interference (ISI). In the aspect of adaptive equalization, by adjusting CTLE control signals and DFE tap coefficients to handle residual inter-symbol interference (ISI), a precoding mode is used to introduce controllable inter-symbol interference during transmission, and the requirements on signal bandwidth and subsequent equalizer performance are low.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (10)
1. A duobinary data transmission apparatus for controllable inter-symbol interference, comprising a transmitter, the transmitter comprising:
the pre-coding module is used for eliminating the correlation between the front and rear symbols of the multipath parallel low-speed source signals through pre-coding;
a feedforward equalizer FFE for performing channel loss compensation;
the parallel-serial conversion module is used for synthesizing the multipath parallel low-speed source signals into a plurality of paths of serial high-speed signals with fewer numbers;
the high-speed synthesizer is used for synthesizing the multi-path serial high-speed signals into one path of data stream;
a transmission driving circuit for outputting the data stream in the form of duobinary data;
a clock unit for providing a clock signal based on an externally input clock source;
the device comprises a pre-coding module, a feedforward equalizer FFE, a parallel-serial conversion module, a high-speed synthesizer and a transmitting driving circuit, wherein the input end of the pre-coding module is used for being connected with a signal generating module, the output end of the transmitting driving circuit is used for outputting the duobinary data obtained after coding, and the output end of a clock unit is respectively connected with the pre-coding module, the feedforward equalizer FFE, the parallel-serial conversion module and the clock signal input end of the high-speed synthesizer.
2. The apparatus for duobinary data transmission of controllable inter-symbol interference according to claim 1, wherein the functional expression of the input and output of the feedforward equalizer FFE is:
in the above formula, y (n) is an output signal, x (n-i) is an input signal of the ith tap, C i For the i-th tap coefficient, N is the number of taps.
3. The apparatus for duobinary data transmission of controllable inter-symbol interference according to claim 2, wherein the feedforward equalizer FFE is a 4-tap feedforward equalizer, the 4-tap feedforward equalizer comprising: four tail current sources and load resistor R L NMOS tube M with 4 groups of symmetrical structures 1 ～M 8 Differential output signal TX_OUT of pre-coding module P [n]、TX_OUT N [n]Respectively through a load resistor R L Is connected with a power supply VDD and is connected with an NMOS tube M 1 ～M 8 Is connected with the drain electrode of NMOS tube M 1 ～M 8 Each group of NMOS tubes is connected with a tail current source by taking the group as a unit, the tail current source is used for updating tap coefficients by changing the transconductance of the NMOS tubes of the corresponding group by changing the current magnitude, and the grid electrodes of the 4 groups of NMOS tubes are respectively connected with four paths of differential DATA signals DATA output by a pre-coding module P [n-2～n+1]And DATA N [n-2～n+1]One path of the N-channel metal oxide semiconductor (NMOS) transistors is connected, and the drains of the 4 groups of NMOS transistors are overlapped and then respectively pass through another load resistor R L Output FFE_OUT P [n],FFE_OUT N [n]Two differential signals.
4. The apparatus of claim 1, wherein the clock unit comprises a pll PPL and 4 sets of frequency dividers, the pll PPL has an input terminal connected to an external clock source, an output terminal generating a 14G clock signal, the 4 frequency dividers generating 875M clock signals respectively connected to the pre-coding module, the feedforward equalizer FFE, and the parallel-to-serial conversion module, and an output terminal connected to a clock signal input terminal of the high-speed synthesizer for providing the 14G clock signal to the high-speed synthesizer.
5. The apparatus for duobinary data transmission of controllable inter-symbol interference of claim 1, further comprising a receiver, the receiver comprising:
a receiving driving circuit for input matching and electrostatic discharge;
a continuous time linear equalizer CTLE for implementing duobinary signal modulation in combination with a channel and providing equalization processing;
the variable gain amplifier VGA is used for adjusting the dynamic range of a signal, adjusting the amplitude of an output signal to be suitable for the working range of a subsequent decision feedback equalizer and realizing the function of stabilizing the power of the output signal;
the feedback weighing instrument DFE is used for carrying out equalization processing on the duobinary signal so as to eliminate residual inter-code crosstalk in post-label processing;
the slicer is used for judging the DFE output signal and inputting the DFE output signal as an ideal signal into the adaptive equalization algorithm to realize the adaptive updating of the tap coefficient of the decision feedback equalizer;
a clock recovery circuit for generating a clock signal;
the input end of the receiving driving circuit is connected with an input signal source, the output end of the receiving driving circuit sequentially outputs a decoding signal Dn to a corresponding signal receiving module through a continuous time linear equalizer CTLE, a variable gain amplifier VGA, a judgment feedback equalizer DFE and a slicer, and the output end of the clock recovery circuit is respectively connected with clock signal input ends of the judgment feedback equalizer DFE and the slicer.
6. The apparatus of claim 5, wherein the continuous-time linear equalizer CTLE is a complementary-symmetric continuous-time linear equalizer CTLE, and the complementary-symmetric continuous-time linear equalizer CTLE comprises a PMOS tube M p1 ～M p4 NMOS tube M n1 ～M n4 Adjustable degenerated resistance R S Degradation capacitance C S For generating bias voltage V BP And bias voltage V Bn Bias voltage generating circuit of PMOS tube M p3 PMOS tube M p1 NMOS tube M n1 NMOS tube M n3 The PMOS tube M is connected in series between the power supply VDD and the ground GND through the end-to-end connection of the source electrode and the drain electrode p4 PMOS tube M p2 NMOS tube M n2 NMOS tube M n4 The PMOS tube M is connected in series between the power supply VDD and the ground GND through the end-to-end connection of the source electrode and the drain electrode p3 And PMOS tube M p4 The grid electrode of the two is connected with the bias voltage V BP A group of adjustable degenerated resistors R are connected in parallel between the drain electrodes S And a degenerate capacitance C S PMOS tube M p1 NMOS tube M n1 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IP PMOS tube M p2 NMOS tube M n2 The grid electrodes of the two are connected with input differential signals V IN And V IP Signal V in (a) IN NMOS tube M n3 And NMOS tube M n4 The grid electrode of the two is connected with the bias voltage V Bn Another group of adjustable degenerated resistors R are connected in parallel between the drain electrodes S And a degenerate capacitance C S The adjustable degeneration resistor R S The resistor comprises a plurality of resistor branches which are connected in parallel and have different resistance values, wherein each resistor branch comprises a switching tube and resistors which are connected in series at two sides of the switching tube and have the same resistance value.
7. The apparatus of claim 6, wherein the bias voltage generating circuit comprises a resistor R, NMOS M 5 ～M 8 And M 12 PMOS tube M 9 ～M 11 Current source I bias PMOS tube M 10 And PMOS tube M 9 One end of the resistor is connected with the power supply VDD through series connection, and the other end sequentially passes through the resistor R, NMOS tube M 7 And NMOS tube M 5 The path formed by connecting the source electrode and the drain electrode in series is grounded, and the current source I bias Is connected with the power supply VDD and the output end outputs the bias voltage V Bn And respectively with NMOS tube M 5 ～M 6 And M 12 Is connected with the grid electrode of NMOS tube M 12 Source drain electrode of (2) is grounded, PMOS tube M 11 The source and drain electrodes of the transistor are connected with the power supply VDD, the grid electrode and the PMOS tube M 10 Connected to the gate of (C) and outputting a bias voltage V BP NMOS tube M 7 And M 8 PMOS tube M 9 The grid electrode of (C) is respectively connected with a power supply V CM Connected with PMOS tube M 11 The grid electrode of (C) is also connected with the PMOS tube M 9 Is connected to the drain of the transistor.
8. The apparatus for duobinary data transmission of controllable inter-symbol interference of claim 5, further comprising a first adaptive circuit for updating the bias voltage of the continuous-time linear equalizer CTLE to achieve adaptive channel shaping, wherein the first adaptive circuit updates the function expression of the bias voltage of the continuous-time linear equalizer CTLE as:
dlev(n+1)＝dlev(n)+ CTLE e(n)·d()，
in the above formula, dlev (n+1) is the bias voltage at time n+1, dlev (n) is the bias voltage at time n, μ CTLE As the iteration factor, d (n) is the ideal signal replaced after the feedback equalizer DFE is judged at the moment of n, and e (n) is the error signal of the output result of the continuous time linear equalizer CTLE at the moment of n.
9. The apparatus for duobinary data transmission of controllable inter-symbol interference of claim 8, further comprising a second adaptive circuit for updating tap coefficients of the decision feedback equalizer DFE, the second adaptive circuit updating a functional expression of the tap coefficients of the decision feedback equalizer DFE as:
in the above formula, w (n+1) is the tap coefficient at time n+1, w (n) is the tap coefficient at time n, μ DFE As a result of the iteration factor,
for the gradient of the mean square error function, E (n) is the error signal between d (n) at the time of n and the output result of the continuous time linear equalizer CTLE, d (n-1) is the ideal replacement signal after the feedback equalizer DFE judgment is judged at the time of n-1, and d (n) is the time of n judgment feedbackReplacing ideal signal after the decision of the weighing apparatus DFE.
10. The apparatus of claim 5, wherein the DFE is a two-tap half-rate DFE comprising a combiner MUX, a buffer, and two half-rate data paths, each half-rate data path having an adder and two cascaded master-slave D flip-flops in series, and each half-rate data path further having a first multiplier for adding tap coefficient C 2 And the output of the second master-slave D flip-flop after the delay is multiplied by a second input of the adder, a second multiplier for multiplying the tap coefficient C 1 The output of the first master-slave D trigger after time delay is multiplied by a third input of an adder serving as the other half-rate data path, the first input of the adder is a two-tap half-rate judgment feedback weighing instrument DFE original input signal, the adder sums the three inputs to serve as the input of the first master-slave D trigger, an Odd signal Odd and an Even signal Even are respectively obtained through the second master-slave D trigger of the two half-rate data paths, and the Odd signal Odd and the Even signal Even are synthesized through a combiner MUX in a 2:1 mode and then are buffered and output through a buffer.
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