CN116346134A - Analog-to-digital converter - Google Patents

Abstract

The invention discloses an analog-to-digital converter, comprising: a capacitive digital-to-analog converter that generates a residual voltage at an upper plate thereof by switching; the input end of the integrating circuit is coupled with the upper polar plate of the capacitive digital-to-analog converter so as to store residual voltage generated by the capacitive digital-to-analog converter; the comparator is used for quantizing the summation signals of the residual voltage generated by the capacitive digital-to-analog converter in the current period and the residual voltages of all periods before the current period stored by the integrating circuit into digital codes; the SAR logic control circuit is used for controlling the switching of the capacitive digital-to-analog converter based on the digital code and continuously generating each bit of output in a successive approximation mode; and a digital circuit for obtaining a digital output signal corresponding to the input voltage signal based on the conversion result of the SAR logic control circuit. The ADC of the invention has faster conversion speed, lower power consumption, smaller area and higher resolution.

Description

Analog-to-digital converter

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to an analog-to-digital converter.

Background

The analog-to-digital converter (Analog to Digital Converter, ADC) is a device capable of converting continuous analog signals into discrete digital signals that can be processed by a computer, and is a key component of an interface between an analog system and a digital system, and has been widely used in fields of radar, communication, measurement and control, medical treatment, instruments, images, audio and the like for a long time. With the continuous development of modern technology, the requirements of these fields on speed and resolution are continuously raised, and the requirements of an analog-to-digital converter are also higher and higher.

Currently, analog-to-digital converters are mainly divided into two main categories: nyquist analog-to-digital converter and oversampling analog-to-digital converter. One of the most representative types of nyquist analog-to-digital converters is a successive approximation analog-to-digital converter (Successive Approximation Register ADC, SAR ADC). The SAR ADC mainly adopts a digital logic unit structure, and as shown in fig. 1, the SAR ADC100 includes a sample-and-hold circuit 110, a register comparator 120, a SAR logic control circuit 130, and a capacitive digital-to-analog converter (ADAC) 140. The sample-hold circuit 110 samples the analog input signal Vin according to the sampling clock and provides the sampled analog input signal Vin to the register comparator 120, the register comparator 120 compares the analog input signal Vin with the analog voltage amount generated by the capacitive digital-to-analog converter 140, the SAR logic control circuit 130 generates a logic control signal according to the comparison result of the register comparator 120, and the feedback control capacitive digital-to-analog converter 140 generates a new analog voltage amount to approach the analog input signal until the analog voltage amount is approximately equal to the analog input signal, and the digital output corresponding to the analog voltage amount is the output Dout of the SAR ADC 100. The SAR ADC has a simple structure and higher efficiency and speed, but due to the existence of comparator noise and DAC establishment errors, the accuracy of the SAR ADC is generally limited to be in the range of 8-12 bits, so the SAR ADC is widely applied to the fields of medium speed and medium accuracy.

The most widely used oversampling analog-to-digital converter is a sigma-delta ADC, whose block diagram is shown in fig. 2, the sigma-delta ADC200 comprising a sigma-delta modulator and a digital filtering and decimation circuit 250, the sigma-delta modulator comprising an adder 210, an integrator 220, a register comparator 230, and a feedback loop comprising a 1-bit DAC240 (the DAC being a simple switch, the negative input of the differential amplifier being connected to a positive or negative reference voltage), the purpose of the feedback DAC being to maintain the average output of the integrator close to the reference level of the comparator. The sigma-delta modulator samples the input signal Vin at an extremely high sampling frequency and low-order quantizes the difference between the two samples to obtain a 1-bit data stream represented by a low-order number, which is then decimated by a digital filter and decimator circuit 250 to obtain a high-resolution linear pulse code modulated digital signal Dout. Oversampling and noise shaping techniques are two key techniques applied in sigma-delta modulators that respectively reduce and largely remove in-band noise, enabling a significant increase in the accuracy of the analog-to-digital converter. But the high oversampling ratio required for the 1-bit quantizer to suppress quantization noise limits the conversion speed and requires a long conversion time.

In order to obtain a high resolution and fast stable ADC, the prior art proposes a multi-bit quantized sigma-delta ADC based on a 1-bit quantized sigma-delta ADC, but this structure requires a dynamic element matching technique to reduce the effect of mismatch, thus requiring a more complex circuit design and higher power consumption. On the other hand, based on the advantage of rapid stability of the SAR ADC, the prior art further proposes an incremental scaling type Σ - Δ ADC, which uses the SAR ADC as a coarse quantization ADC, and the conversion result is used for dynamically adjusting the reference voltage of the Σ - Δ ADC, so as to greatly reduce the quantization error of the Σ - Δ ADC, and has the advantages of high resolution and low power consumption, but the disadvantage is that the digital circuit has a complex structure, the conversion speed is still slower, and a long conversion time is required.

Disclosure of Invention

In view of the above, an object of the present invention is to provide an analog-to-digital converter that can simultaneously achieve both resolution and conversion speed.

According to an embodiment of the present invention, there is provided an analog-to-digital converter including: a capacitive digital-to-analog converter that generates a residual voltage at an upper plate thereof by switching; an integrating circuit, the input end of which is coupled with the upper polar plate of the capacitance type digital-to-analog converter to store residual voltage generated by the capacitance type digital-to-analog converter; the input end of the comparator is coupled with the output end of the integrating circuit, and the comparator is used for quantizing the summation signal of the residual voltage generated by the capacitive digital-to-analog converter in the current period and the residual voltage stored in the integrating circuit in the previous period into a digital code; the input end of the SAR logic control circuit is coupled with the output end of the comparator and is used for controlling the switching of the capacitive digital-to-analog converter based on the digital code, and each bit of output is continuously generated in a successive approximation mode until the quantization is finished; and a digital circuit for obtaining a digital output signal corresponding to the input voltage signal based on a conversion result of the SAR logic control circuit.

Optionally, each cycle of the analog-to-digital converter is divided into a sampling phase and a conversion phase, the capacitive digital-to-analog converter is configured to store the input voltage signal on a plurality of capacitors thereof in the sampling phase, and switch based on the SAR logic control circuit in the conversion phase to generate an approximation voltage of a current cycle, and to difference the approximation voltage from the input voltage signal to generate a residual voltage of the current cycle.

Optionally, the integrating circuit includes: a first end of the first capacitor is coupled with an upper polar plate of the capacitive digital-to-analog converter; an operational amplifier, the input end of which is coupled with the second end of the first capacitor, and the output end of which is coupled with the input end of the comparator; and a first switch and a second capacitor coupled between a first end of the first capacitor and an output of the operational amplifier, wherein the first switch is configured to conduct during the transition phase of each cycle to store the residual voltage on the second capacitor.

Optionally, the integrating circuit further includes: a second switch coupled between the input and the output of the operational amplifier; and a third switch having a first end coupled to the first end of the first capacitor and a second end grounded, wherein the second switch and the third switch are configured to be turned on during a sampling phase of each cycle, and to connect the operational amplifier in a unity gain form to store an offset voltage of the operational amplifier on the first capacitor.

Optionally, the operational amplifier is implemented by an inverter.

Optionally, the digital circuit is configured to sum and average N conversion results of the SAR logic control circuit after N conversions to obtain the digital output signal, N being an integer greater than 1.

In summary, the embodiment of the invention provides a novel SAR ADC based on the sigma-delta ADC residue accumulation idea, which quantizes the summation signal obtained by accumulating the residue voltage generated by the capacitive digital-to-analog converter in the conversion of multiple periods to obtain the digital code.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a successive approximation type analog-to-digital converter;

fig. 2 shows a schematic diagram of a sigma-delta analog-to-digital converter;

fig. 3 shows a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;

fig. 4 shows an operation timing diagram of the analog-to-digital converter according to the embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.

Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected" or "coupled" to another element or being "connected" or "coupled" between two nodes, it can be directly coupled or connected to the other element or intervening elements may also be present, and the connection or coupling between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Fig. 3 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention, and as shown in fig. 3, an analog-to-digital converter 300 according to the present invention includes: a capacitive digital-to-analog converter (CDAC) 301, an integrating circuit 302, a comparator 303, a SAR logic control circuit 304, and a digital circuit 305.

Wherein the capacitive digital-to-analog converter 301 is configured to generate a residual voltage at its upper plate by switching. The input end of the integrating circuit 302 is coupled to the upper plate of the capacitive digital-to-analog converter 301 to store the residual voltage of the previous period generated by the capacitive digital-to-analog converter 301. An input of the comparator 303 is coupled to an output of the integrating circuit 302, and the comparator 303 is configured to quantize a sum signal of the residual voltage generated by the capacitive digital-to-analog converter 301 in the current period and the residual voltage stored in the integrating circuit 302 in the previous period into a digital code. An input terminal of the SAR logic control circuit 304 is coupled to an output terminal of the comparator 303, and is configured to control the switching of the capacitive digital-to-analog converter 301 based on the digital code, and continuously generate an output of each bit in a successive approximation manner until quantization is completed. The digital circuit 305 is configured to output a digital output signal Dout corresponding to the input voltage signal Vin based on the conversion result of the SAR logic control circuit.

Further, the analog-to-digital converter 300 of the present embodiment is mainly used for processing signals close to direct current, and the input signal is considered to be unchanged in a complete conversion period, and each period is divided into a sampling phase Φ1 and a conversion phase Φ2, wherein Φ1 and Φ2 are signals which are not overlapped with each other. In the sampling phase φ 1 of the analog-to-digital converter 300, a capacitive digital-to-analog converter 301 is coupled to an input voltage signal Vin to store the input voltage signal Vin on a plurality of capacitors thereon. In the conversion phase Φ2, the SAR logic control circuit 304 controls a part of capacitors in the capacitor array to be coupled to the positive reference voltage vref+ and the rest of capacitors are coupled to the negative reference voltage VREF-, so as to generate an approximation voltage of the current period, and the approximation voltage is differenced from the input voltage signal Vin to generate a residual voltage of the current period, the residual voltage is transmitted to the integrating circuit 302 and summed with the residual voltage of the previous period, the comparator 303 outputs "1" or "0" according to the positive and negative conditions of the sum signal, and the SAR logic control circuit 304 controls the switching condition of the next bit of the capacitive digital-analog converter 301 according to the output of the comparator 303. Thus, under the control of SAR logic control circuit 304, after a number of cycles are completed, a multi-bit conversion result can be obtained. The digital circuit 305 sums the conversion results one by one, and finally after completing N conversions, N is an integer greater than 1, and averages the result to obtain the final digital output signal Dout.

As shown in fig. 3, the capacitive digital-to-analog converter 301 may include a plurality of capacitors, for example, a 6bit SAR ADC, including a plurality of capacitors Cs 1-Cs 64 (where the number of capacitors is 2) ⁶ And a switch array, wherein the switch array includes two switches shown at 311 and 312 and switches Si 1-Si 64 and switches Sj 1-Sj 64. In the capacitive digital-to-analog converter 301, the upper plates of the plurality of capacitors Cs 1-Cs 64 are coupled to each other and the lower plates are coupled to a corresponding plurality of switches for coupling their corresponding capacitors to the positive reference voltage vref+, the input voltage signal Vin, or the negative reference voltage VREF-. Further, a plurality of switches 311 couple the lower plates of the corresponding capacitors to the input voltage signal Vin, respectively, and a plurality of switches 312 couple the lower plates of the corresponding capacitors to the first ends of the switches Si and Sj, respectively, and the second ends of the switches Si and Sj are coupled to the positive reference voltage vref+ and the negative reference voltage VREF-, respectively. At each of theAt the end of the transition phase phi 2 of the cycle, the residual voltage is present at node P1 of the capacitive digital-to-analog converter 301.

The integrating circuit 302 may include capacitors Cc and Ci, an operational amplifier 321, and switches S1 to S3. The first end of the capacitor Cc is coupled to the node P1 of the capacitive digital-to-analog converter 301, the second end of the capacitor Cc is coupled to the input end of the operational amplifier 321, the output end of the operational amplifier 321 is coupled to the negative input end of the comparator 303, and the positive input end of the comparator 303 is grounded. The switch S1 and the capacitor Ci are coupled between the first end of the capacitor Cc and the output terminal of the operational amplifier 321, the switch S2 is coupled between the input terminal and the output terminal of the operational amplifier 321, the first end of the switch S3 is coupled to the first end of the capacitor Cc, and the second end is grounded. Wherein the switch S1 is configured to be turned on during the conversion phase phi 2 of the analog-to-digital converter 300, and the switches S2 and S3 are configured to be turned on during the sampling phase phi 1.

In a further embodiment, the operational amplifier 321 in the integrating circuit 302 may be an operational amplifier based on an inverter, which has a simple structure, a smaller area and lower power consumption.

Fig. 4 shows an operation timing diagram of the analog-to-digital converter according to the embodiment of the invention. The period of the analog-to-digital converter 300 according to the embodiment of the present invention includes a sampling phase Φ1 and a converting phase Φ2, and the principle of the 6-bit analog-to-digital converter according to the embodiment of the present invention is described below with reference to fig. 4.

In the sampling phase Φ1 of the 1 st period, all switches 311 in the capacitive digital-to-analog converter 301 are turned on, all switches 312 are turned off, switch S3 is turned on, the lower plates of the capacitors Cs 1-Cs 64 are connected to the input voltage signal Vin, and the input voltage signal Vin is stored in all capacitors in the capacitive digital-to-analog converter 301 in the form of electric charges. At the same time, the switch S1 is turned off, the switch S2 is turned on, the operational amplifier in the integrating circuit 302 is connected to a unit gain form, and the offset voltage is stored on the capacitor Cc.

In the conversion phase phi 2, all switches 311 in the capacitive digital-to-analog converter 301 are turned off, all switches 312 are turned on, switch S1 is turned on, switches S2 and S3 are turned off, and then portions of the switches Si 1-Si 64 are turned on under the control of the SAR logic circuit, thereby connecting the lower plates of portions of the plurality of capacitors Cs 1-Cs 64 to the positive reference voltage VREF+. Meanwhile, the lower plates of the remaining capacitors of the plurality of capacitors Cs1 to Cs64 are connected to the negative reference voltage VREF-, under the control of the switches Sj1 to Sj64, thereby generating corresponding approximation voltages. According to the principle of conservation of the charge amount on the capacitor, the difference between the input voltage signal Vin and the approximated voltage, i.e. the residual voltage, can be obtained at the node P1. The residual voltage is transferred to the negative input terminal of the comparator 303 through the capacitor Cc in the integrating circuit 302 and the operational amplifier 321, and the comparator 303 outputs a digital code "1" or "0" according to the positive and negative conditions of the residual voltage. For example, if the residual voltage is positive, the comparator 303 outputs a digital code "0", and the residual voltage is stored in the capacitor Ci for use in the comparison of the next cycle.

In the 2 nd period, the operation of the sampling phase φ 1 is similar to that in the 1 st period, namely, the lower plates of the capacitors Cs 1-Cs 64 are connected with the input voltage signal Vin, and the input voltage signal Vin is stored in all the capacitors in the capacitive digital-to-analog converter 301 in the form of charges. In the conversion phase phi 2, all switches 311 in the capacitive digital-to-analog converter 301 are turned off again, all switches 312 are turned on again, and then part of the switches Si 1-Si 64 are turned on, so that the lower plates of part of the capacitors Cs 1-Cs 64 are connected to the positive reference voltage VREF+, and the lower plates of the remaining capacitors are controlled to be connected to the negative reference voltage VREF-through the switches Sj 1-Sj 64. According to the principle of conservation of the charge amount on the capacitor, the residual voltage of the 2 nd period is obtained at the node P1, the sum signal of the residual voltage obtained in the 1 st period and the residual voltage is transmitted to the negative input end of the comparator 303, and the comparator 303 outputs the digital code "1" or "0" according to the positive and negative conditions of the sum signal. For example, if the sum signal is negative, the comparator 303 outputs a digital code "1".

Similarly, under the control of SAR logic, each time 6 comparisons are performed, a 6-bit conversion result is obtained, and after N conversions are completed, the digital circuit 305 sums the conversion results one by one and averages the conversion results to finally obtain a digital output signal Dout. In theory, the resolution of 6+N can be obtained by N times of complete SAR conversion, actually, the number of times of SAR conversion can be appropriately increased, and a more accurate conversion result can be obtained by taking the high order of the digital output signal, and finally, an analog-to-digital converter with high resolution and fast conversion speed can be obtained.

In summary, the embodiment of the invention provides a novel SAR ADC based on the sigma-delta ADC residue accumulation idea, which quantizes the summation signal obtained by accumulating the residue voltage generated by the capacitive digital-to-analog converter in the conversion of multiple periods to obtain the digital code.

It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (6)

1. An analog-to-digital converter, comprising:

a capacitive digital-to-analog converter that generates a residual voltage at an upper plate thereof by switching;

an integrating circuit, the input end of which is coupled with the upper polar plate of the capacitance type digital-to-analog converter to store residual voltage generated by the capacitance type digital-to-analog converter;

the input end of the comparator is coupled with the output end of the integrating circuit, and the comparator is used for quantizing the summation signal of the residual voltage generated by the capacitive digital-to-analog converter in the current period and the residual voltage stored in the integrating circuit in the previous period into a digital code;

the input end of the SAR logic control circuit is coupled with the output end of the comparator and is used for controlling the switching of the capacitive digital-to-analog converter based on the digital code, and each bit of output is continuously generated in a successive approximation mode until the quantization is finished; and

and the digital circuit is used for obtaining a digital output signal corresponding to the input voltage signal based on the conversion result of the SAR logic control circuit.

2. The analog-to-digital converter of claim 1, wherein each cycle of the analog-to-digital converter is divided into a sampling phase and a conversion phase,

the capacitive digital-to-analog converter is configured to store the input voltage signal on a plurality of capacitors thereof during the sampling phase, and to switch based on the SAR logic control circuit during the conversion phase to generate an approximation voltage of a current period, and to make a difference between the approximation voltage and the input voltage signal to generate a remnant voltage of the current period.

3. The analog-to-digital converter of claim 2, wherein the integrating circuit comprises:

a first end of the first capacitor is coupled with an upper polar plate of the capacitive digital-to-analog converter;

an operational amplifier, the input end of which is coupled with the second end of the first capacitor, and the output end of which is coupled with the input end of the comparator; and

a first switch and a second capacitor coupled between a first end of the first capacitor and an output of the operational amplifier, wherein the first switch is configured to conduct during the transition phase of each cycle to store the residual voltage on the second capacitor.

4. The analog-to-digital converter of claim 3, wherein the integrating circuit further comprises:

a second switch coupled between the input and the output of the operational amplifier; and

a third switch having a first end coupled to the first end of the first capacitor and a second end grounded,

the second switch and the third switch are configured to be conducted in a sampling stage of each period, and the operational amplifier is connected in a unit gain mode so as to store an offset voltage of the operational amplifier on the first capacitor.

5. The analog-to-digital converter of claim 4, wherein the operational amplifier is implemented by an inverter.

6. The analog-to-digital converter of claim 1, wherein the digital circuit is configured to sum and average N conversion results of the SAR logic control circuit after N conversions to obtain the digital output signal, N being an integer greater than 1.

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