CN115801003A - Multi-step analog-to-digital converter and implementation method thereof - Google Patents
Multi-step analog-to-digital converter and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a multi-step analog-to-digital converter and an implementation method thereof, wherein the structure of an incremental scaling analog-to-digital converter is improved, and a noise shaping successive approximation analog-to-digital converter is adopted for fine quantization of the analog-to-digital converter; the method comprises the following steps: the digital slope analog-to-digital converter comprises a multi-bit band digital prediction digital slope analog-to-digital converter, a multi-bit multi-order noise shaping successive approximation analog-to-digital converter and a configurable floating voltage domain amplifier. The invention adopts a working mode of sampling once and converting many times, and the quantization process of the analog-digital converter is configured into coarse quantization once and then fine quantization many times; the multi-step analog-to-digital converter has high energy efficiency and high precision, has medium input bandwidth and low data output delay, and can be adapted to various application scenes of the Internet of things.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, relates to the integrated circuit design technology of an analog-digital converter, and particularly relates to a high-energy-efficiency high-precision multistep analog-digital converter structure and an implementation method thereof.
Background
In recent years, the precision and energy efficiency of analog-to-digital converters (ADCs) in emerging application fields such as the internet of things have been more strictly required. Especially in the application of mobile terminal equipment, the high-energy-efficiency successive approximation analog-to-digital converter (sar adc) is limited by the thermal noise of the comparator therein, which often reduces the accuracy of the whole system, while the high-accuracy Sigma-delta adc consumes a large amount of energy, which causes a bottleneck to the endurance time of the equipment battery. Meanwhile, the Sigma-delta adc requires a complex digital processing circuit, and a quantization result of an input analog signal cannot be obtained in real time due to long data delay, which is not favorable for integration in a system. In order to solve the problem that the ADC is difficult to achieve both high precision and high energy efficiency, some new ADC structures such as a Zoom ADC (Zoom ADC) and a noise-shaping successive approximation ADC (noise ADC) have been proposed in recent years by designers.
ZoomADC is a multi-step analog-to-digital converter, which uses a low-power-consumption sar ADC at a first stage and a high-precision Sigma-Delta ADC at a second stage to perform a first-step coarse quantization and a second-step fine quantization on a sampled input signal, respectively. After the coarse quantization is finished, the reference level range of the second-stage Sigma-Delta ADC is adjusted according to the coarse quantization result of the first-stage SARADC, so that the input signal falls in the reduced reference level range, the size of the input signal of the loop filter in the Sigma-Delta ADC is greatly reduced, the power consumption of the loop filter is further reduced, and the high-energy-efficiency fine quantization is realized. However, in order to achieve high precision, the conventional ZoomADC needs a high oversampling rate, so that the second stage Sigma-delta adc performs multiple conversions, but each conversion destroys the residual voltage value stored in the first stage sar adc, and the residual voltage can be recovered by resampling.
The existing NoiseHapingSARADC uses SARADC with low power consumption as a quantizer of a Sigma-Delta ADC, and the characteristic that SARADC can carry out multi-bit quantization is utilized, so that the over-sampling rate is greatly reduced, and the input bandwidth and the applicability of a system are improved. However, because of the absence of the first-stage coarse quantization, the existing noise filtering sar adc usually requires a higher-order loop filter to meet the requirement of high precision at a lower oversampling rate, thereby significantly increasing the hardware overhead and the design complexity.
Therefore, designing an ADC that can be applied to emerging application fields such as the internet of things and that combines high energy efficiency and high precision still has a high challenge.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an energy-efficient high-precision multistep analog-to-digital converter and an implementation method thereof, the multistep analog-to-digital converter circuit is a novel Incremental Zoom analog-to-digital converter (Incremental Zoom ADC) circuit, a noise shaping successive approximation analog-to-digital converter (NoiseShapingSARADC) is adopted to carry out second-stage fine quantization in a Zoom analog-to-digital converter (Zoom ADC), the designed analog-to-digital converter adopts a working mode of once sampling and multiple conversion, high energy efficiency and high precision can be achieved, medium input bandwidth and low data output delay can be achieved, and the multi-internet-of-things application scene can be adapted.
The present invention defines the following term names and corresponding english names:
an incremental scaling analog-to-digital converter (incrementalZoomaDC);
noise-shaping successive approximation type analog-to-digital converter (NoiseHapingSARADC)
A digital ramp-type analog-to-digital converter (digitalslopeodc);
MSB (most significant bit);
LSB (Least Significant Bit);
the invention provides a multi-step analog-to-digital converter, which structurally adopts NoiseHapingSARADC to perform fine quantization in a ZoomaDC system, and provides the effects of performing one-time sampling, then performing one-time coarse quantization and performing multiple times of fine quantization conversion in the ZoomaDC system, thereby achieving the effect of one-time sampling and multiple times of conversion. Therefore, the quantization precision of the zoomADC system is improved, and the power consumption of a fine quantization stage in the zoomADC system is reduced. The invention designs a novel NoiseHapingSARADC implementation mode, which can reduce the hardware overhead and power consumption of the NoiseHapingSAR ADC. The invention adopts a multi-order digital prediction technology on the basis of the Digital SlopeADC, designs the Digital SlopeADC with the multi-order digital prediction technology, and thus reduces the capacitance switching power consumption in the Digital SlopeADC. The invention is improved based on the floating voltage domain amplifier, the configurable floating voltage domain amplifier is designed, the floating voltage domain amplifier can be configured according to different amplifier noise requirements, and the power consumption of the floating voltage domain amplifier is reduced.
The technical scheme of the invention is as follows:
a multi-step analog-to-digital converter, namely the analog-to-digital converter of the incremental type scaling type; the invention improves the ADC structure in the form of an incremental scaling type analog-to-digital converter, and the main improvement lies in that a Noise Shaping SAR ADC is adopted to carry out fine quantization on the ADC in the form. The incremental scaling analog-to-digital converter of the present invention comprises: the digital predictive digital signal source comprises a multi-bit digital predictive DigitalSlopeADC, a multi-bit multi-order NoiseHapingSARADC and a configurable floating voltage domain amplifier; taking a digital predictive Digital SlopeADC with multiple bit bands as a first stage of an ADC system to carry out first-step coarse quantization; taking the multi-bit and multi-order NoiseHapingSARADC as the second stage of the ADC system, and performing second-step fine quantization; a configurable floating voltage domain amplifier is embedded in the second stage for eliminating sampling noise and amplifying the signal between coarse and fine quantization. Wherein the content of the first and second substances,
the digital predictive Digital SlopeADCs and the multi-digit and multi-order NoiseHapingSARADCs share the same digital-to-analog converter (DAC) component, the DAC component is formed by connecting two capacitor array top plates in different coding modes, the two capacitor array top plates are respectively used for the two ADCs, the DAC is called a coarse quantization DAC correspondingly used for the Digital SlopeADCs, and the DAC is called a fine quantization DAC correspondingly used for the NoiseHapingSARADCs.
In specific implementation, the digital predictive digital slopeadc with multiple bit bands is a digital predictive digital slopeadc with 6 bit bands and 2 orders; the multi-bit multi-order NS-SARADC is a 7-bit 2-order NS-SARADC.
The following is a detailed description of the components in the incremental scaling analog-to-digital converter system proposed by the present invention:
A. a multi-bit-band digitally predicted DigitalSlopeADC;
in specific implementation, the invention designs and adopts a Digital Slope ADC with second-order Digital prediction to carry out coarse quantization, wherein the Digital Slope ADC comprises a sampling circuit, a coarse quantization DAC, a comparator and a Digital logic part, the Digital logic part is added with the Digital predictor (such as a first-order, second-order or multi-order Digital predictor) of the invention on the basis of the Digital logic of the existing Digital Slope ADC, and the coarse quantization DAC part in the Digital Slope ADC with multi-order Digital prediction adopts thermometer coding to adapt to the needs of the multi-order Digital predictor.
After the sampling circuit finishes sampling the input signal, the digital predictive DigitalSlopeADC of the multi-bit band begins to carry out coarse quantization, and the process is as follows: firstly, performing second-order digital prediction on the input signal sampled at this time by using the results of the previous two times of coarse quantization, and considering the results of the first negative coarse quantization and the zeroth coarse quantization as zero, so that the second-order digital prediction of the first coarse quantization and the second coarse quantization can be performed, and after obtaining the prediction result, applying the prediction result to a coarse quantization DAC; subsequent coarse quantization continues on the basis of the prediction; and comparing the voltage on the DAC top plate with zero by using a comparator, changing one LSB according to a predicted result according to a comparison result, namely switching 1 unit capacitor in the coarse quantization DAC, repeating the process of firstly comparing and then switching once in each period, and after a plurality of periods, turning over the comparison result of the comparator (for example, the comparison result of the comparator in the previous periods is always positive, and the current comparison result is negative, namely the turning over occurs), stopping and obtaining the result of the coarse quantization at this time.
By analysis and simulation, in an ADC system with an oversampling rate of 8, after the 6-bit DigitalSlopeADC with second-order digital prediction is adopted and a prediction result is applied to a coarse quantization DAC, the coarse quantization of an analog-to-digital converter can be completed only by switching 6 unit capacitors at most, namely 6 periods. Compared with the existing zoomADC, the method has the advantages that SARADC is adopted for coarse quantization, all capacitors in the coarse quantization DAC are required to be switched once, and the switching direction is uncertain; in the specific implementation of the invention, the Digital Slope ADC is improved by combining second-order Digital prediction, and the Digital Slope ADC with the second-order Digital prediction only needs to switch a capacitor corresponding to an input signal, so that the switching number and the switching power consumption of the coarse-quantization DAC are greatly reduced.
B. Multibit and multistage NoiseHapingSARADC
In specific implementation, the invention designs and adopts second-order NoiseHapingSARADC to carry out fine quantization, wherein the fine quantization comprises a fine quantization DAC, a comparator, a loop filter and digital logic, the loop filter part adopts a novel loop filter implementation mode, and the fine quantization DAC part adopts binary coding.
After the coarse quantization is finished, the top plate of the coarse quantization DAC and the top plate of the fine quantization DAC are both coarse quantization residual voltages; firstly amplifying the residual voltage, adding the output voltage of the loop filter in the fine quantization process, adding an input comparator and comparing with zero, switching a capacitor in the fine quantization DAC according to a comparison result, repeating the process of amplifying, comparing and switching once in each period, and sequentially switching 7 capacitors in the fine quantization DAC from large to small after 7 periods to finish the fine quantization. Each time the fine quantization is completed, a loop filter update is triggered.
The loop filter is a multi-order FIR filter (Finite Impulse Response, finite single-bit Impulse Response filter), which can adopt a second-order FIR filter, and the realization method proposed by the invention is as follows: the last fine quantization and the input of the loop filter after the last fine quantization are finished are extracted and stored on two delay capacitors through a dynamic buffer: the delay capacitor 1 and the delay capacitor 2 respectively store the single-cycle delay of the last input signal of the loop filter and the double-cycle delay of the last input signal of the loop filter during the fine quantization. The output of the loop filter during the fine quantization is obtained by using the voltage values stored on the delay capacitor 1 and the delay capacitor 2: the two capacitors are connected in series by a capacitor, so that the addition between the single-period delay and the double-period delay of the two input signals on the loop filter can be realized, when the addition is carried out, the single-period delay of the last input signal of the loop filter needs to be multiplied by a coefficient 2, the coefficient is realized by splitting the delay capacitor storing the single-period delay of the last input signal of the loop filter into two parts, and then the two parts of capacitors are connected in series, and the final addition result is the output of the loop filter.
Two capacitors connected in series are connected to the output end of the configurable floating voltage domain amplifier in a capacitor stacking mode, and the addition of the output result of the loop filter and the output result of the configurable floating voltage domain amplifier is realized in the fine quantization process.
When the loop filter is updated after the fine quantization is finished, the buffer is used for extracting the input signal of the loop filter in the current period and storing the input signal on the third delay capacitor (delay capacitor 3), and the voltage values stored on the delay capacitor 3 and the delay capacitor 1 are used for obtaining new loop filter output in the next fine quantization. After the next fine quantization is finished, the buffer is used to extract the input signal of the loop filter in the current period and store the signal on the delay capacitor 2, and the voltage values stored on the delay capacitor 2 and the delay capacitor 3 are used to obtain the new output of the loop filter during the next fine quantization, and so on.
Compared with the existing loop filter implementation mode, the loop filter implementation mode provided by the invention can achieve the noise shaping effects of high robustness and high precision, and can easily expand the order of the filter to a higher order by only one buffer, thereby reducing the power consumption and hardware overhead of the loop filter.
C. Configurable floating voltage domain amplifier design
The configurable floating voltage domain amplifier structure comprises a power supply capacitor, a load capacitor, an amplifier tube and a binary capacitor array; the power supply capacitor comprises a first part power supply capacitor, a second part power supply capacitor and a third part power supply capacitor; the load capacitor comprises a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor;
the working process of the incremental scaling analog-to-digital converter comprises the following steps: a sampling stage, a coarse quantization stage, a fine quantization stage and a loop filter updating stage; the three stages of the sampling stage, the fine quantization stage and the stage of updating the loop filter require that the amplifier has the same gain, but have different requirements on the noise level of the amplifier, wherein the noise of the amplifier is minimum in the sampling stage, the stage of updating the loop filter is next, and the fine quantization stage can tolerate larger noise of the amplifier due to the noise shaping effect. The configurable floating voltage domain amplifier provided by the invention comprises the following components in operation:
in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added by a first part power supply capacitor, a second part power supply capacitor and a third part power supply capacitor; configuring a load capacitor as the sum of the first partial load capacitor, the second partial load capacitor and the noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;
in the fine quantization stage, the noise of the comparator is suppressed by amplifying the residual voltage, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum, and the noise is maximum;
in the updating stage of the loop filter, the noise of the loop filter is suppressed by amplifying the residual voltage, the charge conservation on a capacitor DAC is ensured, a power supply capacitor is configured to be added by a first part of power supply capacitors and a second part of power supply capacitors, and a load capacitor is configured to be added by a first part of load capacitors and a second part of load capacitors;
furthermore, another additional binary capacitor array is added and connected in parallel with the power supply capacitor to fine tune the size of the power supply capacitor of the three-stage amplifier, so as to calibrate the gain of the amplifier.
Compared with the prior art that the configurable amplifier is adopted and needs to be designed aiming at meeting the minimum noise requirement, the configurable floating voltage domain amplifier disclosed by the invention has the advantages that the parameters of the floating voltage domain amplifier are configured aiming at different noise requirements, the power consumption of the amplifier is lower, and the energy efficiency of an ADC (analog-to-digital converter) system is favorably improved.
The incremental zoom analog-to-digital converter configures the quantization process of the incremental zoomADC into a coarse quantization and then carries out multiple fine quantization; the implementation method comprises the following steps:
1) Preparing a multi-bit Digital Slope ADC which comprises a sampling circuit, a DAC, a comparator and a Digital logic part, improving the structure of the Digital Slope ADC based on the structure of the Digital Slope ADC, and adding a multi-order Digital prediction element in the Digital logic part of the Digital Slope ADC to prepare the multi-bit Digital Slope ADC with Digital prediction;
structurally, coarse quantization is carried out by using a Digital Slope ADC (analog to Digital converter) of multi-digit band multi-order Digital prediction;
2) The method for preparing the multi-bit and multi-order NoiseHapingSARADC comprises a DAC, a loop filter, a comparator and a digital logic part, wherein the loop filter part adopts the novel loop filter implementation mode provided by the invention.
Using a multi-bit multi-order NS-SAR ADC to carry out refinement quantization;
3) The digital slope analog-to-digital converter with multi-bit band digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter (DAC) part, and the part is formed by connecting two capacitor array top plates in different coding modes; the digital-to-analog converter used by the digital ramp type analog-to-digital converter corresponding to the multi-bit band digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used by the noise shaping successive approximation type analog-to-digital converter is a fine quantization digital-to-analog converter;
4) Designing and preparing a configurable floating voltage domain amplifier, namely improving the existing floating voltage domain amplifier; the power supply capacitor and the load capacitor of the floating voltage domain amplifier are divided into a plurality of parts, and control elements with various configurations are added to the digital logic part of the amplifier, so that the power supply capacitor configuration and the load capacitor configuration are configured, the configurable property of the amplifier is increased, and the amplifier is configured into different modes in different working stages according to different noise requirements of the amplifier.
And a floating voltage domain amplifier is used for amplification between coarse quantization and fine quantization and sampling noise elimination.
5) The Digital Slope ADC with multi-digit band and multi-digit Digital prediction is used as a first-stage ADC, the NoiseShapingSARADC with multi-digit and multi-digit is used as a second-stage ADC, the first-stage ADC and the second-stage ADC are connected through a top plate of a DAC component, a configurable floating voltage domain amplifier is embedded in the second-stage ADC and is arranged between the DAC and a loop filter, and the improved IncremeltalZoomaDC is obtained.
Compared with the prior art, the invention has the following beneficial effects:
compared with the traditional Zoom analog-to-digital converter, the analog-to-digital converter designed by the invention can give consideration to high energy efficiency and high precision, has medium input bandwidth and low data output delay, and can be adapted to various application scenes of the Internet of things.
Compared with the traditional ZoomaDC which needs to be re-sampled after the fine quantization is finished each time to recover the residual voltage, the incremental analog-to-digital converter provided by the invention can carry out multiple times of fine quantization without re-sampling after one time of coarse quantization, namely, one time of sampling and multiple times of conversion, thereby saving a large amount of sampling operation, improving the input bandwidth of the system and greatly relieving the requirement on an input driving circuit.
Compared with the existing implementation method, the Noise Shaping SAR implementation method provided by the invention not only can realize a stable Noise Shaping effect, but also can reduce the hardware overhead and power consumption of the NS-SAR ADC.
The Digital SlopeADC with the multi-order digital prediction technology can reduce the capacitance switching power consumption in the conventional Digital SlopeADC.
Compared with the existing floating voltage domain amplifier, the configurable floating voltage domain amplifier provided by the invention can be configured into a plurality of modes according to different amplifier noise requirements, and the power consumption of the floating voltage domain amplifier is reduced.
Drawings
FIG. 1 is a schematic diagram of an incremental scaling ADC according to the present invention;
wherein, the first and the second end of the pipe are connected with each other,
is an input signal;
sampling the input signal when the input signal is set to be high for sampling the signal;
for coarsely quantizing the signal, the coarse quantization is performed while setting high；
Setting the signal to be fine quantization signal, and performing fine quantization when setting the signal to be high;
the system is reset when set high for a reset signal.
Fig. 2 is a timing diagram illustrating the operation of the incrementally scaled adc of the present invention.
Fig. 3 is a circuit diagram of an incremental scaling adc according to the present invention.
Fig. 4 is a schematic diagram of an operation process of the incremental scaling analog-to-digital converter of the present invention.
Fig. 5 is a schematic diagram illustrating the operation principle of the loop filter in the delta-scaled analog-to-digital converter according to the present invention.
FIG. 6 is a circuit diagram of a configurable floating voltage domain amplifier in an ADC according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in the following description, without in any way limiting the scope of the invention.
The incremental ZoomADC (incremental scaling analog-to-digital converter) provided by the invention comprises a coarse quantization ADC and a fine quantization ADC, wherein the coarse quantization ADC is realized by improving based on a digital slope analog-to-digital converter (Digital slope ADC), and is designed into the digital slope ADC with multi-bit band second-order digital prediction. The fine quantization ADC is realized by NoiseHapingSARADC, and the coarse quantization ADC and the fine quantization ADC share a capacitor (DAC). The incremental scaling analog-to-digital converter structure provided by the invention has the technical advantages of high energy efficiency and multi-bit quantization of NoiseHapingSARADC, and also utilizes the coarse quantization and reference level range adjustment technology in ZoomaDC, so that the high-precision requirement of analog-to-digital conversion can be met without a high-order loop filter.
As shown in FIGS. 1 and 2, the incremental ZoomaDC of the present invention is implemented by a 6-bit Digital SlopeADC for coarse quantization at the first stage, a 7-bit NoiseHapingSARADC for fine quantization at the second stage, and a floating voltage domain amplifier for inter-stageSignal amplification and sampling noise cancellation. The digitalslopeodc and the noisseshapingsar adc share a DAC component. In the one-time complete analog-to-digital conversion process of the incremental ZoomaDC, firstly, the Digital SlopeADC performs conversion on an input signal
Sampling is carried out, noise of the sampling is eliminated by using a floating voltage domain amplifier, then the DigitalSlopeADC carries out first coarse quantization on the sampled input signal, after the coarse quantization is finished, the floating voltage domain amplifier carries out interstage amplification and carries out 4 times of fine quantization by using NoiseHapingSARADC, and multiple times of fine quantization conversion after one-time sampling is realized. Repeating the process eight times, carrying out 8 times of sampling, 8 times of coarse quantization and 32 times of fine quantization to obtain 32 quantization results, and processing the 32 quantization results by using a sampling filter to obtain a result of one-time analog-to-digital conversion.
The ADC system circuit and working process of the present invention are shown in fig. 3 and fig. 4, and the whole ADC system includes the following 4 working stages:
1) A sampling stage:
in that
When the voltage is high level, the sampling switch is closed to connect the bottom plate of the DAC to the input signal
Upper, top polar plate connected to common mode level
Upper, amplifier and capacitor
And resetting. In that
Time of day
Is set to low level, the DAC top polar plate switch is switched off, the input signal is transmitted
And first sampling noise
Is fixed on the DAC and triggers the amplifier to start amplifying. In that
Time of day
Set to low level, sampling switch and capacitor
Is turned off, will
To
Time varying input signal
And first sampling noise
Amplifying and sampling to a capacitor
In the above, sampling of the input signal and removal of sampling noise are completed.
2) A coarse quantization stage:
after the sampling is finished, the coarse quantization result is firstly obtained according to the last two sampling periods
And
performing second-order prediction on the input signal value of the sampling period, wherein the prediction result is
And switching the bottom plate voltage of the unit capacitor corresponding to the predicted result number in the DAC. Then triggering a comparator to compare the voltage of the DAC top electrode plate and comparing the voltage of the DAC top electrode plate according to a comparison junctionThe bottom plate voltage of a unit capacitor in the DAC is switched every conversion period. After comparison of a plurality of conversion periods and detection of inversion of the comparison result, comparison is performed again and the compensation capacitors with the size of 0.5 unit capacitor in the DAC are switched to complete coarse quantization to obtain the coarse quantization result of the sampling period
。
3) Fine quantization stage
In each conversion period of the fine quantization stage, firstly, the amplifier is triggered to amplify the residual voltage on the DAC top plate, and the amplified signal is superposed with the noise elimination capacitor
And the voltage of the bottom plate of the corresponding bit in the DAC is switched according to the comparison result to complete a conversion period, and the process is repeated for 7 times to complete one fine quantization.
4) Loop filter update stage
The loop filter is implemented as a second order FIR filter, as shown in FIG. 5
In sub-fine quantization, the capacitance in the filter
And
on which the feedback signal after the last fine quantization is finished is stored
Capacitor
And
the feedback signal after the last fine quantization is finished is saved
A capacitor
And
connected in parallel with the capacitor
And
is reversely connected in series to obtain
The second order FIR filter output of (1). Finish the first
After the secondary fine quantization, the FIR filter needs to be updated once, firstly, the trigger amplifier amplifies the residual voltage on the DAC top plate after the fine quantization is finished, and the amplified signal is superposed with a capacitor
And obtaining the feedback signal after the fine quantization is finished after the feedback signal passes through an FIR filter
It is stored in the capacitor through the buffer
And
performing a capacitor cyclic shift operation using the capacitors
And
replacement capacitor
And
in the position of (2), using a capacitor
And
replacement capacitor
And
position of (2), using a capacitor
And
replacement capacitor
And
to finish the first
And updating the secondary loop filter. At the next fine quantization, i.e. the first
When performing sub-fine quantization, the
The output value of the FIR filter feedback after secondary updating is updated to
To accomplish the following
The feedback signal after the sub-fine quantization is stored in the capacitor through the buffer
And
and again cyclically moving the capacitor position. After the fine quantization is finished each time, the operations of saving the feedback signal and capacitance shifting are repeated, and then the update of the second-order FIR filter can be realized.
And after the loop filter is updated, resetting the voltage of the DAC bottom electrode plate corresponding to the fine quantization ADC.
In 4 working phases of the ADC system of the present invention, the amplifier is used in the sampling phase, the fine quantization phase and the loop filter update phase, and the amplifier of the present invention is implemented using a configurable floating voltage domain amplifier structure as shown in fig. 6, in which the supply capacitor is used
Comprises a first part of power supply capacitor
A second part power supply capacitor
And a third part supply capacitor
Three parts, load capacitance
Then includes a first partial load capacitance
And a second partial load capacitor
Two parts. During the sampling phase, the amplifier is most sensitive to noise, so the supply capacitance is configured to
The load capacitance is configured as
The amplifier has the largest power consumption and the smallest noise; in the fine quantization stage, the noise of the amplifier is shaped and can tolerate larger noiseThe supply capacitor is thus configured as
The load capacitance is configured as
The amplifier has the minimum power consumption and the maximum noise; in the loop filter update phase, the amplifier has moderate noise and power consumption, and the supply capacitor is configured to
The load capacitance is configured as
. And the other additional binary capacitor array is added and connected with the power supply capacitor in parallel to be used for finely adjusting the size of the power supply capacitor of the amplifier in the three stages, the gain of the amplifier is calibrated, and the gain of the amplifier can meet the design requirement after one-time factory calibration.
It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the invention and scope of the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (10)
1. A multistep analog-to-digital converter is characterized in that the structure of an incremental scaling analog-to-digital converter is improved, and a Noise Shaping successive approximation type analog-to-digital converter (Noise Shaping SAR ADC) is adopted for fine quantization of the analog-to-digital converter; the method comprises the following steps: a multi-bit band digital prediction digital ramp analog-to-digital converter (DigitalSlopeADC), a multi-bit multi-order noise shaping successive approximation analog-to-digital converter and a configurable floating voltage domain amplifier; realizing sampling for one time and converting for multiple times, namely performing coarse quantization for one time after sampling for one time and performing fine quantization for multiple times;
a digital ramp type analog-to-digital converter with multi-bit band digital prediction is used as the first stage of the multi-step analog-to-digital converter and is used for carrying out first-step coarse quantization; a multi-bit and multi-order noise shaping successive approximation type analog-to-digital converter is used as the second stage of the multi-step analog-to-digital converter and used for carrying out second-step fine quantization; a configurable floating voltage domain amplifier is embedded in the second stage and is used for eliminating sampling noise and amplifying signals between coarse quantization and fine quantization;
the digital ramp type analog-to-digital converter with multi-bit band digital prediction and the multi-bit multi-order noise shaping successive approximation type analog-to-digital converter share the same digital-to-analog converter (DAC) component, and the component is formed by connecting two capacitor array top plates in different coding modes; the digital-to-analog converter used by the digital ramp type analog-to-digital converter corresponding to the multi-bit band digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used by the noise shaping successive approximation type analog-to-digital converter is a fine quantization digital-to-analog converter;
A. a digital ramp-type analog-to-digital converter with multi-bit-band digital prediction comprising: the device comprises a sampling circuit part, a coarse quantization digital-to-analog converter part, a comparator part and a digital logic part; wherein, the digital logic part is added into a multi-order digital predictor; the coarse quantization digital-to-analog converter part adopts thermometer coding;
B. the multi-bit and multi-order noise shaping successive approximation type analog-to-digital converter comprises a fine quantization digital-to-analog converter part, a comparator part, a loop filter part and a digital logic part; wherein, the loop filter part adopts a novel loop filter; the fine quantization digital-to-analog converter part adopts binary coding; the novel loop filter is a multi-order finite-length single-bit impulse response filter, and the order of the filter can be expanded to a higher order only by one buffer;
C. the configurable floating voltage domain amplifier structure comprises a power supply capacitor, a load capacitor, an amplifier tube and a binary capacitor array; the power supply capacitor comprises a first part power supply capacitor, a second part power supply capacitor and a third part power supply capacitor; the load capacitor comprises a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor;
the configurable floating voltage domain amplifier can realize the same gain and can configure different noises at different stages of the working process of the incremental scaling analog-to-digital converter; the configurable floating voltage domain amplifier, in operation, comprises:
in a sampling phase, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added by a first part power supply capacitor, a second part power supply capacitor and a third part power supply capacitor; configuring a load capacitor as the sum of a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor, so that the power consumption of the amplifier is maximum, and the noise is minimum;
in the fine quantization stage, the noise of the comparator is suppressed by amplifying the residual voltage, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum, and the noise is maximum;
in the updating stage of the loop filter, the residual voltage is amplified to suppress the noise of the loop filter and ensure the conservation of the charge on the capacitor DAC, the supply capacitor is configured to be added by the first part of the supply capacitor and the second part of the supply capacitor, and the load capacitor is configured to be added by the first part of the load capacitor and the second part of the load capacitor.
2. The multi-step analog-to-digital converter of claim 1, wherein the multi-bit band digital predictive digital ramp-type analog-to-digital converter is a 6-bit band 2-order digital predictive; the multi-bit and multi-order noise shaping successive approximation type analog-to-digital converter is 7 bits and 2 orders.
3. A method for realizing a multi-step analog-to-digital converter is characterized in that a multi-step analog-to-digital converter, namely an incremental scaling analog-to-digital converter is designed, a quantization process of the analog-to-digital converter is configured into one-time sampling, then one-time coarse quantization is carried out, then multiple times of fine quantization are carried out, namely one-time sampling and multiple times of conversion are carried out, and repeated sampling is not needed between the fine quantization; the implementation method comprises the following steps:
1) Preparing a digital slope type analog-to-digital converter with multi-bit band digital prediction;
the structure based on the digital ramp type analog-to-digital converter is improved, a multi-order digital prediction element is added to a digital logic part in the digital ramp type analog-to-digital converter, and the digital ramp type analog-to-digital converter with multi-bit band digital prediction is prepared and obtained, and comprises a sampling circuit, a digital-to-analog converter, a comparator and digital logic and is used for carrying out coarse quantization;
2) Preparing a multi-bit and multi-order noise shaping successive approximation type analog-to-digital converter for fine quantization, wherein the analog-to-digital converter comprises a digital-to-analog converter, a loop filter, a comparator and a digital logic part; wherein, the loop filter part adopts a novel loop filter;
3) The digital slope analog-to-digital converter with multi-bit band digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter (DAC) part, and the part is formed by connecting two capacitor array top plates in different coding modes; the digital-to-analog converter used by the digital slope analog-to-digital converter corresponding to the multi-bit band digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used by the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;
4) Designing and preparing a configurable floating voltage domain amplifier; used for carrying out amplification and sampling noise elimination between coarse quantization and fine quantization;
the existing floating voltage domain amplifier is improved; the power supply capacitor and the load capacitor of the floating voltage domain amplifier are split into multiple parts, and control elements with multiple configurations are added to a digital logic part of the amplifier to configure the configuration of the power supply capacitor and the configuration of the load capacitor, so that the configurable property of the amplifier is increased, and the amplifier is configured into different modes at different working stages according to different noise requirements of the amplifier;
5) Connecting a digital slope type analog-to-digital converter with multi-bit band multi-order digital prediction and a multi-bit multi-order noise shaping successive approximation type analog-to-digital converter through a top pole plate of a digital-to-analog converter part; the configurable floating voltage domain amplifier is embedded in the multi-bit and multi-order noise shaping successive approximation type analog-to-digital converter and is arranged between the digital-to-analog converter and the loop filter, and the improved incremental scaling type analog-to-digital converter is obtained.
4. A method for implementing a multi-step analog-to-digital converter as claimed in claim 3, wherein after the sampling circuit has sampled the input signal, the digital ramp-type analog-to-digital converter with multi-bit band digital prediction performs the coarse quantization process by:
firstly, performing second-order digital prediction on the input signal sampled at this time by using the results of the previous two coarse quantization;
the results of the first negative and zeroth coarse quantizations are zero;
after a prediction result is obtained, the prediction result is firstly applied to a coarse quantization DAC;
then, coarse quantization is carried out: comparing the voltage on the DAC top polar plate with zero by using a comparator, and changing one LSB (least significant bit) of a prediction result according to the comparison result, namely switching 1 unit capacitor in the coarse quantization DAC;
repeating the process of comparing first and then switching once in each period;
after several cycles, the comparison result of the comparator is inverted, the operation is stopped and the result of the coarse quantization is obtained.
5. The method of claim 4, wherein the coarse and fine DACs have coarse quantization residual voltages on their top plates.
6. A method of implementing a multi-step analog-to-digital converter as claimed in claim 5, characterized by first amplifying and adding the residual voltage to the output voltage of the loop filter during the current fine quantization, adding the input comparator for comparison with zero;
switching a capacitor in the fine quantization DAC according to the comparison result;
repeating the processes of amplifying, comparing and switching once in each period;
after a plurality of cycles, the capacitors in the fine quantization DAC are switched from large to small in sequence to finish the current fine quantization;
triggering the updating of the loop filter after each fine quantization is finished.
7. A method for implementing a multi-step analog-to-digital converter as claimed in claim 3, wherein the configurable floating-voltage-domain amplifier, in operation, comprises:
in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added by a first part power supply capacitor, a second part power supply capacitor and a third part power supply capacitor; configuring a load capacitor as the sum of a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;
in the fine quantization stage, the noise of the comparator is suppressed by amplifying the residual voltage, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum, and the noise is maximum;
in the updating phase of the loop filter, the noise of the loop filter is suppressed by amplifying the residual voltage, the charge conservation on the capacitor DAC is ensured, the power supply capacitor is configured to be added by the first part of power supply capacitor and the second part of power supply capacitor, and the load capacitor is configured to be added by the first part of load capacitor and the second part of load capacitor.
8. A method for implementing a multi-step analog-to-digital converter as claimed in claim 3, wherein said novel loop filter is specifically:
extracting and storing the input of the loop filter after the last fine quantization and the last fine quantization are finished on two delay capacitors, wherein the two delay capacitors respectively store the single-cycle delay of the last input signal of the loop filter and the double-cycle delay of the last input signal;
and obtaining the output of the loop filter when the current fine quantization is carried out by using the voltage values stored on the two delay capacitors: connecting two capacitors in series by a capacitor, adding the two-time input signal single-period delay and the two-period delay on the loop filter, multiplying the single-period delay of the last input signal of the loop filter by a set coefficient, splitting a delay capacitor storing the last input signal single-period delay of the loop filter, and connecting the capacitors in series; the addition result is the output of the loop filter.
9. A method of implementing a multi-step analog-to-digital converter as claimed in claim 8, wherein two capacitors connected in series are connected in a capacitor stack to the output of the configurable floating voltage domain amplifier, and the addition of the loop filter output result and the amplifier output result is performed during the present fine quantization process.
10. The method as claimed in claim 9, wherein when the loop filter is updated after the fine quantization is completed, the buffer is used to extract and store the input signal of the loop filter in the current period to the third delay capacitor, and when the fine quantization is performed next time, the voltage values stored in the third delay capacitor and the first delay capacitor are used to obtain a new loop filter output; and after the next fine quantization is finished, extracting the input signal of the loop filter in the current period by using a buffer, storing the input signal into a second delay capacitor, and obtaining new loop filter output by using the voltage values stored in the second delay capacitor and a third delay capacitor during the next fine quantization.
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| US20160142072A1 (en) * | 2014-11-13 | 2016-05-19 | Zentrum Mikroelektronik Dresden Ag | Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters |
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| CN114124099A (en) * | 2021-11-24 | 2022-03-01 | 苏州聚元微电子股份有限公司 | Input scaling module of incremental analog-to-digital converter |
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| US20160142072A1 (en) * | 2014-11-13 | 2016-05-19 | Zentrum Mikroelektronik Dresden Ag | Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters |
| CN109412597A (en) * | 2018-10-29 | 2019-03-01 | 清华大学深圳研究生院 | A kind of gradual approaching A/D converter and D conversion method of second-order noise shaping |
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