CN116341447A - Method for designing non-binary capacitor array with stable time - Google Patents
Method for designing non-binary capacitor array with stable time Download PDFInfo
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Abstract
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a method for establishing a time-stable non-binary capacitor array design, which is suitable for capacitor design of a non-binary capacitor DAC. The invention sets the ratio of each bit of capacitance weight and corresponding redundancy in the capacitance arraykThe capacitance value of each capacitor in the capacitor array is determined one by one from low to high, and is solved by linear programming optimizationkAnd the value of N, thereby realizing the double-choice optimal design of the establishment precision and the establishment time, not only improving the establishment speed of the non-binary capacitor array, but also avoiding the blindness of the non-binary code design.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a method for establishing a time-stable non-binary capacitor array design, which is suitable for capacitor design of a non-binary capacitor DAC.
Background
The capacitive array is an important part of the capacitive analog-to-digital converter. For a conventional SAR ADC, since the input signal corresponds to the digital code one by one, each bit of quantization must be accurate, otherwise the final result will be erroneous. In order to ensure that each quantization can obtain a correct result, the setup error of each capacitor in the capacitor array must be less than 0.5LSB, so that the setup time required for quantizing the most significant bit and the least significant bit is greatly different, and the time utilization rate of the system is low.
Aiming at the problem of low utilization rate of system time, a non-binary coding capacitor array design method is proposed in literature, the method has high design freedom, and redundancy of each capacitor can be designed independently. When the ith capacitor has redundancy r i When it is established, its time can be expressed as:
wherein t is i To establish time, τ is a time constant, W i-1 Is the i-1 bit capacitance weight value. From the above equation, the larger the redundancy amount is, the larger the DAC-tolerant setup error is, so that the setup time of the DAC is reduced; however, the greater the amount of redundancy, the smaller the overall dynamic range of the ADC, and therefore, the greater the number of capacitance bits required to achieve the same dynamic range as the original binary ADC, which in turn increases the quantization time of the system. Therefore, how to build a time-directed DAC per-bit capacitor design for a capacitor array is an urgent issue to be addressed in non-binary capacitor array applications.
Disclosure of Invention
Aiming at the problems or the shortcomings, the invention provides a non-binary capacitor array design method with stable establishment time, and the capacity value of each capacitor in a capacitor array is determined one by one from low to high by setting the weight of each capacitor in the capacitor array and the proportion of corresponding redundancy, so that the double-choice optimization design of the establishment precision and the establishment time is realized.
A method for establishing a time-stable non-binary capacitor array design comprises the following specific steps:
wherein r is i For the redundancy of the ith capacitor, W i-1 Is the i-1 bit capacitance weight value. k determines the settling time t for designing the ith capacitor i The value of k is determined.
Step 2, the low three-bit capacitor C of the capacitor array 1 -C 3 Respectively designed as C in turn U 、2C U 、3C U ，C U Is the unit capacitance; from the fourth bit capacitance C 4 Beginning to capacitor array top C N And calculating the capacitance value of each capacitor one by one according to the set capacitance weight and the proportional k value of the corresponding redundancy.
Specifically, for the fourth bit capacitance C 4 The capacitance value is calculated by the following formula:
namely:
fifth bit capacitor C 5 The capacitance values are as follows:
namely:
and so on, the final Nth capacitor C N The capacitance of (2) is:
step 3, rounding and rounding the capacitances of each bit of the non-binary capacitor array calculated in the step 2 to obtain C i Becomes C i ′ The method comprises the following steps:
obtaining the capacitance value C of each bit of the N-bit non-binary capacitor array N ′ 。
Further, the values of k and N in the step 1 are determined by the following linear programming relation:
linear programming function: c (C) 1 + C 2 + C 3 +…+ C N =6(2k+1) N /(k+1) N ≥2 ENOB -1
Objective function:
wherein ENOB is the effective bit number of the capacitor array, N is the number of capacitors of the capacitor array, and τ is the time constant. And minimizing an objective function through calculation, minimizing the overall establishment time of the capacitor array, and finally optimizing and determining the values of k and N.
According to the invention, the capacitance value of each capacitor in the capacitor array is determined one by one from low to high by setting the weight of each capacitor in the capacitor array and the proportion k of the corresponding redundancy, and the values of k and N are solved through linear programming optimization, so that the double-selection optimization design of the establishment precision and the establishment time is realized, the establishment speed of the non-binary capacitor array is improved, and the blindness of the non-binary coding design is avoided.
Drawings
FIG. 1 is a circuit diagram of the present invention for creating a time stable non-binary capacitive array;
FIG. 2 is a schematic diagram of a non-binary capacitor array with 8-bit significant bit set-up time stabilization according to an embodiment;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
As shown in fig. 2, a circuit diagram of a non-binary capacitor DAC capacitor array with stable setup time for the 8-bit significant bit number in this embodiment is shown.
linear programming function: c (C) 1 + C 2 + C 3 +…+ C N =6(2k+1) N /(k+1) N ≥2 8 -1
Objective function:
as calculated, the objective function is minimal when n=16, k=0.502.
Step 2, as shown in figure 1, the low three-bit capacitors of the capacitor array are respectively C 1 -C 3 Designed as C U 、2C U 、3C U And calculates the fourth bit capacitance C 4 Is the capacitance value of (2): c (C) 4 =2.005C U 。
Similarly, the fifth capacitor C 5 The capacitance of (c) can be calculated as: c (C) 5 =2.675C U 。
Similarly, the sixth to 16 th capacitors C 6 ~C 16 The capacitance of (c) can be calculated as:
C 6 =3.568C U ，C 7 =4.76C U ，C 8 =6.35C U ，C 9 =8.47C U ，C 10 =11.3C U ，C 11 =15.08C U ，C 12 =20.11C U ，C 13 =26.83C U ，C 14 =35.79C U ，C 15 =47.74C U ，C 16 =63.69C U 。
step 3, rounding and rounding the capacitors of each bit, wherein the rounded capacitor array is as follows:
C 1 =1C U ，C 2 =2C U ，C 3 =3C U ，C 4 ′ =2C U ，C 5 ′ =3C U ，C 6 ′ =4C U ，C 7 ′ =5C U ，C 8 ′ =6C U ，C 9 ′ =8C U ，C 10 ′ =11C U ，C 11 ′ =15C U ，C 12 ′ =20C U ，C 13 ′ =27C U ，C 14 ′ =36C U ，C 15 ′ =48C U ，C 16 ′ =64C U 。
according to the embodiment, the capacitance value of each capacitor in the capacitor array is determined one by one from the low level to the high level by setting the weight of each capacitor in the capacitor array and the proportion of the corresponding redundancy, so that the double-selection optimal design of the establishment precision and the establishment time is realized, the establishment speed of the non-binary capacitor array is improved, and the blindness of the non-binary coding design is avoided. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (3)
1. The method for establishing the time-stable non-binary capacitor array design is characterized by comprising the following specific steps of:
step 1, for the capacitors in the non-binary capacitor array of the effective bit number ENOB bit, N is the number of capacitors in the capacitor array, where the ratio k of the capacitance weight of each bit to the corresponding redundancy number is:
；
wherein r is i For the redundancy of the ith capacitor, W i-1 The value is the i-1 bit capacitance weight value; k determines the settling time t for designing the ith capacitor i Taking a value of k;
step 2, the low three-bit capacitor C of the capacitor array 1 -C 3 Respectively designed as C in turn U 、2C U 、3C U ，C U Is the unit capacitance; from the fourth bit capacitance C 4 Beginning to capacitor array top C N Calculating the capacitance value of each capacitor one by one according to the set capacitance weight and the proportional k value of the corresponding redundancy;
step 3, for each bit capacitance C of the non-binary capacitor array calculated in the step 2 i Rounding to give i= 4~N, so that C i Becomes C i ′ Obtaining the capacitance value C of each bit of the N-bit non-binary capacitor array N ′ ：
2. The method for designing a time-stable non-binary capacitor array according to claim 1, wherein the values of k and N in the step 1 are determined by the following linear programming relation:
linear programming function: c (C) 1 + C 2 + C 3 +…+ C N =6(2k+1) N /(k+1) N ≥2 ENOB -1
Objective function:
；
wherein ENOB is the effective digits of the capacitor array, N is the number of capacitors of the capacitor array, and τ is the time constant; and minimizing an objective function through calculation, minimizing the overall establishment time of the capacitor array, and finally optimizing and determining the values of k and N.
3. The method of creating a time stable non-binary capacitive array design of claim 1, wherein:
the step 2 is to calculate the capacitance value of each capacitor one by one according to the set proportion k value specifically as follows:
for the fourth bit capacitance C 4 The capacitance value is calculated by the following formula:
namely:
；
fifth bit capacitor C 5 The capacitance values are as follows:
；
namely:
；
and so on, the final Nth capacitor C N The capacitance of (2) is:
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Citations (6)
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| CN104660264A (en) * | 2015-03-20 | 2015-05-27 | 中国电子科技集团公司第二十四研究所 | Analog-digital converter and chip of non-binary capacitor array with redundancy bit |
| CN110086468A (en) * | 2019-05-17 | 2019-08-02 | 成都微光集电科技有限公司 | A kind of weight calibration method of nonbinary gradual approaching A/D converter |
| CN110350918A (en) * | 2019-07-17 | 2019-10-18 | 电子科技大学 | A kind of digital Background calibration method based on least mean square algorithm |
| CN111130550A (en) * | 2020-01-03 | 2020-05-08 | 清华大学 | Successive approximation register type analog-to-digital converter and signal conversion method thereof |
| CN114301463A (en) * | 2021-12-31 | 2022-04-08 | 山东大学 | Non-binary capacitor array successive approximation type analog-digital converter circuit based on Pasteur number array and working method |
| CN115099182A (en) * | 2022-07-25 | 2022-09-23 | 湖南毂梁微电子有限公司 | Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter |
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| CN104660264A (en) * | 2015-03-20 | 2015-05-27 | 中国电子科技集团公司第二十四研究所 | Analog-digital converter and chip of non-binary capacitor array with redundancy bit |
| CN110086468A (en) * | 2019-05-17 | 2019-08-02 | 成都微光集电科技有限公司 | A kind of weight calibration method of nonbinary gradual approaching A/D converter |
| CN110350918A (en) * | 2019-07-17 | 2019-10-18 | 电子科技大学 | A kind of digital Background calibration method based on least mean square algorithm |
| CN111130550A (en) * | 2020-01-03 | 2020-05-08 | 清华大学 | Successive approximation register type analog-to-digital converter and signal conversion method thereof |
| CN114301463A (en) * | 2021-12-31 | 2022-04-08 | 山东大学 | Non-binary capacitor array successive approximation type analog-digital converter circuit based on Pasteur number array and working method |
| CN115099182A (en) * | 2022-07-25 | 2022-09-23 | 湖南毂梁微电子有限公司 | Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter |
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| YONGFU LI 等: "Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods", 《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》, vol. 33, no. 9, pages 1277 - 1287, XP011556780, DOI: 10.1109/TCAD.2014.2323217 * |
| 陈晓青 等: "非二进制SAR_ADC的电容失配校正方法", 《计算机工程与设计》, vol. 39, no. 6, pages 1603 - 1609 * |
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