CN116339438A - Input bias current eliminating circuit - Google Patents
Input bias current eliminating circuit Download PDFInfo
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- CN116339438A CN116339438A CN202111603224.8A CN202111603224A CN116339438A CN 116339438 A CN116339438 A CN 116339438A CN 202111603224 A CN202111603224 A CN 202111603224A CN 116339438 A CN116339438 A CN 116339438A
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- 230000008030 elimination Effects 0.000 claims description 4
- 238000003379 elimination reaction Methods 0.000 claims description 4
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The application discloses an input bias current cancellation circuit, including: a main input module including an operational amplifier based on main input pipes Q1, Q2; the input common mode following module realizes the input common mode following of the main input module based on Q3 and Q4 which are respectively connected with positive and negative inputs of the operational amplifier and a common mode acquisition Q5, so that the working state of the Q5 is consistent with that of the main input pipes Q1 and Q2; the adjusting module adjusts the collector current of Q5; the feedback module collects the base current Ib1 of the Q5 to the current mirror module; and the current mirror module outputs the Ib1 mirror image to the positive and negative inputs of the operational amplifier according to the proportion k, and eliminates the bias current input by the main input module. The invention can eliminate the new input bias current generated by the change of the input common mode.
Description
Technical Field
The invention belongs to the technical field of base current elimination of transistors, and relates to an input bias current elimination circuit.
Background
The bipolar transistor is a current amplifying device, and the ratio of collector current to base current is the current amplification factor β of the bipolar transistor. Since the current amplification factor β of an actual transistor is limited, typically about 100 times, the input current is inevitably present in a bipolar transistor. In general, it is desirable to minimize the supply of input current from the external node to the base of the bipolar transistor. An associated base current cancellation circuit is thus created.
The base current cancellation circuit of the bipolar transistor operates on the principle that an appropriate current source is connected to the base of the bipolar transistor to cancel or reduce the current flowing from the external node to the base of the bipolar transistor.
Fig. 1 shows a prior art scheme IN which two fixed current sources I1, I2 are connected to the positive and negative inputs IN-, in+ of an operational amplifier, respectively. The current source I1 is generated by a fixed bias, and does not change with the state change of the transistor Q1. For example, when the input common mode voltage of the two input transistors Q1 and Q2 changes, the current amplification factor β of the two transistors slightly changes, which means that the base currents flowing into Q1 and Q2 change without changing I1, and the base current Ib1 of the transistor Q1 remains unchanged, so that a new non-eliminated base current is generated.
In addition, in practical applications, the output impedance of I1 is not infinite, that means that I1 will change with the change of the input common mode voltage of Q1 and Q2, causing the emitter currents of Q1 and Q2 to change, even if the current amplification coefficient β of the transistors does not change at this time, the base currents Ib of the two transistors will also change, and a new current that is not eliminated will still be generated if Ib1 remains unchanged.
Disclosure of Invention
In order to solve the defects in the prior art, the application provides an input bias current eliminating circuit.
In order to achieve the above object, the present invention adopts the following technical scheme:
an input bias current eliminating circuit comprises a main input module, an input common mode following module, a feedback module, a current mirror module and an adjusting module;
the main input module comprises an operational amplifier based on main input tube bipolar transistors Q1 and Q2;
the input common mode following module is used for realizing input common mode following of the main input module based on bipolar transistors Q3 and Q4 which are respectively connected with positive and negative inputs of the operational amplifier and a common mode acquisition bipolar transistor Q5, so that the working state of the Q5 is consistent with that of the main input pipes Q1 and Q2;
the adjusting module is used for adjusting the collector current of Q5;
the feedback module is used for collecting the base current Ib1 of the Q5 to the current mirror module;
and the current mirror module is used for outputting the Ib1 mirror image to the positive and negative inputs of the operational amplifier according to the proportion k to eliminate the bias current input by the main input module.
The invention further comprises the following preferable schemes:
preferably, the main input module comprises main input tube bipolar transistors Q1, Q2 and corresponding cascode devices Mn1, mn2, and a current source I1;
the drains of Mn1 and Mn2 are connected with a load circuit, the grid is connected with a power supply vb, and the sources are respectively connected with the collectors of Q1 and Q2;
the bases of Q2 and Q1 are respectively the positive and negative inputs of an operational amplifier, the emitter is connected with a current source I1, and the current source I1 is grounded.
Preferably, the input common-mode following module comprises bipolar transistors Q3 and Q4, a common-mode acquisition bipolar transistor Q5, and corresponding cascode devices Mn3, mn4, mn5 and a current source I2;
the emitters of the Q3, Q4 and Q5 are connected with a current source I2, and the current source I2 is grounded;
the bases of the Q3 and the Q4 are respectively connected with the positive and negative inputs of the operational amplifier, and the collectors are respectively connected with the sources of the Mn3 and the Mn 4;
the grid electrodes of Mn3 and Mn4 are connected with a power supply vb, and the drain electrodes are connected with a power supply voltage VDD;
the collector electrode of the Q5 is connected with the source electrode of the Mn5, and the base electrode is connected with the feedback module;
and the grid electrode of Mn5 is connected with a power supply vb, and the drain electrode is connected with a feedback module and an adjusting module.
Preferably, the regulating module comprises bipolar transistors Q6 and Q7, NMOS transistor Mn7, PMOS transistors Mp1 and Mp0, and a current source I3;
the drain electrode of the Mp1 is connected with the drain electrode of Mn5, the source electrode is connected with the power supply voltage VDD, and the grid electrode is connected with the grid electrode and the drain electrode of the Mp 0;
the source electrode of the Mp0 is connected with the power supply voltage VDD, and the drain electrode of the Mp0 is connected with the drain electrode of the Mn 7;
the grid electrode of Mn7 is connected with a power supply vb, and the source electrode is connected with the collector electrodes of Q6 and Q7;
the emission sets of Q6 and Q7 are connected with a current source I3, and the current source I3 is grounded;
the bases of the Q6 and the Q7 are respectively connected with the positive input and the negative input of the operational amplifier.
The regulation module provides bias for Mp1 to make collector current of Q5 equal to 0.5I 3-Ib (Q6).
Preferably, the feedback module includes an NMOS transistor Mn6, whose source is connected to the base of Q5, gate is connected to the drain of Mn5, and drain is connected to the current mirror module.
Preferably, the current mirror module PMOS transistors Mp2, mp3, mp4;
the sources of Mp2, mp3 and Mp4 are connected with the power supply voltage VDD, the grid is connected with the drain electrode of Mn6, and the drain electrodes are respectively connected with the drain electrode of Mn6 and the positive and negative inputs of the operational amplifier.
Preferably, by configuring the mirror ratio k such that the input bias currents ib0=q5 of Q1, Q2 are base current Ib1, complete cancellation of the input bias currents is achieved.
Preferably, the current amplification coefficients of Q1, Q2, and Q5 are the same, and are all β.
Preferably, the input bias currents ib0=i1/(2×β+1)) of Q1 and Q2, the regulating module makes the collector current of Q5 equal to 0.5×i3—ibjb (Q6), the base current ib1=i3/2×β+1 of Q5, and if i2=1.5×i3 is set, ib3=ib4=ib5 (Q5) =ib6) =ib7, and if Mp2 and Mp3 and Mp2 and Mp4 are arranged in mirror proportion k=2+ (I1/(I3)), ib0+ib3) +ib5 (Q5)
=kχib1, achieving complete cancellation of the input bias current.
The beneficial effect that this application reached:
in the present invention, the input bias current ib0=i1/(2×β+1) of the main input tubes Q1, Q2, and the expression of Ib0 includes both β and I1, which means that Ib1 can change with I1 and β, and new input bias current generated by the change of the input common mode can be eliminated. Furthermore, according to the present invention, when the base current ib1=i3/(2×β+1)) of Q5 in the common mode follower module is input, the mirror image ratios k=2+ (I1/(I3)) of Mp2 and Mp3 and Mp2 and Mp4 are configured, so that ib0+ib (Q3) +ib (Q5) =k×ib1, and complete elimination of the input bias current is achieved.
Drawings
Fig. 1 is a base current cancellation circuit of a bipolar transistor according to a prior art scheme;
fig. 2 is a circuit diagram of an input bias current cancellation circuit of the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.
As shown in fig. 2, the present invention is an improvement of the scheme of fig. 1, mainly adding the base current eliminating circuit on the right side of fig. 2, and a pair of transistors Q3, Q4 connected to the positive and negative inputs respectively, and a common mode collecting transistor Q5 are added compared with the old scheme. In fig. 2, I1, I2 two current sources are generated by one bias. I.e. the ratio of the two currents according to the ratio of the current changes of I1 and I2 caused by the change of the input common mode voltage of the circuit as shown in fig. 2. I.e. Δi1/Δi2=i1/I2.
Specifically, the invention relates to an input bias current eliminating circuit which comprises a main input module, an input common mode following module, a feedback module, a current mirror module and an adjusting module;
the main input module comprises an operational amplifier based on main input tube bipolar transistors Q1 and Q2;
the main input module comprises main input tube bipolar transistors Q1 and Q2, corresponding cascode devices Mn1 and Mn2 and a current source I1;
the drains of Mn1 and Mn2 are connected with a load circuit, the grid is connected with a power supply vb, and the sources are respectively connected with the collectors of Q1 and Q2;
the bases of Q2 and Q1 are respectively the positive and negative inputs of an operational amplifier, the emitter is connected with a current source I1, and the current source I1 is grounded.
The input common mode following module is configured to implement input common mode following of the main input module based on bipolar transistors Q3, Q4 connected to the positive and negative inputs of the operational amplifier, and a common mode collecting bipolar transistor Q5, so that the working state of Q5 is consistent with that of the main input transistors Q1, Q2, that is, when the input common mode changes, a slight change Δβ of the current amplification factor β of Q1, Q2 occurs, which is also reflected on Q5, that is, Q5 generates Δβ of the same magnitude.
The input common mode following module comprises bipolar transistors Q3 and Q4, a common mode acquisition bipolar transistor Q5, corresponding cascode devices Mn3, mn4 and Mn5 and a current source I2;
the emitters of the Q3, Q4 and Q5 are connected with a current source I2, and the current source I2 is grounded;
the bases of the Q3 and the Q4 are respectively connected with the positive and negative inputs of the operational amplifier, and the collectors are respectively connected with the sources of the Mn3 and the Mn 4;
the grid electrodes of Mn3 and Mn4 are connected with a power supply vb, and the drain electrodes are connected with a power supply voltage VDD;
the collector electrode of the Q5 is connected with the source electrode of the Mn5, and the base electrode is connected with the feedback module;
and the grid electrode of Mn5 is connected with a power supply vb, and the drain electrode is connected with a feedback module and an adjusting module.
The regulating module comprises bipolar transistors Q6 and Q7, NMOS (N-channel metal oxide semiconductor) transistors Mn7, PMOS (P-channel metal oxide semiconductor) transistors Mp1 and Mp0 and a current source I3;
the drain electrode of the Mp1 is connected with the drain electrode of Mn5, the source electrode is connected with the power supply voltage VDD, and the grid electrode is connected with the grid electrode and the drain electrode of the Mp 0;
the source electrode of the Mp0 is connected with the power supply voltage VDD, and the drain electrode of the Mp0 is connected with the drain electrode of the Mn 7;
the grid electrode of Mn7 is connected with a power supply vb, and the source electrode is connected with the collector electrodes of Q6 and Q7;
the emission sets of Q6 and Q7 are connected with a current source I3, and the current source I3 is grounded;
the bases of the Q6 and the Q7 are respectively connected with the positive input and the negative input of the operational amplifier.
The regulation module provides bias for Mp1 to make collector current of Q5 equal to 0.5I 3-Ib (Q6).
The feedback module is used for collecting the base current Ib1 of the Q5 to the current mirror module;
the feedback module comprises an NMOS tube Mn6, the source electrode of the NMOS tube is connected with the base electrode of Q5, the grid electrode of the NMOS tube is connected with the drain electrode of Mn5, and the drain electrode of the NMOS tube is connected with the current mirror module.
And the current mirror module is used for outputting the Ib1 mirror image to the positive and negative inputs of the operational amplifier according to the proportion k to eliminate the bias current input by the main input module.
The current mirror module PMOS tubes MP2, MP3, MP4;
the sources of Mp2, mp3 and Mp4 are connected with the power supply voltage VDD, the grid is connected with the drain electrode of Mn6, and the drain electrodes are respectively connected with the drain electrode of Mn6 and the positive and negative inputs of the operational amplifier.
In specific implementation, by configuring the mirror ratio k, the base current Ib1 of the input bias currents ib0=q5 of Q1, Q2 is made to achieve complete cancellation of the input bias current.
The current amplification coefficients of Q1, Q2 and Q5 are the same and are beta.
According to fig. 2, the input bias currents ib0=i1/(2×β+1)) of Q1 and Q2, the adjusting module makes the collector current of Q5 equal to 0.5×i3—ib (Q6), and the base current ib1=i3/2×β+1 of Q5, and in addition, since Q3, Q4, Q6, Q7 are also connected to the positive and negative inputs, the base currents of these four devices need to be eliminated. Setting i2=1.5×i3, if Ib (Q3) =ib (Q4) =ib (Q5) =ib (Q6) =ib (Q7), and configuring the mirror ratios k=2+ (I1/(I3)) of Mp2 and Mp3 and Mp2 and Mp4, ib0+ib (Q3) +ib (Q5) =k×ib1, so as to achieve complete cancellation of the input bias current.
Two problems with the old solution corresponding to fig. 1:
1. additional Ib is produced when Q1, Q2 varies.
2. I1 also generates additional Ib as input changes.
In the present scheme, the expression of Ib0 includes both β and I1, meaning that Ib1 can vary with I1 and β. The new input bias current generated by the change of the input common mode can be eliminated. I.e. the problems with the old solutions can be solved.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. The utility model provides an input bias current elimination circuit, includes main input module, input common mode follow module, feedback module, current mirror image module and regulation module, its characterized in that:
the main input module comprises an operational amplifier based on main input tube bipolar transistors Q1 and Q2;
the input common mode following module is used for realizing input common mode following of the main input module based on bipolar transistors Q3 and Q4 which are respectively connected with positive and negative inputs of the operational amplifier and a common mode acquisition bipolar transistor Q5, so that the working state of the Q5 is consistent with that of the main input pipes Q1 and Q2;
the adjusting module is used for adjusting the collector current of Q5;
the feedback module is used for collecting the base current Ib1 of the Q5 to the current mirror module;
and the current mirror module is used for outputting the Ib1 mirror image to the positive and negative inputs of the operational amplifier according to the proportion k to eliminate the bias current input by the main input module.
2. The input bias current cancellation circuit of claim 1, wherein:
the main input module comprises main input tube bipolar transistors Q1 and Q2, corresponding cascode devices Mn1 and Mn2 and a current source I1;
the drains of Mn1 and Mn2 are connected with a load circuit, the grid is connected with a power supply vb, and the sources are respectively connected with the collectors of Q1 and Q2;
the bases of Q2 and Q1 are respectively the positive and negative inputs of an operational amplifier, the emitter is connected with a current source I1, and the current source I1 is grounded.
3. An input bias current canceling circuit according to claim 2 wherein:
the input common mode following module comprises bipolar transistors Q3 and Q4, a common mode acquisition bipolar transistor Q5, corresponding cascode devices Mn3, mn4 and Mn5 and a current source I2;
the emitters of the Q3, Q4 and Q5 are connected with a current source I2, and the current source I2 is grounded;
the bases of the Q3 and the Q4 are respectively connected with the positive and negative inputs of the operational amplifier, and the collectors are respectively connected with the sources of the Mn3 and the Mn 4;
the grid electrodes of Mn3 and Mn4 are connected with a power supply vb, and the drain electrodes are connected with a power supply voltage VDD;
the collector electrode of the Q5 is connected with the source electrode of the Mn5, and the base electrode is connected with the feedback module;
and the grid electrode of Mn5 is connected with a power supply vb, and the drain electrode is connected with a feedback module and an adjusting module.
4. An input bias current canceling circuit according to claim 3 wherein:
the regulating module comprises bipolar transistors Q6 and Q7, NMOS (N-channel metal oxide semiconductor) transistors Mn7, PMOS (P-channel metal oxide semiconductor) transistors Mp1 and Mp0 and a current source I3;
the drain electrode of the Mp1 is connected with the drain electrode of Mn5, the source electrode is connected with the power supply voltage VDD, and the grid electrode is connected with the grid electrode and the drain electrode of the Mp 0;
the source electrode of the Mp0 is connected with the power supply voltage VDD, and the drain electrode of the Mp0 is connected with the drain electrode of the Mn 7;
the grid electrode of Mn7 is connected with a power supply vb, and the source electrode is connected with the collector electrodes of Q6 and Q7;
the emission sets of Q6 and Q7 are connected with a current source I3, and the current source I3 is grounded;
the bases of the Q6 and the Q7 are respectively connected with the positive input and the negative input of the operational amplifier.
5. The input bias current canceling circuit of claim 4 wherein:
the regulation module provides bias for Mp1 to make collector current of Q5 equal to 0.5I 3-Ib (Q6).
6. The input bias current canceling circuit of claim 4 wherein:
the feedback module comprises an NMOS tube Mn6, the source electrode of the NMOS tube is connected with the base electrode of Q5, the grid electrode of the NMOS tube is connected with the drain electrode of Mn5, and the drain electrode of the NMOS tube is connected with the current mirror module.
7. The input bias current canceling circuit of claim 5 wherein:
the current mirror module PMOS tubes MP2, MP3, MP4;
the sources of Mp2, mp3 and Mp4 are connected with the power supply voltage VDD, the grid is connected with the drain electrode of Mn6, and the drain electrodes are respectively connected with the drain electrode of Mn6 and the positive and negative inputs of the operational amplifier.
8. The input bias current canceling circuit of claim 7 wherein:
by configuring the mirror ratio k such that the input bias current Ib0 of Q1, Q2 is equal to the base current Ib1 of Q5, complete cancellation of the input bias current is achieved.
9. The input bias current canceling circuit of claim 8 wherein:
the current amplification coefficients of Q1, Q2 and Q5 are the same and are beta.
10. The input bias current canceling circuit of claim 9 wherein:
the input bias currents ib0=i1/(2×β+1)) of Q1 and Q2, the regulating module makes the collector current of Q5 equal to 0.5×i3-Ib (Q6), the base current ib1=i3/2×β+1 of Q5, and if i2=1.5×i3, it sets ib3=ibb (Q4) =ib5) =ib6=ib7, and the mirror ratios k=2+ (I1/(I3)) of Mp2 and Mp3 and Mp2 and Mp4 are configured so that ib0+ib3) +ib5=k×ib1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111603224.8A CN116339438A (en) | 2021-12-24 | 2021-12-24 | Input bias current eliminating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111603224.8A CN116339438A (en) | 2021-12-24 | 2021-12-24 | Input bias current eliminating circuit |
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| Publication Number | Publication Date |
|---|---|
| CN116339438A true CN116339438A (en) | 2023-06-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111603224.8A Pending CN116339438A (en) | 2021-12-24 | 2021-12-24 | Input bias current eliminating circuit |
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| CN (1) | CN116339438A (en) |
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2021
- 2021-12-24 CN CN202111603224.8A patent/CN116339438A/en active Pending
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