CN116245072B

CN116245072B - Wiring method, device, equipment and storage medium of quantum chip layout

Info

Publication number: CN116245072B
Application number: CN202310233372.8A
Authority: CN
Inventors: 焦晓杨; 杨卓琛; 晋力京
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2023-03-06
Filing date: 2023-03-06
Publication date: 2024-05-14
Anticipated expiration: 2043-03-06
Also published as: CN116245072A

Abstract

The disclosure provides a wiring method, a device, equipment and a storage medium of a quantum chip layout, relates to the technical field of computers, and particularly relates to the field of quantum chips and quantum chip manufacturing. The specific implementation scheme is as follows: based on the device distribution information of the quantum chip layout, obtaining the identification information of each quantum bit in the quantum bit array and the identification information of each coupler in the coupler array; obtaining identification information of a read line port based on the read line distribution information of the quantum chip layout; obtaining identification information of each pin based on the pin distribution information of the quantum chip layout; based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

Description

Wiring method, device, equipment and storage medium of quantum chip layout

Technical Field

The present disclosure relates to the field of computer technology, and in particular, to the field of quantum chips, and quantum chip manufacturing.

Background

With the development of micro-nano processing technology, the number of quantum bits which can be integrated on a quantum chip is increased from several, tens to hundreds, and the integration of thousands of quantum bits is finally realized in the future. Against the ever-increasing demand for the number of qubits, the necessity and urgency of automated design of quantum chips is becoming evident.

Disclosure of Invention

The present disclosure provides a wiring method, apparatus, device and storage medium for quantum chip layout.

According to an aspect of the present disclosure, there is provided a method of wiring a quantum chip layout, including:

Based on the device distribution information of the quantum chip layout, obtaining the identification information of each quantum bit in the quantum bit array and the identification information of each coupler in the coupler array; the device distribution information is used for representing the distribution information of the M rows and N columns of quantum bit arrays arranged in the core area of the quantum chip layout and the distribution information of the coupler arrays arranged in the core area; the coupler in the coupler array is used for connecting two adjacent qubits in the qubit array;

Obtaining identification information of a read line port based on the read line distribution information of the quantum chip layout; the read line distribution information is used for representing the distribution information of M rows of read lines arranged in the core area; the M-th row reading line of the M rows of reading lines is used for reading information of each quantum bit in the M-th row quantum bits; the read line port is positioned at one end of the read line;

Obtaining identification information of each pin based on the pin distribution information of the quantum chip layout; the pin distribution information is used for representing the distribution information of a plurality of pins distributed in the peripheral area of the quantum chip layout; the total number of the plurality of pins is related to the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports;

Based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

According to another aspect of the present disclosure, there is provided a wiring device of a quantum chip layout, including:

the processing unit is used for obtaining the identification information of each quantum bit in the quantum bit array and the identification information of each coupler in the coupler array based on the device distribution information of the quantum chip layout; the device distribution information is used for representing the distribution information of the M rows and N columns of quantum bit arrays arranged in the core area of the quantum chip layout and the distribution information of the coupler arrays arranged in the core area; the coupler in the coupler array is used for connecting two adjacent qubits in the qubit array; obtaining identification information of a read line port based on the read line distribution information of the quantum chip layout; the read line distribution information is used for representing the distribution information of M rows of read lines arranged in the core area; the M-th row reading line of the M rows of reading lines is used for reading information of each quantum bit in the M-th row quantum bits; the read line port is positioned at one end of the read line; obtaining identification information of each pin based on the pin distribution information of the quantum chip layout; the pin distribution information is used for representing the distribution information of a plurality of pins distributed in the peripheral area of the quantum chip layout; the total number of the plurality of pins is related to the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports; based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports;

An output unit for outputting at least one of: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

According to another aspect of the present disclosure, there is provided an electronic device including:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the embodiments of the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform a method according to any one of the embodiments of the present disclosure.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method according to any of the embodiments of the present disclosure.

Therefore, the scheme of the invention can automatically give out the corresponding relation between the pins and the ports of the reading lines and between the pins and the quantum devices according to the input quantum chip layout without other extra operations, has high accuracy and high efficiency at the same time; thus, a foundation is laid for rapid wiring; in addition, the method has important practical value for subsequent quantum chip design automation.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic flow diagram of a routing method for a quantum chip layout according to an embodiment of the present application;

FIGS. 2 (a) and 2 (b) are schematic diagrams illustrating the arrangement of core regions in a quantum chip layout in one example of the present application;

FIG. 3 (a) is a schematic diagram of a quantum chip layout according to an embodiment of the present application;

FIG. 3 (b) is a schematic diagram of a quantum chip layout according to an embodiment of the present application;

FIG. 3 (c) is a schematic diagram of the result of dividing the line region in the core region of the quantum chip layout according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an implementation flow of a routing method of a quantum chip layout in a particular embodiment according to an embodiment of the present disclosure;

FIGS. 5 (a) through 5 (e) are schematic diagrams of automated numbering process in a quantum chip layout according to embodiments of the present disclosure;

FIG. 5 (f) is a diagram of a routing effect in one example of a routing method for a quantum chip layout according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram after automated numbering of a routing method of a quantum chip layout in another example, in accordance with an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a layout of a quantum chip layout of a layout arrangement according to a disclosed embodiment;

fig. 8 is a block diagram of an electronic device for implementing a routing method of a quantum chip layout of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, e.g., including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C. The terms "first" and "second" herein mean a plurality of similar technical terms and distinguishes them, and does not limit the meaning of the order, or only two, for example, a first feature and a second feature, which means that there are two types/classes of features, the first feature may be one or more, and the second feature may be one or more.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be appreciated by one skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Quantum computing is considered as an important direction of research and development in academia and industry as a hallmark technique in the post-molar age. Quantum computing presents significant advantages in solving problems such as large number decomposition over traditional computing; in addition, the method has important significance for leading edge researches of quantum multi-body systems, quantum chemical simulation and the like. In hardware implementation, quantum computing has various technical schemes, such as superconducting circuits, ion traps, optical quantum systems, and the like. Among them, superconducting quantum circuits are considered as the most promising quantum computing hardware candidates in the industry, benefiting from the advantages of long decoherence time, easy manipulation and reading, strong scalability, etc.

As a core carrier of the superconducting quantum circuit technical scheme, development of a superconducting quantum chip integrated with a plurality of quantum bits is of great importance. With the development of micro-nano processing technology, the number of quantum bits which can be integrated on a superconducting quantum chip is increased from several, tens to hundreds, and the integration of thousands of quantum bits is finally realized in the future. Against the increasing demand of the number of the quantum bits, the necessity and urgency of the design of the superconducting quantum chip layout are increasingly revealed.

The design of the superconducting quantum chip layout (hereinafter, simply referred to as quantum chip layout) includes the design of the core device, the design of the coupling port, the design of the wiring, and the like. In the design of wiring, for a single qubit, one or two control lines (such as flux control lines, or microwave control lines) connected to an external control system of the superconducting quantum chip (depending on the different superconducting quantum chip architecture) are often required to achieve manipulation of the qubit. In addition, additional read lines are required to read single or multiple qubits. In superconducting quantum chips with Coupler structures, each Coupler (which can be considered as a qubit with adjustable frequency) also requires a flux control line connected to an external control system. In short, due to the limitation of wiring rules and micro-nano technology, with the increase of the number of quantum bits in the superconducting quantum chip, the number of measurement and control lines (control lines and reading lines can be collectively called as measurement and control lines) can be increased, the size of the whole quantum chip layout can be inevitably increased, and the design difficulty is increased.

The importance of automated design of superconducting quantum chips (Quantum Electronic design automation, QEDA) is increasingly pronounced, in analogy to the function of electronic design automation (Electronic design automation, EDA) of classical chips. In the whole automatic design flow of the superconducting quantum chip, the design of the wiring is a very important part, for example, from the initial design of the quantum chip layout to the measurement and control of the superconducting quantum chip, a measurement and control port and pins corresponding to the measurement and control port and the pins need to be marked very accurately; in practice, the port corresponding to each pin needs to be known, so that the effect of the pin can be judged, and the device is further used for calibrating and measuring and controlling the superconducting quantum chip. However, in the current design flow of the quantum chip layout, the measurement and control line and the pin are mainly identified by means of eyesight, and the method is low in efficiency and high in error rate, so that a scheme capable of automatically giving the corresponding relation between the port and the pin according to the layout of the quantum chip layout is needed.

Based on this, the present disclosure proposes an addressing method of a quantum chip layout, which can quickly obtain a mapping relationship between a quantum bit and a pin, a mapping relationship between a coupler and a pin, and a mapping relationship between a read line port and a pin, so as to quickly obtain an addressing result, for example, quickly obtain a quantum bit corresponding to a pin.

It should be noted that, in the present disclosure, the horizontal direction is defined as a row, the vertical direction is defined as a column, and in practical application, other defining manners are also possible, and at this time, only the adaptive adjustment needs to be performed on the present disclosure, which is not limited thereto.

In particular, FIG. 1 is a schematic flow chart of a routing method of a quantum chip layout according to an embodiment of the application. The method is optionally applied in classical computing devices, such as personal computers, servers, server clusters, etc. with classical computing capabilities. The method includes at least some of the following. As shown in fig. 1, includes:

Step S101: based on the device distribution information of the quantum chip layout, the identification information of each quantum bit in the quantum bit array and the identification information of each coupler in the coupler array are obtained.

Here, the device distribution information is used to represent the distribution information of the M row×n column qubit array arranged in the core region of the quantum chip layout, and the distribution information of the coupler array arranged in the core region; the couplers in the coupler array are used for connecting two adjacent qubits in the qubit array.

Here, M is a positive integer greater than or equal to 2, N is a positive integer greater than or equal to 2, and the values of M and N are the same or different, which is not limited in this disclosure.

Step S102: and obtaining the identification information of the read line port based on the read line distribution information of the quantum chip layout.

Here, the read line distribution information is used to represent the distribution information of M rows of read lines arranged in the core region; the M-th row reading line of the M rows of reading lines is used for reading information of each quantum bit in the M-th row quantum bits; the read line port is located at one end of the read line.

Step S103: and obtaining the identification information of each pin based on the pin distribution information of the quantum chip layout.

Here, the pin distribution information is used for representing distribution information of a plurality of pins arranged in a peripheral area of the quantum chip layout; the total number of the plurality of pins is related to the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports.

It is noted that the peripheral region of the quantum chip layout may represent at least a partial region other than the core region of the quantum chip layout.

Step S104: based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

It should be noted that, the quantum chip layout according to the present disclosure is used to describe physical structures of quantum devices in a real quantum chip (or superconducting quantum chip), including, but not limited to, shapes, areas, positions, etc. of each physical structure on the quantum chip.

In a specific example, the quantum chip layout is a layout depicting a physical structure of the quantum chip. Therefore, the scheme disclosed by the invention can be applied to the quantum chip, and has important practical value for the design and simulation work of the quantum chip.

Or in another specific example, the quantum chip layout is a layout for describing a physical structure of the superconducting quantum chip. Therefore, the scheme disclosed by the invention can be applied to the superconducting quantum chip, and has important practical value for the design and simulation work of the superconducting quantum chip.

Here, the superconducting quantum chip refers to a quantum chip prepared from a superconducting material. For example, all components (such as qubits, coupling devices, etc.) in the superconducting quantum chip are made of superconducting materials.

In this way, the scheme of the disclosure obtains the mapping relation between the pins and the reading line ports and the mapping relation between the pins and the quantum devices by inputting various distribution information in the quantum chip layout, the obtained identification information of the quantum bits, the identification information of the coupler, the identification information of the reading line ports and the identification information of the pins, and further obtains the mapping relation between the pins and the reading line ports and the mapping relation between the pins and the quantum devices based on the identification information, so that the scheme can automatically give out the corresponding relation between the pins and the reading line ports and the corresponding relation between the pins and the quantum devices according to the input distribution information without additional operation, and has high accuracy and high efficiency; thus, a foundation is laid for rapid wiring; in addition, the method has important practical value for subsequent quantum chip design automation.

In a specific example, based on the device distribution information and the read line distribution information of the quantum chip layout, identification information of each quantum bit in the quantum bit array, identification information of each coupler in the coupler array and identification information of the read line port are obtained. That is, in this example, after the distribution information corresponding to the core region is obtained, the identification information of the quantum devices arranged in the core region and the identification information of the reading line ports of the reading lines arranged in the core region can be determined.

In a specific example of the present disclosure, the total number of the plurality of pins is equal to the sum of the following numbers: the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports. At this time, the pins are in one-to-one correspondence with the ports of the reading lines, the pins are in one-to-one correspondence with the qubits, and the pins are in one-to-one correspondence with the couplers, so that structural support is provided for calibrating or measuring the quantum devices or the reading lines corresponding to the pins through the pins.

It will be appreciated that since the couplers in the coupler array are used to connect two adjacent qubits in the qubit array, the coupler array can be determined in the case where the qubit array is determined to be M rows by N columns.

Further, in a specific example, the coupler array includes a transverse coupler array of M rows by (N-1) columns and a longitudinal coupler array of (M-1) rows by N columns; wherein, the transverse couplers in the transverse coupler array are used for connecting two adjacent quantum bits in the same row; the longitudinal couplers in the longitudinal coupler array are used for connecting two adjacent quantum bits in the same column.

For example, the transverse coupler of the ith row in the transverse coupler array is arranged in the ith row in the quantum bit array and is used for connecting two adjacent quantum bits in the ith row; and the longitudinal coupler of the j-th column in the longitudinal coupler array is arranged in the j-th column in the quantum bit array and is used for connecting two adjacent quantum bits in the j-th column, wherein i is a positive integer which is more than or equal to 1 and less than or equal to M, and j is a positive integer which is more than or equal to 1 and less than or equal to N.

Therefore, the scheme can connect two adjacent quantum bits in the quantum bit array through the transverse coupler and the longitudinal coupler, so that the quantum chip has good expansibility under the condition that the number of the quantum bits is continuously increased, and the research and development efficiency of the quantum chip is greatly improved.

In a specific example of the scheme of the disclosure, after the mapping relation is obtained, the peripheral wiring layer in the quantum chip layout can be automatically wired; specifically comprises at least one of the following:

Extending a control line corresponding to a control port of the quantum bit to a pin position with a mapping relation with the quantum bit;

Extending a control line corresponding to a control port of a coupler to a pin with a mapping relation with the coupler;

And extending the reading line corresponding to the reading line port to a pin with a mapping relation with the reading line port.

In this way, in the subsequent measurement and control process, the corresponding relation among the pin, the measurement and control line (control line or reading line) and the quantum device (such as the quantum bit or the coupler) is conveniently utilized, and thus structural support is provided for realizing reading and controlling of the quantum bit.

Moreover, the wiring scheme provided by the scheme is simple to operate, low in use threshold and high in efficiency.

In a specific example of the solution of the present disclosure, in order for the M-th row of the readout lines to facilitate reading of information of each qubit in the M-th row of the qubits, the M-th row of the readout lines may be located on an upper row or a lower row of the M-th row of the qubits. In this way, the reading of data of one row of qubits by the reading line is facilitated.

In a specific example of the scheme of the present disclosure, the mth row of read lines is located in a next row of the mth row of qubits; specifically, in the case where M is any one of 1 to M-1, the mth row read line is located between the mth row qubit and the mth row longitudinal coupler; in the case where M takes on the value of M, the M-th row read line is located in the next row of the M-th row qubits.

In this disclosure, a coordinate system is constructed with a horizontal direction as an X-axis direction and a vertical direction as a Y-axis direction, as shown in fig. 2 (a) and 2 (b), where a positive Y-axis direction is defined as up, a negative Y-axis direction is down, a positive X-axis direction is left, and a negative X-axis direction is right.

Further, as shown in fig. 2 (a), for example, the qubit array in the quantum chip layout is 4 rows×4 columns, the longitudinal coupler array is 3 rows×4 columns, and the lateral coupler array is 4 rows×3 columns; further, in the case where m is any one of values 1 to 3, the mth row read line is located between the mth row qubit and the mth row longitudinal coupler, for example, in the case where m is a value 1, the first row read line is located between the first row qubit and the first row longitudinal coupler; under the condition that m takes a value of 2, a second row of reading lines are positioned between the second row of quantum bits and the second row of longitudinal couplers; under the condition that m takes a value of 3, a third row of reading lines are positioned between the third row of quantum bits and the third row of longitudinal couplers; and in the case where m takes a value of 4, the fourth row read line is located in the next row of the fourth row qubits.

Or in another specific example, the mth row read line is located in the upper row of the mth row qubits; specifically, in the case where M is any one of 2 to M, the mth row read line is located between the mth row qubit and the mth-1 row longitudinal coupler; in the case where m takes a value of 1, the first row read line is located in the upper row of the first row qubits.

For example, as shown in fig. 2 (b), the qubit array in the quantum chip layout is 4 rows×4 columns, the longitudinal coupler array is 3 rows×4 columns, and the transverse coupler array is 4 rows×3 columns; further, in the case where m is any one of values 2 to 4, the mth row read line is located between the mth row qubit and the m-1 th row longitudinal coupler, for example, in the case where m is a value 2, the second row read line is located between the second row qubit and the first row longitudinal coupler; under the condition that m takes a value of 3, the third row of reading lines are positioned between the third row of quantum bits and the second row of longitudinal couplers; under the condition that m takes a value of 4, the fourth row of reading lines are positioned between the fourth row of quantum bits and the third row of longitudinal couplers; and in the case where m takes a value of 1, the first row read line is located in the upper row of the first row qubits.

Therefore, the scheme reads the information of one layer of quantum bits through the reading line, and the structure can enable the quantum chip to have good expansibility under the condition that the number of the quantum bits is continuously increased, so that the research and development efficiency of the quantum chip is greatly improved.

In a specific example of the scheme of the present disclosure, the identification information of each quantum device, the identification information of the coupler, and the identification information of the read line port may be obtained in the following manner; specifically, the device distribution information based on the quantum chip layout described above obtains identification information of each quantum bit in the quantum bit array and identification information of each coupler in the coupler array, and obtains identification information of a read line port based on read line distribution information of the quantum chip layout, including:

Step S201: dividing the core region based on the distribution information of M rows of quantum bits in the device distribution information and the distribution information of M rows of reading lines in the reading line arrangement information to obtain M rows of regions to be processed;

step S202: sequentially numbering the quantum bits, the couplers and the reading line ports in each row of the M rows of the to-be-processed areas to obtain identification information of the quantum bits, the identification information of the couplers and the identification information of the reading line ports in each row of the to-be-processed areas.

In an example, after the number of each quantum device (such as a qubit or a coupler) is obtained, the number of the quantum device may be directly used as the identification information of the quantum device, and after the number of the read line port is obtained, the number of the read line port may be used as the identification information of the read line port.

It can be understood that in an actual scenario, after the number is obtained, corresponding identification information can be obtained based on the number, for example, after the number is correspondingly processed, the identification information is obtained.

Step S203: and obtaining the identification information of each pin based on the pin distribution information of the quantum chip layout.

It is understood that the order of obtaining the identification information of the pins and the order of obtaining the identification information corresponding to the core area may be exchanged, which is not limited by the scheme of the present disclosure.

It should be noted that the identification information in the core area is different from each other, that is, the identification information of the quantum bit in the core area, the identification information of the coupler and the identification information of the reading line port are different from each other, so that the quantum device in the core area can be uniquely indicated, or the reading line port in the core area can be uniquely indicated, and a foundation is laid for matching different pins for each quantum device and the reading line port in the follow-up.

Correspondingly, the identification information in the peripheral area is also different from each other, namely, the identification information of different pins in the peripheral area is different, so that the pins in the peripheral area can be uniquely indicated, and a foundation is laid for matching different pins for each quantum device and the reading line port.

Step S204: based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

In a specific example, the setting rule of the identification information of the pin is related to the setting rule of the identification information corresponding to the core area, so that the core area has the identification information with the preset corresponding relation with the identification information of the pin, for example, the core area has the same identification information as the identification information of the pin, so that the mapping relation (one-to-one correspondence relation) is established between the pin with the preset corresponding relation of the identification information and the quantum device or between the pin and the control line port, and support is provided for the follow-up realization of the automatic wiring of the peripheral wiring layer.

It should be noted that, the mapping between the pins and the quantum device, and between the pins and the control line port can be performed based on other rules, and the specific mapping mode is not limited by the scheme of the present disclosure; for example, the preset numbers are all from the left side, and after the left side numbers are completed, the right side is numbered from the first row; specifically, the quantum devices and the reading line ports in the left area of the core area are numbered preferentially, pins in the left half part are numbered, and matching is further performed based on the sequence of the numbers, namely, a one-to-one mapping relation is established between the ith numbered quantum device or the reading line port in the left area of the core area and the ith numbered pin, a one-to-one mapping relation is established between the (i+1) th numbered quantum device or the reading line port in the left area of the core area and the (i+1) th numbered pin, and the mapping relation between all the quantum devices or the reading line ports in the left area of the core area and all the pins in the left half part is obtained by the same way. Similarly, the quantum devices or the reading line ports in the right side area of the core area are corresponding to the pins in the right half part in a similar manner, so that the mapping relation between the quantum devices or the reading line ports in the right side area of the core area and the pins in the right half part is obtained.

In this way, the core area can be divided, M rows of areas to be processed are obtained, and then the areas to be processed in the M rows of areas to be processed are numbered sequentially, so that the corresponding relation between the pins and the ports of the reading line and the corresponding relation between the pins and the quantum devices can be automatically given, the accuracy is high, meanwhile, the efficiency is high, and a foundation is laid for rapid wiring; in addition, the method has important practical value for subsequent quantum chip design automation.

In a specific example of the present disclosure, the above-mentioned sequential numbering of the qubits, the couplers and the read line ports in each of the M rows of the to-be-processed regions (i.e. the sub-steps in step S202) specifically includes:

numbering the M-th row of the M-row of the areas to be processed according to the following manner:

Under the condition that a control line led out by a quantum device positioned in the middle area in the m-th row of the area to be processed extends towards the outer edge of the right side, the quantum device positioned in the middle area of the m-th row of the area to be processed is used as the quantum device in the right area of the m-th row of the area to be processed; or under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed extends towards the outer edge of the left side, the quantum device in the middle area of the m-th row of the area to be processed is used as the quantum device in the left side area of the m-th row of the area to be processed; the quantum device is a qubit or a coupler;

The quantum devices or control line ports in the left side area in the m-th row of the area to be processed are connected with the maximum number of the left side area of the m-1 th row of the area to be processed, and the serial numbers are carried out;

and the quantum devices or control line ports in the m-th row of the to-be-processed area and positioned in the right side area are connected with the maximum number of the right side area of the m-1-th row of the to-be-processed area, and the serial numbers are carried out.

Thus, after the processing of the M rows of to-be-processed areas is completed in the above manner, the numbers of all quantum devices and the numbers of all reading line ports in the core area can be obtained, and further the identification information of all quantum devices and the identification information of all reading line ports are obtained.

In this way, the scheme of the disclosure provides a specific automatic numbering mode, which has high accuracy and high efficiency; thus, a foundation is laid for rapid wiring; in addition, the method has important practical value for subsequent quantum chip design automation.

The numbering step of the quantum devices or control line ports in the left region of the m-th row of regions to be processed is described in detail below.

It is to be noted that a coordinate system may be constructed based on the manner shown in fig. 2 (a) or fig. 2 (b), in which case the core region may be divided into a left region, a middle region, and a right region. It can be understood that the left area, the middle area and the right area are all relative positions, and other division manners are also possible in the actual scene, which is not particularly limited in the present disclosure. Further, the left area of the m-th row of the areas to be processed may specifically refer to an area located at the left area of the core area among the m-th row of the areas to be processed.

In a specific example of the solution of the present disclosure, the quantum devices or control line ports located in the left area in the m-th row of to-be-processed area may be sequentially numbered in such a manner that the quantum devices or control line ports located in the left area in the m-th row of to-be-processed area described above are sequentially numbered, and then the maximum number of the left area in the m-1-th row of to-be-processed area is sequentially numbered, which specifically includes:

And under the condition that a control line led out by the quantum devices in the middle area in the m-th row to-be-processed area is led out upwards and extends towards the outer edge of the left side, continuing the maximum number of the left side area of the m-1-th row to-be-processed area, numbering the quantum devices in the middle area of the m-th row to-be-processed area, and continuing the numbers of the quantum devices in the middle area of the m-th row to-be-processed area according to a preset sequence (such as the direction from the upper part to the lower part and from the outer edge to the center), and sequentially numbering other quantum devices and control line ports in the left side area in the m-th row to-be-processed area. That is, in this embodiment, when the control line led out from the quantum device located in the middle area in the m-th row to-be-processed area is led out upward and extends toward the left outer edge, the quantum device in the middle area is preferentially numbered, and after the numbering, the other quantum devices or the control line ports in the m-th row to-be-processed area are sequentially numbered based on the number of the quantum device in the middle area.

Or alternatively

And under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed is led out downwards and extends towards the outer edge of the left side, continuing the maximum number of the left side area of the m-1-th row of the area to be processed, and sequentially numbering the quantum device and the control line port of the left side area in the m-th row of the area to be processed according to a preset sequence (such as according to the direction from top to bottom and from the outer edge to the center). That is, in this embodiment, in the case where the control line led out from the quantum device located in the middle area in the m-th row to-be-processed area is led out downward and extends toward the outer edge of the left side, the quantum devices in the middle area are not numbered preferentially, but the maximum number of the left area of the m-1-th row to-be-processed area is sequentially numbered in the preset order, and the quantum devices and the control line ports of the left area in the m-th row to-be-processed area are sequentially numbered.

It should be noted that, when the value of m is 1, the m-th row of area to be processed is the first row of area to be processed, and at this time, the quantum devices and the control line ports in the left area of the first row of area to be processed are numbered according to the above manner based on the preset starting number.

For example, for the first row of to-be-processed regions, if the control line led out by the quantum device located in the middle region is led out upwards and extends towards the outer edge of the left side, at this time, starting with a preset starting number, the quantum devices in the middle region of the first row of to-be-processed regions are numbered, and then, the other quantum devices and the control line ports in the left side region of the first row of to-be-processed regions are numbered sequentially according to a preset sequence (for example, according to the direction from top to bottom and from the outer edge to the center) continuing with the number of the quantum devices in the middle region of the first row of to-be-processed regions. Or for the first row of to-be-processed regions, if the control line led out by the quantum device located in the middle region is led out downwards and extends towards the outer edge of the left side, starting with a preset starting number, and sequentially numbering the quantum devices and the control line ports of the left side region in the first row of to-be-processed regions according to a preset sequence (such as according to the direction from top to bottom and from the outer edge to the center).

In this way, the scheme of the disclosure provides a specific automatic numbering mode, and the numbers of all quantum devices and reading line ports in the left side area of the core area can be obtained without additional other operations, so that the identification information of all quantum devices and the identification information of reading line ports in the left side area of the core area are obtained, and support is provided for the subsequent realization of automatic wiring of the peripheral wiring layer.

Further, in a specific example, the mth row read line is located in a next row of the mth row qubits; at this time, in the case where M is any one of values 1 to M-1, the M-th row of the area to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

At this time, under the condition that the control line led out by the quantum device in the middle area in the m-th row to-be-processed area is led out upwards and extends towards the left outer edge, continuing the maximum number of the left area of the m-1-th row to-be-processed area, numbering the quantum devices in the middle area of the m-th row to-be-processed area, continuing the number of the quantum devices in the middle area of the m-th row to-be-processed area according to a preset sequence, and sequentially numbering the ports of other quantum devices and control lines in the left area of the m-th row to-be-processed area, wherein the method specifically comprises the following steps:

Under the condition that a control line led out by a quantum device in the middle area of the first subarea m1 in the m-th row to-be-processed area is led out upwards and extends towards the left outer edge, continuing the maximum number of the left area of the m-1-th row to-be-processed area, and numbering the quantum device in the middle area of the first subarea m1; and, serial numbering of quantum devices in the middle area of the first sub-area m1, and serial numbering of other quantum devices in the left area of the first sub-area m1 is performed according to a preset sequence (for example, from the outer edge to the center);

continuing the maximum number of the left side area of the first subarea m1, and numbering the control line port on the left side of the second subarea m 2;

And under the condition that a third sub-area m3 exists in the m-th row of to-be-processed area, continuing the serial numbers of the control line ports on the left side of the second sub-area m2, and sequentially numbering the quantum devices in the area on the left side of the third sub-area m3 according to a preset sequence (for example, the direction from the outer edge to the center).

When M is any one of 1 to M-1, the third sub-region M3 exists in the M-th row of to-be-processed regions, and at this time, the maximum number of the left region of the third sub-region M3 in the M-th row of to-be-processed regions is the maximum number of the left region of the M-th row of to-be-processed regions. And under the condition that the value of M is M, the third sub-region M3 does not exist in the M-th row of to-be-processed region, and at the moment, the number of the control line port at the left side of the second sub-region M2 in the M-th row of to-be-processed region is the maximum number of the left side region of the M-th row of to-be-processed region, namely the maximum number of the left side region in the core region.

Further, in another specific example, the mth row read line is located at a next row of the mth row qubits; at this time, in the case where M is any one of values 1 to M-1, the M-th row of the area to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m1 corresponding to one row of reading lines;

at this time, under the condition that the control line led out by the quantum device in the middle area in the m-th row to-be-processed area is led out downwards and extends towards the left outer edge, continuing the maximum number of the left area of the m-1-th row to-be-processed area, and sequentially numbering the quantum device and the control line port of the left area in the m-th row to-be-processed area according to a preset sequence, specifically including:

Under the condition that a control line led out by the quantum devices in the middle area of the first subarea m1 is led out downwards and extends towards the outer edge of the left side in the m-th row of to-be-processed areas, continuing the maximum number of the left side area of the m-1 th row of to-be-processed areas, and sequentially numbering the quantum devices in the left side area of the first subarea m1 according to a preset sequence (for example, the direction from the outer edge to the center);

The method and the device provide a specific automatic numbering mode, and numbers of all quantum devices and all reading line ports in a core area can be obtained without additional other operations, so that identification information of all quantum devices and identification information of all reading line ports are obtained, and support is provided for subsequent automatic wiring of a peripheral wiring layer.

Further, in yet another specific example, the mth row read line is located at a row above the mth row qubit; at this time, in the case where M is any one of values 1 to M-1, the M-th row of the area to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

In the m-th row of to-be-processed area, continuing the maximum number of the left area of the m-1-th row of to-be-processed area, and numbering the control line port on the left side of the first sub-area m 1;

In the m-th row of to-be-processed area, under the condition that a control line led out by a quantum device in the middle area of the second sub-area m2 is led out upwards and extends towards the outer edge of the left side, continuing the serial number of a control line port of the left side of the first sub-area m1, and numbering the quantum device in the middle area of the second sub-area m2; and the number of the quantum devices in the middle area of the second sub-area m2 is continued, and the other quantum devices in the left area of the second sub-area m2 are numbered sequentially according to a preset sequence (for example, the direction from the outer edge to the center);

And under the condition that a third sub-area m3 exists in the m-th row of to-be-processed area, continuing the maximum number of the left side area of the second sub-area m2, and sequentially numbering the quantum devices of the left side area of the third sub-area m3 according to a preset sequence (for example, the direction from the outer edge to the center).

When M is any one of 1 to M-1, the third sub-region M3 exists in the M-th row of to-be-processed regions, and at this time, the maximum number of the left region of the third sub-region M3 in the M-th row of to-be-processed regions is the maximum number of the left region of the M-th row of to-be-processed regions. And under the condition that the value of M is M, the third sub-region M3 does not exist in the M-th row of to-be-processed region, and at the moment, the maximum number of the left side region of the second sub-region M2 in the M-th row of to-be-processed region is the maximum number of the left side region of the M-th row of to-be-processed region, namely the maximum number of the left side region in the core region.

Under the condition that a control line led out from the quantum devices in the middle area of the second subarea m2 in the m-th row to-be-processed area is led out downwards and extends towards the outer edge of the left side, serial numbers of control line ports on the left side of the first subarea m1 are continued, and the quantum devices in the left side area of the second subarea m2 are sequentially numbered according to a preset sequence (for example, the direction from the outer edge to the center);

The following describes in detail the numbering step of the quantum devices or control line ports in the right region of the m-th row of regions to be processed.

In a specific example of the solution of the present disclosure, the quantum devices or control line ports located in the right area in the m-th row of to-be-processed area may be sequentially numbered, that is, the quantum devices and control line ports located in the right area in the m-th row of to-be-processed area described above, are sequentially numbered, and then the maximum number of the right area in the m-1-th row of to-be-processed area is sequentially numbered, which specifically includes:

And under the condition that a control line led out by the quantum devices in the middle area in the m-th row to-be-processed area is led out upwards and extends towards the outer edge of the right side, continuing the maximum number of the right side area of the m-1-th row to-be-processed area, numbering the quantum devices in the middle area of the m-th row to-be-processed area, and continuing the numbers of the quantum devices in the middle area of the m-th row to-be-processed area according to a preset sequence (such as the direction from top to bottom and from the outer edge to the center), and sequentially numbering other quantum devices and control line ports in the right side area in the m-th row to-be-processed area. That is, in this embodiment, when the control line led out from the quantum device located in the middle area in the m-th row to-be-processed area is led out upward and extends toward the outer edge on the right side, the quantum device in the middle area is preferentially numbered, and after the numbering, the other quantum devices or the control line ports in the m-th row to-be-processed area are sequentially numbered based on the number of the quantum device in the middle area.

Or alternatively

And under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed is led out downwards and extends towards the outer edge on the right side, continuing the maximum number of the right side area of the m-1-th row of the area to be processed, and sequentially numbering the quantum device and the control line port of the right side area in the m-th row of the area to be processed according to a preset sequence (such as according to the direction from top to bottom and from the outer edge to the center). That is, in this embodiment, in the case where the control line led out from the quantum device located in the middle area in the m-th row to-be-processed area is led out downward and extends toward the outer edge on the right side, the quantum devices in the middle area are not numbered preferentially, but the maximum number of the right area of the m-1-th row to-be-processed area is followed, and the quantum devices and the control line ports in the right area in the m-th row to-be-processed area are numbered sequentially.

For example, for the first row of to-be-processed regions, if the control line led out by the quantum device located in the middle region is led out upwards and extends towards the outer edge of the right side, at this time, starting with a preset starting number, the quantum devices in the middle region of the first row of to-be-processed regions are numbered, and then, the other quantum devices and the control line ports in the right side region of the first row of to-be-processed regions are numbered sequentially according to a preset sequence (for example, according to the direction from top to bottom and from the outer edge to the center) continuing with the number of the quantum devices in the middle region of the first row of to-be-processed regions. Or for the first row of to-be-processed regions, if the control line led out by the quantum device located in the middle region is led out downwards and extends towards the outer edge of the right side, starting with a preset starting number, and sequentially numbering the quantum devices and the control line ports of the right side region in the first row of to-be-processed regions according to a preset sequence (for example, according to the direction from top to bottom and from the outer edge to the center).

In this way, the scheme of the disclosure provides a specific automatic numbering mode, and the numbers of all quantum devices and reading line ports in the right side area of the core area can be obtained without additional other operations, so that the identification information of all quantum devices and the identification information of reading line ports in the right side area of the core area are obtained, and support is provided for the subsequent realization of automatic wiring of the peripheral wiring layer.

At this time, under the condition that the control line led out by the quantum device in the middle area in the m-th row to-be-processed area is led out upwards and extends towards the outer edge of the right side, continuing the maximum number of the right side area of the m-1-th row to-be-processed area, numbering the quantum devices in the middle area of the m-th row to-be-processed area, continuing the number of the quantum devices in the middle area of the m-th row to-be-processed area according to a preset sequence, and sequentially numbering the other quantum devices and the ports of the control line in the right side area of the m-th row to-be-processed area, wherein the method specifically comprises the following steps:

under the condition that a control line led out by a quantum device in the middle area of the first subarea m1 in the m-th row to-be-processed area is led out upwards and extends towards the outer edge of the right side, continuing the maximum number of the right side area of the m-1-th row to-be-processed area, and numbering the quantum device in the middle area of the first subarea m 1; and the number of the quantum devices in the middle area of the first sub-area m1 is continued, and the other quantum devices in the right area of the first sub-area m1 are numbered sequentially according to a preset sequence (for example, the direction from the outer edge to the center);

Continuing the maximum number of the right side area of the first subarea m1, and numbering the control line port on the right side of the second subarea m 2;

and under the condition that a third sub-area m3 exists in the m-th row of to-be-processed area, continuing the serial numbers of the control line ports on the right side of the second sub-area m2, and sequentially numbering the quantum devices in the area on the right side of the third sub-area m3 according to a preset sequence (for example, the direction from the outer edge to the center).

When M is any one of 1 to M-1, the third sub-region M3 exists in the M-th row of to-be-processed regions, and at this time, the maximum number of the right region of the third sub-region M3 in the M-th row of to-be-processed regions is the maximum number of the right region of the M-th row of to-be-processed regions. And under the condition that the value of M is M, the third sub-region M3 does not exist in the M-th row of to-be-processed region, and at the moment, the number of the control line port on the right side of the second sub-region M2 in the M-th row of to-be-processed region is the maximum number of the right side region of the M-th row of to-be-processed region, namely the maximum number of the right side region in the core region.

Further, in another specific example, the mth row read line is located at a next row of the mth row qubits; at this time, in the case where M is any one of values 1 to M-1, the M-th row of the area to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

at this time, under the condition that the control line led out from the quantum device located in the middle area in the m-th row to-be-processed area is led out and extends towards the outer edge of the right side, continuing the maximum number of the right area of the m-1-th row to-be-processed area, and sequentially numbering the quantum device and the control line port of the right area in the m-th row to-be-processed area according to a preset sequence, wherein the method specifically comprises the following steps of

Under the condition that a control line led out by the quantum devices in the middle area of the first subarea m1 is led out downwards and extends towards the outer edge of the right side in the m-th row of to-be-processed area, continuing the maximum number of the right side area of the m-1 th row of to-be-processed area, and sequentially numbering the quantum devices in the right side area of the first subarea m1 according to a preset sequence (for example, the direction from the outer edge to the center);

in the m-th row of to-be-processed area, continuing the maximum number of the right side area of the m-1-th row of to-be-processed area, and numbering the control line port on the right side of the first sub-area m 1;

In the m-th row of to-be-processed area, under the condition that a control line led out by a quantum device in the middle area of the second sub-area m2 is led out upwards and extends towards the outer edge of the right side, continuing the serial number of a control line port on the right side of the first sub-area m1, and numbering the quantum device in the middle area of the second sub-area m2; and the number of the quantum devices in the middle area of the second sub-area m2 is continued, and the other quantum devices in the right area of the second sub-area m2 are numbered sequentially according to a preset sequence (for example, the direction from the outer edge to the center);

And under the condition that a third sub-area m3 exists in the m-th row of to-be-processed area, continuing the maximum number of the right side area of the second sub-area m2, and sequentially numbering the quantum devices of the right side area of the third sub-area m3 according to a preset sequence (for example, the direction from the outer edge to the center).

When M is any one of 1 to M-1, the third sub-region M3 exists in the M-th row of to-be-processed regions, and at this time, the maximum number of the right region of the third sub-region M3 in the M-th row of to-be-processed regions is the maximum number of the right region of the M-th row of to-be-processed regions. And under the condition that the value of M is M, the third sub-region M3 does not exist in the M-th row of to-be-processed region, and at the moment, the maximum number of the right side region of the second sub-region M2 in the M-th row of to-be-processed region is the maximum number of the right side region of the M-th row of to-be-processed region, namely the maximum number of the right side region in the core region.

Under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed is led out downwards and extends towards the outer edge of the right side, continuing the maximum number of the area on the right side of the m-1-th row of the area to be processed, and sequentially numbering the quantum device and the control line port of the area on the right side in the m-th row of the area to be processed according to a preset sequence, wherein the method specifically comprises the following steps:

Under the condition that a control line led out from the quantum devices in the middle area of the second subarea m2 in the m-th row to-be-processed area is led out downwards and extends towards the outer edge on the right side, serial numbers of control line ports on the right side of the first subarea m1 are continued, and the quantum devices in the right side area of the second subarea m2 are sequentially numbered according to a preset sequence (for example, the direction from the outer edge to the center);

The numbering step of the plurality of pins arranged in the peripheral region is described in detail below.

In the scheme of the disclosure, the plurality of pins are arranged in a single row around the peripheral area; or the pins are arranged in a double-row and staggered manner around the peripheral area, so that a mapping relationship with the ports of the quantum devices or the reading lines in the core area is conveniently established.

In a specific example of the present disclosure, the pins arranged in the peripheral area may be sequentially numbered in a manner that the above-mentioned pin distribution information based on the quantum chip layout obtains the identification information of each pin (i.e. the above-mentioned step S103 or the above-mentioned step S203), which specifically includes:

Step S301: and selecting a first pin and a second pin from a plurality of pins based on the pin distribution information of the quantum chip layout, wherein the connection line of the first pin and the second pin can divide the quantum chip layout into a left half part and a right half part.

It should be noted that a coordinate system may be constructed based on the manner shown in fig. 2 (a) or fig. 2 (b), in which case the quantum chip layout may be divided into left and right halves. Or the quantum chip layout can be further divided into an upper half and a lower half. In an actual scenario, there may be other division modes, and the scheme of the present disclosure is not limited in particular.

Step S302: starting from the first pin, sequentially numbering pins positioned at the left half part of the quantum chip layout according to a first direction until the pin which is positioned before the second pin.

For example, taking the example that the first pin is located in the upper half of the quantum chip layout and the second pin is located in the lower half of the quantum chip layout, pins located in the left half of the quantum chip layout may be sequentially numbered from the first pin in a counterclockwise direction until the previous pin of the second pin.

Step S303: and starting from the first pin, sequentially numbering pins positioned at the right half part of the quantum chip layout according to a second direction opposite to the first direction until the pin which is positioned before the second pin.

For example, the first pin is located at the upper half part of the quantum chip layout, and the second pin is located at the lower half part of the quantum chip layout, and at this time, pins located at the right half part of the quantum chip layout are numbered sequentially from the first pin in a clockwise direction until the previous pin of the second pin.

It will be appreciated that the order of execution of step S302 and step S303 may be reversed, and the present disclosure is not limited in this regard.

Step S304: based on the first preset number of the first pin, the first preset number of the second pin and the numbers of other pins, the identification information of each pin is obtained.

It can be understood that in an actual scenario, after the serial number of the pin is obtained, the serial number of the pin can be directly used as the identification information of the pin, or the identification information of the pin is obtained after the serial number of the pin is correspondingly processed, which is not limited in this aspect of the present disclosure, as long as the identification information corresponding to the peripheral area can uniquely indicate the pin.

It should be noted that, in a specific example, the pins located at the left half of the quantum chip layout are specifically used for establishing a mapping relationship with the quantum devices or the reading line ports in the left area of the core area, and correspondingly, the pins located at the right half of the quantum chip layout are specifically used for establishing a mapping relationship with the quantum devices or the reading line ports in the right area of the core area.

Further, in a specific example, in a case where the first pin is located in the upper half of the quantum chip layout, the first preset number of the first pin may be specifically a minimum number in the pins, for example, a preset starting number, and correspondingly, the second preset number of the second pin is a maximum number of the left half or a maximum number of the right half.

Further, in a specific example, the first pin establishes a mapping relationship with the quantum device or the reading line port with priority number in the first row (the first sub-region 11 in the first row of the area to be processed), and the second pin establishes a mapping relationship with the quantum device or the reading line port with last number in the last row (the second sub-region M2 in the M-th row of the area to be processed).

In this way, the scheme provides a specific automatic numbering mode, and numbers of all pins in the peripheral area can be obtained without additional other operations, so that identification information of all pins is obtained, and support is provided for subsequent automatic wiring of the peripheral wiring layer.

The present disclosure is described in further detail below with reference to specific examples; specifically, the present disclosure proposes an addressing scheme in a superconducting quantum chip layout (hereinafter referred to as a quantum chip layout), which aims at the mapping relationship between output pins and quantum devices (such as qubits or couplers) automated in a chip design stage, reads the mapping relationship between a line port and a pin, further determines a pin corresponding to a measurement and control line, and in a subsequent measurement and control process, can utilize the corresponding relationship among the pin, a measurement line and the quantum devices (such as the qubits or couplers) to read and control the qubits.

It should be noted that, in the superconducting quantum chip, the quantum devices (such as the qubit and the coupler) are connected with the pins through the control lines, and the pins are also connected with the readout lines, however, when the scale of the qubit in the superconducting quantum chip is increased, the connection relationship becomes complex and is not easy to distinguish, and at this time, the pins corresponding to each quantum device (such as the qubit coupler) and the pins corresponding to the readout lines for reading the qubit data can be determined efficiently based on the addressing scheme described in the present disclosure.

The present disclosure is set forth in several sections below; wherein, the first part introduces the relevant background knowledge of the superconducting quantum chip; and a second section for elaborating the numbering scheme of the disclosed scheme and for elaborating core steps implemented by the disclosed scheme in connection with examples.

First part

The present disclosure is described taking a superconducting quantum chip of 3D architecture, including a coupler, as an example.

For ease of understanding, the basic construction of a 3D architecture superconducting quantum chip containing a coupler is briefly described below. Here, the superconducting quantum chip of the 3D architecture including the coupler mainly includes a device layer including a qubit, a coupler, a read line, and the like, and a wiring layer; the wiring layers are further divided into an inner peripheral wiring layer, an outer peripheral wiring layer and a pin wiring layer.

In a practical scenario, the device layer and the wiring layer are two separated layers, and the two layers can be connected by using an indium column in a flip-chip bonding manner.

In an example, the quantum chip layout after flip-chip connection of the device layer and the wiring layer, as shown in fig. 3 (a), specifically includes:

(1) Qubits 31 (e.g., cross-shaped in fig. 3 (a)) arranged in a two-dimensional array; wherein each qubit 31 has a control port 32 (dots on the qubit 31 in fig. 3 (a)) and a read port 33 (triangles in fig. 3 (a)), and wherein each qubit 31 is further provided with a read cavity (not shown);

(2) A Coupler (not shown) disposed between the adjacent two qubits 31 for connecting the adjacent two qubits; each coupler also has a control port 34, in particular, two adjacent qubits 31 are connected through the control port 34 of the coupler. Here, the coupler may be further divided into a lateral coupler and a longitudinal coupler according to an arrangement manner of two adjacent qubits connected to the coupler; specifically, if two adjacent qubits in the same row are connected by a coupler, the coupler (e.g., the coupler corresponding to the control port 34) may be referred to as a lateral coupler; if the coupler connects two adjacent qubits in the same column, the coupler (e.g., the coupler corresponding to control port 35) may be referred to as a vertical coupler;

(3) A read line 36 for connecting with the read port 33 of the qubit 31 through the read cavity of the qubit 31 to read the qubit 31.

It is understood that the qubits, couplers and readout lines are arranged in the core region of the quantum chip layout.

(4) Pins 37 are distributed around the quantum chip layout (i.e., around the periphery of the quantum chip layout) (e.g., pentagons in fig. 3 (a)).

The number of pins is related to the number of control ports and the number of read lines. Here, as shown in fig. 3 (a), since there are two end points of the read line 36, and both end points need to be connected to pins, for convenience of collective terms, in this example, the left and right end points of the read line are collectively referred to as read line ports, and at this time, the number of pins=the number of control ports+the number of read line ports.

Further, as shown in fig. 3 (b), the inner wiring layer may specifically refer to: control lines 38 leading from the control ports (including the control port 32 of the qubit and the control port 34 of the coupler) for connecting the peripheral wiring layers, and read lines 36.

The peripheral wiring layer specifically means: a measurement and control line for connecting with measurement and control lines (such as a control line 38 and a read line 36) of the inner wiring layer; and the measurement and control lines of the peripheral wiring layer are used for being connected with the measurement and control lines in the pin wiring layer.

The pin wiring layer specifically refers to: and the measurement and control line is used for connecting the measurement and control line of the peripheral wiring layer with the pin.

It can be understood that, based on the arrangement structure of the quantum chip layout, in the case of determining the quantum bit scale, for example, determining that the quantum bit array is mxn, where M is the number of rows of the quantum bit array, and N is the number of columns of the quantum bit array, the overall structure of the device layer in the quantum chip layout can be determined, for example, the number of quantum bits in the core area of the quantum chip layout can be determined to be mxn, the number of reading cavities of the quantum bits is mxn, the number of reading lines is M, the number of transverse couplers is mx (N-1), and the number of longitudinal couplers is (M-1) ×n.

Further, the total number of ports in the core area that need to be connected to pins can be obtained. Specifically, the number of control ports of the qubit is mxn, the number of control ports of the lateral coupler is mx (N-1), the number of control ports of the longitudinal coupler is (M-1) xn, and the number of read line ports is 2M, based on which the total number of pins required for the device layer is 3mn+m-N.

For example, continuing to take the quantum chip layout shown in fig. 3 (a) as an example, in the case that the qubit array is specifically 4×4, the number of qubits is 16, and the number of control ports corresponding to the qubits is 16; correspondingly, the number of the transverse couplers is 12, and the number of the corresponding control ports is 12; the number of the longitudinal couplers is 12, and the number of the corresponding control ports is 12; the number of pins required to read the line port is 8; based on this, in the case where the qubit array is specifically 4×4, the number of pins required for the device layer is specifically 48.

Second part

The part firstly describes an automatic numbering mode of the scheme, and based on the numbering mode, the control port of the quantum bit distributed in the core area of the quantum chip layout, the control port of the coupler, the reading line port and the pins distributed in the peripheral area of the quantum chip layout are automatically numbered; secondly, based on the number, determining the mapping relation between the control port and the pin, and determining the mapping relation between the read line port and the pin, for example, pairing the control port and the pin with the same number, pairing the read line port and the pin with the same number, and further using the pairing result (i.e. the mapping relation) as an output result of the addressing scheme in the scheme of the disclosure.

It should be noted that, in the present disclosure, a preset value is taken as a preset initial number, and numbers are numbered according to a number increment manner from the number 1, for example, numbers are numbered according to preset values (for example, 0 is recorded or min is recorded), 1,2,3 …; it will be appreciated that the preset starting number may be based on actual requirements, and the present disclosure is not limited thereto.

Further, in order to implement automatic numbering, the present disclosure introduces a concept of line numbers, and determines line numbers according to an arrangement manner of the qubit array, for example, as shown in fig. 3 (c), for an mxn qubit array, line numbers increase from top to bottom, and are respectively a first line, a second line, …, an mth line (i.e. the mth line to be processed area described above), …, and an mth line; further, on the basis of the line number, the concept of sub-areas is introduced, specifically, the area division is continued for each line, for example, for any line from the first line to the M-1 line, each line is divided into three sub-areas, namely, a first sub-area to a third sub-area; here, the sub-area of the current line may be recorded using a line number+area number, for example, for the first line, the first sub-area may be recorded as the first sub-area 11, the second sub-area may be recorded as the second sub-area 12, and the third sub-area may be recorded as the third sub-area 13; in the M-th (positive integer of 1 or more and M-1 or less), the first subregion of the M-th row may be referred to as a first subregion M1, the second subregion of the M-th row may be referred to as a second subregion M2, and the third subregion of the M-th row may be referred to as a third subregion M3. Further, for the last row, i.e. the M-th row, only the first sub-region (which may be denoted as first sub-region M1) and the second sub-region (which may be denoted as second sub-region M2) are included.

Based on this, for control ports and read line ports in the core area, the numbering follows the following rules:

(1) The larger the line number, the larger the number; such as the largest number in the first row, is smaller than the smallest number of control ports in the second row. For another example, the maximum number of the first sub-region in the first row is smaller than the minimum number of the second sub-region in the first row.

(2) In the same subarea, the number of the control port of the upward wiring is larger than that of the control port of the downward wiring. Specifically, in the same subarea, if the routing of the control port in the middle area is upward and the routing of the other control ports is downward, the number of the control port in the middle area is smaller than the number of the other control ports. In other words, in the sequential numbering process, if the trace of the control port in the middle area is led out upwards in the same subarea, the numbering is performed preferentially.

It should be noted that, in the same sub-area, the wires of the control ports in the middle area may be upward or downward, and the wires of the other control ports except the middle area are downward. In an actual scene, the wires of other control ports except the middle area can be upwards, and the numbering mode is unchanged at the moment, namely the numbering mode of the scheme does not pay attention to the extraction directions of the wires of other control ports except the middle area.

(3) Within the same sub-zone, the control ports running down are numbered sequentially from the outer edge to the center, e.g., the numbers increment from the outer edge to the center.

As shown in fig. 4, the core steps of the implementation of the disclosed solution:

step S401: and obtaining device distribution information, reading line distribution information and pin distribution information of the quantum chip layout according to the input quantum chip layout.

Here, the device distribution information is used to represent the arrangement information of the M row by N column quantum bit arrays arranged in the core region of the quantum chip layout, and the distribution information of the M row by x (N-1) column transverse coupler arrays and the (M-1) row by N column longitudinal coupler arrays arranged in the core region; the read line distribution information is used for representing the distribution information of M rows of read lines arranged in the core area; the pin distribution information is used for representing the distribution information of a plurality of pins distributed in the peripheral area of the quantum chip layout.

In practical application, in order to facilitate numbering, the quantum chip layout can be further divided into a left half part and a right half part, at this time, the number of pins to be numbered in the left half part can be respectively recorded as LeftNum, and the number of pins to be numbered in the right half part can be recorded as RightNum.

Or other dividing modes are also possible, for example, the number of pins in the upper, lower, left and right directions is respectively recorded as: upNum, downNum, leftNum, rightNum; the present disclosure is not limited in this regard.

Step S402: numbering the pins to obtain the identification information of each pin.

Specifically, a first pin is selected from the middle of the top, a second pin is selected from the middle of the bottom, and the connection line of the first pin and the second pin can divide the quantum chip layout into a left half part and a right half part.

If the number of the pins at the top is odd, the pins at the middle of the top are the first pins, and similarly, if the number of the pins at the bottom is odd, the pins at the middle of the bottom are the second pins; further, if the number of the top pins is even, any one of the two pins at the middle of the top can be selected as the first pin, and similarly, if the number of the bottom pins is even, any one of the two pins at the middle of the bottom can be selected as the second pin.

Further, after determining the first pins and the second pins, all the pins may be divided into two parts, i.e. a pin located in the left half and a pin located in the right half, where the left half may be numbered sequentially in a counterclockwise direction and the right half may be numbered sequentially in a clockwise manner.

For example, as shown in fig. 5 (a), the number of the top pins is even, at this time, one of the two pins at the middle of the top is selected as the first pin, and the first pin is numbered as min; the number of bottom pins is also even, at this time, one of the two pins at the middle of the bottom is selected as the second pin, and the second pin is numbered as max. At this time, the connection line of the first pin and the second pin can divide the quantum chip layout into a left half part and a right half part; further, for the left half, starting from L1, sequential numbering is performed, e.g., continuing with L1, and numbering is performed in an ascending order, e.g., L2, L3, until the previous pin of the second pin. Similarly, for the right half, starting from R1, sequential numbering is performed, e.g., continuing with R1, and numbering is performed in increasing order, with increasing order of R2, R3, until the previous pin of the second pin. Thus, the numbering of the pins is completed.

Here, in this example, the pin number may be directly used as the identification information of the pin.

In the example, pins arranged in the peripheral area of the quantum chip layout are double rows of pins, and the arrangement of bottom pins and top pins in the quantum chip layout is symmetrical; moreover, the arrangement of the left pin and the right pin in the quantum chip layout is symmetrical, so that a foundation is further laid for realizing automatic numbering.

Step S403: according to a preset numbering mode, the control ports (including the control ports of the quantum bits and the control ports of the coupler) and the reading line ports are numbered, and identification information of each control port are obtained.

Specifically, as shown in fig. 3 (c), each row is numbered from top to bottom; specifically, this example is explained with the next row example in which the mth row read line is located at the mth row qubit; at this time, in the case where M is any one of values 1 to M-1, the M-th row of the area to be processed (may also be abbreviated as M-th row) includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of qubits, and a second sub-region m2 corresponding to one row of read lines. Thus, each row is numbered by row number in this example.

Here, step S403 specifically includes:

Step S4031: when m has a value of 1, the first to third sub-areas 11 to 13 in the first row are sequentially numbered.

As shown in fig. 5 (b), in the first sub-region 11, the control line led out by the quantum device located in the middle region is led out upward and extends toward the left outer edge, at this time, the quantum devices in the middle region of the first sub-region 11 are preferentially numbered, for example, with the number of min, and then continuing the minimum value, and the quantum devices in the left region of the first sub-region 11 are sequentially numbered, for example, continuing the min, in the direction from the outer edge to the center, and sequentially numbered with the numbers of L1, L2, and L3, so as to complete the numbering of the quantum devices in the left region of the first sub-region 11. Meanwhile, the quantum devices in the right side region of the first sub-region 11 are sequentially numbered from the outer edge to the center, for example, from the preset starting number R1, and the directions from the outer edge to the center are sequentially numbered as R1, R2, and R3.

Further, as shown in fig. 5 (c), the read line port number on the left side of the read line of the second sub-region 12 is L4, following the maximum number (i.e., L3) of the left side region of the first sub-region 11. Similarly, the largest number of the right-hand region (i.e. R3) continuing the first sub-region 11,

The read line port to the right of the read line of the second sub-region 12 is numbered R4.

Further, as shown in fig. 5 (d), the quantum devices in the left region of the third sub-region 13 are sequentially numbered L5 and L6 from the outer edge to the center, following the maximum number (i.e., L4) of the left region of the second sub-region 12; similarly, the quantum devices in the right region of the third sub-region 13 are sequentially numbered R5 and R6 in the direction from the outer edge to the center, with the largest number (i.e., R4) in the right region of the second sub-region 12.

Step S4032: and in the case that the value of m is [2, M ], sequentially numbering the first subarea m1 to the third subarea m3 in the m-th row.

For example, in the case of a value of 2, the first to third sub-areas 21 to 23 in the second row are sequentially numbered. As shown in fig. 5 (e), in the first sub-region 21, the control line led out by the quantum device located in the middle region is led out upward and extends toward the outer edge on the right side, at this time, the quantum device in the middle region of the first sub-region 21 is preferentially numbered, that is, the largest number (i.e., R6) of the right side region in the first row is continued, the quantum device in the middle region of the first sub-region 21 is preferentially numbered, and is numbered as R7, and further continued with R7,

The quantum devices in the right region of the first sub-region 21 are numbered R8, R9, R10 in order from the outer edge to the center, to complete the numbering of the quantum devices in the right region of the first sub-region 21. At the same time, continuing the maximum number of the left area in the first row (i.e., L6),

The quantum devices in the left region of the first sub-region 21 are numbered L7, L8, and L9 in this order from the outer edge to the center.

The read line ports of the second sub-area 22 are numbered in the manner of the second sub-area 12 and the control ports of the quantum devices of the third sub-area 23 are numbered in the manner of the third sub-area 13, thus completing the numbering of the second row.

Step S4033: judging whether all rows are numbered completely; if not, the process returns to step S4032. Otherwise, step S404 is performed.

In this example, the number may be directly used as the identification information.

Step S404: based on the identification information, a mapping relation is established between the control port and the pin, and between the reading line port and the pin, and the mapping relation is output for subsequent calibration and measurement and control.

For example, pairing control ports with the same numbers with pins, such as a pin with the number of min-a control port with the number of min, a pin with the number of L1-a control port with the number of L1, a pin with the number of R1-a control port with the number of R1, and the like, and then outputting paired information of the paired pins and control ports according to output requirements for subsequent chip calibration and measurement and control.

As shown in fig. 5 (f), after the mapping relation is obtained, the control line corresponding to the control port of the qubit is extended to the pin having the mapping relation with the qubit, the control line corresponding to the control port of the coupler is extended to the pin having the mapping relation with the coupler, and the read line corresponding to the read line port is extended to the pin having the mapping relation with the read line port.

In fig. 6, in the first sub-region 11, the control line led out by the quantum device located in the middle region is led out downwards and extends towards the left outer edge, and at this time, the quantum devices in the middle region of the first sub-region 11 need not be numbered preferentially, and the quantum devices in the left region of the first sub-region 11 may be numbered sequentially from the outer edge to the center, for example, the quantum devices in the left region of the first sub-region 11 are numbered sequentially with min as a preset initial number, and are numbered sequentially with min, L1, L2, and L3, so as to complete the numbering of the quantum devices in the left region of the first sub-region 11. Meanwhile, the quantum devices in the right side region of the first sub-region 11 are sequentially numbered from the outer edge to the center, for example, from the preset starting number R1, and the directions from the outer edge to the center are sequentially numbered as R1, R2, and R3.

Further, the read line port number on the left side of the read line of the second sub-region 12 is L4, following the maximum number (i.e., L3) of the left side region of the first sub-region 11. Similarly, the read line port number on the right side of the read line of the second sub-region 12 is R4, following the maximum number (i.e., R3) of the right side region of the first sub-region 11. Further, the quantum devices in the left side region of the third sub-region 13 are sequentially numbered as L5 and L6 from the outer edge to the center, continuing the maximum number (i.e., L4) of the left side region of the second sub-region 12; similarly, the quantum devices in the right region of the third sub-region 13 are sequentially numbered R5 and R6 in the direction from the outer edge to the center, with the largest number (i.e., R4) in the right region of the second sub-region 12. Thus, until the process completes the last line.

It should be noted that, the preset starting number of the scheme of the present disclosure may be other characters, which is not limited in this aspect of the present disclosure.

By the adoption of the scheme, the quantum device corresponding to each pin can be automatically determined, the function corresponding to each pin is further determined conveniently, the method has important value for the design automation of the quantum chip, and the research and development efficiency of the quantum chip can be effectively improved. Specifically, the solution of the present disclosure also has the following advantages:

First, the expansibility is strong; the scheme logic disclosed by the disclosure is applicable to any wiring scheme, is not limited to the 3D architecture exemplified herein, and can be extended to 2D quantum chip layouts.

Second, high efficiency; the scheme can rapidly give the mapping relation after the distribution information is obtained, and has short time consumption and high accuracy.

Thirdly, automation; the scheme can be automatically realized without other additional operations, and practical value is provided for the design automation of the subsequent quantum chip.

The disclosed scheme also provides a wiring device of the quantum chip layout, as shown in fig. 7, comprising:

The processing unit 701 is configured to obtain identification information of each quantum bit in the quantum bit array and identification information of each coupler in the coupler array based on device distribution information of the quantum chip layout; the device distribution information is used for representing the distribution information of the M rows and N columns of quantum bit arrays arranged in the core area of the quantum chip layout and the distribution information of the coupler arrays arranged in the core area; the coupler in the coupler array is used for connecting two adjacent qubits in the qubit array; obtaining identification information of a read line port based on the read line distribution information of the quantum chip layout; the read line distribution information is used for representing the distribution information of M rows of read lines arranged in the core area; the M-th row reading line of the M rows of reading lines is used for reading information of each quantum bit in the M-th row quantum bits; the read line port is positioned at one end of the read line; obtaining identification information of each pin based on the pin distribution information of the quantum chip layout; the pin distribution information is used for representing the distribution information of a plurality of pins distributed in the peripheral area of the quantum chip layout; the total number of the plurality of pins is related to the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports; based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports;

An output unit 702 for outputting at least one of: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports.

In a specific example of the present disclosure, the processing unit 701 is further configured to extend a control line corresponding to a control port of a qubit to a pin having a mapping relationship with the qubit; extending a control line corresponding to a control port of a coupler to a pin with a mapping relation with the coupler; extending a reading line corresponding to a reading line port to a pin with a mapping relation with the reading line port; obtaining a quantum chip layout after wiring;

The output unit 702 is further configured to output the routed quantum chip layout.

In a specific example of the disclosed arrangement, the coupler array includes a transverse coupler array of M rows by (N-1) columns and a longitudinal coupler array of (M-1) rows by N columns;

The transverse couplers in the transverse coupler array are used for connecting two adjacent quantum bits in the same row;

the longitudinal couplers in the longitudinal coupler array are used for connecting two adjacent quantum bits in the same column.

In a specific example of the scheme of the present disclosure, the mth row of read lines is located at the upper row or the lower row of the mth row of qubits.

In a specific example of the scheme of the disclosure, in the case where M is any one of 1 to M-1, the mth row read line is located between the mth row qubit and the mth row longitudinal coupler; under the condition that M takes the value of M, the reading line of the M row is positioned on the next row of the quantum bits of the M row;

Or alternatively

In the case where M is any one of 2 to M, the mth row read line is located between the mth row qubit and the mth-1 row longitudinal coupler; in the case where m takes a value of 1, the first row read line is located in the upper row of the first row qubits.

In a specific example of the solution of the present disclosure, the processing unit 701 is specifically configured to:

Dividing the core region based on the distribution information of M rows of quantum bits in the device distribution information and the distribution information of M rows of reading lines in the reading line arrangement information to obtain M rows of regions to be processed;

Sequentially numbering the quantum bits, the couplers and the reading line ports in each row of the M rows of the to-be-processed areas to obtain identification information of the quantum bits, the identification information of the couplers and the identification information of the reading line ports in each row of the to-be-processed areas.

The quantum devices and the control line ports in the left area in the m-th row of the area to be processed are connected with the maximum number of the left area of the m-1-th row of the area to be processed, and the serial numbers are carried out;

and the quantum devices and the control line ports in the m-th row of the to-be-processed area and positioned in the right side area are connected with the maximum number of the right side area of the m-1-th row of the to-be-processed area, and the serial numbers are carried out.

Under the condition that a control line led out by a quantum device in the middle area is led out upwards and extends towards the outer edge of the left side in the m-th row to be processed area, continuing the maximum number of the left side area of the m-1-th row to be processed area, numbering the quantum devices in the middle area of the m-th row to be processed area, continuing the number of the quantum devices in the middle area of the m-th row to be processed area according to a preset sequence, and sequentially numbering other quantum devices and control line ports of the left side area of the m-th row to be processed area;

Or alternatively

And continuing the maximum number of the left area of the m-1 row of to-be-processed area under the condition that the control line led out by the quantum device in the middle area is led out downwards and extends towards the outer edge of the left side, and sequentially numbering the quantum device and the control line port of the left area in the m row of to-be-processed area according to a preset sequence.

In a specific example of the solution of the present disclosure, in a case where M is any one of values 1 to M-1, the M-th row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

The processing unit 701 is specifically configured to:

under the condition that a control line led out by a quantum device in the middle area of the first subarea m1 in the m-th row to-be-processed area is led out upwards and extends towards the left outer edge, continuing the maximum number of the left area of the m-1-th row to-be-processed area, and numbering the quantum device in the middle area of the first subarea m 1; the number of the quantum devices in the middle area of the first sub area m1 is continued, and other quantum devices in the left area of the first sub area m1 are numbered sequentially according to a preset sequence;

and under the condition that a third sub-region m3 exists in the m-th row of to-be-processed region, continuing the serial numbers of the control line ports on the left side of the second sub-region m2, and sequentially numbering the quantum devices in the left side region of the third sub-region m3 according to a preset sequence.

In a specific example of the solution of the present disclosure, in a case where M is any one of values 1 to M-1, the M-th row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m1 corresponding to one row of reading lines;

The processing unit 701 is specifically configured to:

Under the condition that a control line led out by the quantum devices in the middle area of the first subarea m1 is led out downwards and extends towards the left outer edge in the m-th row of to-be-processed area, continuing the maximum number of the left area of the m-1-th row of to-be-processed area, and sequentially numbering the quantum devices in the left area of the first subarea m1 according to a preset sequence;

In a specific example of the solution of the present disclosure, in a case where M is any one of values 1 to M-1, the M-th row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

The processing unit 701 is specifically configured to:

In the m-th row of to-be-processed area, under the condition that a control line led out by a quantum device in the middle area of the second sub-area m2 is led out upwards and extends towards the outer edge of the left side, continuing the serial number of a control line port of the left side of the first sub-area m1, and numbering the quantum device in the middle area of the second sub-area m 2; the number of the quantum devices in the middle area of the second sub-area m2 is continued, and other quantum devices in the left area of the second sub-area m2 are numbered sequentially according to a preset sequence;

And under the condition that a third sub-region m3 exists in the m-th row of to-be-processed region, continuing the maximum number of the left side region of the second sub-region m2, and sequentially numbering the quantum devices of the left side region of the third sub-region m3 according to a preset sequence.

The processing unit 701 is specifically configured to:

Under the condition that a control line led out by a quantum device in the middle area of the second subarea m2 in the m-th row to-be-processed area is led out downwards and extends towards the outer edge of the left side, continuing the serial numbers of the control line ports of the left side of the first subarea m1, and sequentially numbering the quantum devices in the left side area of the second subarea m2 according to a preset sequence;

Under the condition that a control line led out by a quantum device in the middle area is led out upwards and extends towards the outer edge of the right side in the m-th row to be processed area, continuing the maximum number of the right side area of the m-1-th row to be processed area, numbering the quantum devices in the middle area of the m-th row to be processed area, continuing the number of the quantum devices in the middle area of the m-th row to be processed area according to a preset sequence, and sequentially numbering other quantum devices and control line ports of the right side area of the m-th row to be processed area;

Or alternatively

And continuing the maximum number of the right side area of the m-1 row of the area to be processed under the condition that the control line led out by the quantum device in the middle area is led out downwards and extends towards the outer edge of the right side in the m row of the area to be processed, and sequentially numbering the quantum device and the control line port of the right side area in the m row of the area to be processed according to a preset sequence.

The processing unit 701 is specifically configured to:

under the condition that a control line led out by a quantum device in the middle area of the first subarea m1 in the m-th row to-be-processed area is led out upwards and extends towards the outer edge of the right side, continuing the maximum number of the right side area of the m-1-th row to-be-processed area, and numbering the quantum device in the middle area of the first subarea m 1; the number of the quantum devices in the middle area of the first sub area m1 is continued, and other quantum devices in the right area of the first sub area m1 are numbered sequentially according to a preset sequence;

and under the condition that a third sub-region m3 exists in the m-th row of to-be-processed region, continuing the serial numbers of the control line ports on the right side of the second sub-region m2, and sequentially numbering the quantum devices in the right side region of the third sub-region m3 according to a preset sequence.

The processing unit 701 is specifically configured to:

under the condition that a control line led out by the quantum devices in the middle area of the first subarea m1 is led out downwards and extends towards the outer edge of the right side in the m-th row of to-be-processed area, continuing the maximum number of the right side area of the m-1-th row of to-be-processed area, and sequentially numbering the quantum devices in the right side area of the first subarea m1 according to a preset sequence;

The processing unit 701 is specifically configured to:

in the m-th row of to-be-processed area, under the condition that a control line led out by a quantum device in the middle area of the second sub-area m2 is led out upwards and extends towards the outer edge of the right side, continuing the serial number of a control line port on the right side of the first sub-area m1, and numbering the quantum device in the middle area of the second sub-area m 2; the number of the quantum devices in the middle area of the second sub-area m2 is continued, and other quantum devices in the right area of the second sub-area m2 are numbered sequentially according to a preset sequence;

and under the condition that a third sub-region m3 exists in the m-th row of to-be-processed region, continuing the maximum number of the right side region of the second sub-region m2, and sequentially numbering the quantum devices of the right side region of the third sub-region m3 according to a preset sequence.

The processing unit 701 is specifically configured to:

under the condition that a control line led out by a quantum device in the middle area of the second subarea m2 in the m-th row to-be-processed area is led out downwards and extends towards the outer edge of the right side, continuing the serial number of the control line port on the right side of the first subarea m1, and sequentially numbering the quantum devices in the right side area of the second subarea m2 according to a preset sequence;

In a specific example of the solution of the present disclosure, the plurality of pins are arranged in a single row around the peripheral area; or the pins are arranged in a double-row and staggered manner around the peripheral area.

In a specific example of the present disclosure, the total number of the plurality of pins is equal to the sum of the following numbers: the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports.

Selecting a first pin and a second pin from a plurality of pins based on pin distribution information of the quantum chip layout, wherein a connecting line of the first pin and the second pin can divide the quantum chip layout into a left half part and a right half part;

Sequentially numbering pins positioned at the left half part of the quantum chip layout from the first pin according to a first direction until a pin before the second pin;

Sequentially numbering pins positioned at the right half part of the quantum chip layout from the first pin according to a second direction opposite to the first direction until a pin before the second pin;

Based on the first preset number of the first pin, the second preset number of the second pin and the numbers of other pins, the identification information of each pin is obtained.

Descriptions of specific functions and examples of each unit of the apparatus in the embodiments of the present disclosure may refer to related descriptions of corresponding steps in the foregoing method embodiments, which are not repeated herein.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 8 illustrates a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile apparatuses, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing apparatuses. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 801 performs the respective methods and processes described above, for example, a wiring method of a quantum chip layout. For example, in some embodiments, the routing method of the quantum chip layout may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the memory unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the routing method of the quantum chip layout described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the routing method of the quantum chip layout in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions, improvements, etc. that are within the principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1.A wiring method of a quantum chip layout comprises the following steps:

Based on the identification information of the qubit, the identification information of the coupler, the identification information of the read line port and the identification information of the pin, at least one of the following is obtained: mapping relation between pins and quantum bits, mapping relation between pins and couplers, and mapping relation between pins and reading line ports;

The method for obtaining the identification information of each quantum bit in the quantum bit array and the identification information of each coupler in the coupler array based on the device distribution information of the quantum chip layout and obtaining the identification information of the read line port based on the read line distribution information of the quantum chip layout comprises the following steps:

Dividing the core region based on the distribution information of M rows of quantum bits in the device distribution information and the distribution information of M rows of reading lines in the reading line distribution information to obtain M rows of regions to be processed;

sequentially numbering the quantum bits, the couplers and the reading line ports in each row of the M rows of the to-be-processed areas to obtain identification information of the quantum bits, the identification information of the couplers and the identification information of the reading line ports in each row of the to-be-processed areas;

The sequentially numbering the qubits, the couplers and the read line ports in each of the M rows of to-be-processed regions includes:

2. The method of claim 1, further comprising at least one of:

3. The method of claim 1 or 2, wherein the coupler array comprises a transverse coupler array of M rows x (N-1) columns and a longitudinal coupler array of (M-1) rows x N columns;

4. A method according to claim 3, wherein the mth row of read lines is located in the upper or lower row of mth row of qubits.

5. The method of claim 4, wherein, in the case where M is any one of 1 to M-1, the mth row read line is located between the mth row qubit and an mth row longitudinal coupler; under the condition that M takes the value of M, the reading line of the M row is positioned on the next row of the quantum bits of the M row;

Or alternatively

6. The method of claim 1, wherein the quantum devices and control line ports in the left region of the m-th row of regions to be processed, are numbered sequentially with the largest number of left regions of the m-1 th row of regions to be processed, comprising:

Or alternatively

7. The method according to claim 6, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

under the condition that a control line led out by a quantum device in the middle area is led out upwards and extends towards the left outer edge in the m-th row of the to-be-processed area, continuing the maximum number of the left area of the m-1-th row of the to-be-processed area, numbering the quantum devices in the middle area of the m-th row of the to-be-processed area, continuing the numbers of the quantum devices in the middle area of the m-th row of the to-be-processed area according to a preset sequence, sequentially numbering other quantum devices and control line ports of the left area in the m-th row of the to-be-processed area, wherein the method comprises the following steps:

8. The method according to claim 6, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m1 corresponding to one row of reading lines;

Under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed is led out downwards and extends towards the outer edge of the left side, continuing the maximum number of the left area of the m-1-th row of the area to be processed, and sequentially numbering the quantum device and the control line port of the left area in the m-th row of the area to be processed according to a preset sequence, wherein the method comprises the following steps:

9. The method according to claim 6, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

10. The method according to claim 6, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

11. The method of claim 1, wherein the quantum devices and control line ports in the m-th row of regions to be processed, located in the right region, are numbered consecutively to the maximum number of the m-1 st row of regions to be processed, comprising:

Or alternatively

12. The method according to claim 11, wherein in case M is any one of values 1 to M-1, the mth row of areas to be processed comprises, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

Under the condition that a control line led out by a quantum device in the middle area is led out upwards and extends towards the outer edge of the right side in the m-th row of to-be-processed area, continuing the maximum number of the right side area of the m-1-th row of to-be-processed area, numbering the quantum devices in the middle area of the m-th row of to-be-processed area, continuing the number of the quantum devices in the middle area of the m-th row of to-be-processed area according to a preset sequence, and sequentially numbering other quantum devices and control line ports of the right side area in the m-th row of to-be-processed area, wherein the method comprises the following steps:

13. The method according to claim 11, wherein in case M is any one of values 1 to M-1, the mth row of areas to be processed comprises, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

Under the condition that a control line led out by the quantum device in the middle area in the m-th row of the area to be processed is led out downwards and extends towards the outer edge of the right side, continuing the maximum number of the area on the right side of the m-1-th row of the area to be processed, and sequentially numbering the quantum device and the control line port of the area on the right side in the m-th row of the area to be processed according to a preset sequence, wherein the method comprises the following steps:

14. The method according to claim 11, wherein in case M is any one of values 1 to M-1, the mth row of areas to be processed comprises, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

15. The method according to claim 11, wherein in case M is any one of values 1 to M-1, the mth row of areas to be processed comprises, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

16. The method of claim 1 or 2, wherein the plurality of pins are arranged in a single row around the peripheral region; or the pins are arranged in a double-row and staggered manner around the peripheral area.

17. The method of claim 16, the total number of the plurality of pins being equal to a sum of: the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports.

18. The method of claim 16, wherein the obtaining the identification information of each pin based on the pin distribution information of the quantum chip layout includes:

19. A wiring device of a quantum chip layout, comprising:

wherein, the processing unit is specifically configured to:

Wherein, the processing unit is further specifically configured to:

The quantum devices and the control line ports in the m-th row of the to-be-processed area and positioned in the right side area are connected with the maximum number of the right side area of the m-1-th row of the to-be-processed area, and the serial numbers are carried out;

20. The apparatus of claim 19, wherein,

The processing unit is further used for extending a control line corresponding to the control port of the quantum bit to a pin with a mapping relation with the quantum bit; extending a control line corresponding to a control port of a coupler to a pin with a mapping relation with the coupler; extending a reading line corresponding to a reading line port to a pin with a mapping relation with the reading line port; obtaining a quantum chip layout after wiring;

The output unit is also used for outputting the layout of the wired quantum chip.

21. The apparatus of claim 19 or 20, wherein the coupler array comprises a transverse coupler array of M rows x (N-1) columns and a longitudinal coupler array of (M-1) rows x N columns;

22. The apparatus of claim 21, wherein the mth row of read lines is located in a row above or a row below an mth row of qubits.

23. The apparatus of claim 22, wherein, in the case where M is any one of 1 to M-1, the mth row read line is located between the mth row qubit and an mth row longitudinal coupler; under the condition that M takes the value of M, the reading line of the M row is positioned on the next row of the quantum bits of the M row;

Or alternatively

24. The apparatus of claim 19, wherein the processing unit is specifically configured to:

Or alternatively

25. The apparatus of claim 24, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

wherein, the processing unit is specifically configured to:

26. The apparatus of claim 24, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m1 corresponding to one row of reading lines;

wherein, the processing unit is specifically configured to:

27. The apparatus of claim 24, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

wherein, the processing unit is specifically configured to:

28. The apparatus of claim 24, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

wherein, the processing unit is specifically configured to:

29. The apparatus of claim 19, wherein the processing unit is specifically configured to:

Or alternatively

30. The apparatus of claim 29, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

wherein, the processing unit is specifically configured to:

31. The apparatus of claim 29, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, a second sub-region m2 corresponding to one row of read lines, and a third sub-region m3 corresponding to one row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to one row of quantum bits, and a second sub-region m2 corresponding to one row of read lines;

wherein, the processing unit is specifically configured to:

32. The apparatus of claim 29, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

wherein, the processing unit is specifically configured to:

33. The apparatus of claim 29, wherein, in the case where M is any one of values 1 to M-1, the mth row of areas to be processed includes, in order from top to bottom: a first sub-region m1 corresponding to a row of read lines, a second sub-region m2 corresponding to a row of qubits, and a third sub-region m3 corresponding to a row of longitudinal couplers; under the condition that M is M, the M-th row of areas to be treated comprises the following steps in sequence from top to bottom: a first sub-region m1 corresponding to a row of read lines, and a second sub-region m2 corresponding to a row of qubits;

wherein, the processing unit is specifically configured to:

34. The apparatus of claim 19 or 20, wherein the plurality of pins are arranged in a single row around the peripheral region; or the pins are arranged in a double-row and staggered manner around the peripheral area.

35. The apparatus of claim 34, a total number of the plurality of pins equal to a sum of: the number of qubits in the qubit array, the number of couplers in the coupler array, and the number of read line ports.

36. The apparatus of claim 34, wherein the processing unit is specifically configured to:

37. An electronic device, comprising:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-18.

38. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-18.