CN116155436A

CN116155436A - System, method, electronic device and storage medium capable of performing time code conversion

Info

Publication number: CN116155436A
Application number: CN202310102521.7A
Authority: CN
Inventors: 邓舒予; 黎小军; 何培东; 严平; 涂娅欣; 方建全; 袁世炯; 沈文琪; 潘可佳; 李显忠; 姚宬丞; 张君胜; 刘丽娜
Original assignee: Marketing Service Center Of State Grid Sichuan Electric Power Co
Current assignee: Marketing Service Center Of State Grid Sichuan Electric Power Co
Priority date: 2023-01-31
Filing date: 2023-01-31
Publication date: 2023-05-23

Abstract

The invention relates to the technical field of time synchronization, and discloses a system, a method, electronic equipment and a storage medium capable of performing time code conversion, wherein the system, the method, the electronic equipment and the storage medium are used for extracting second on-time edge information of IRIG-B codes from position information of P code elements by acquiring the position information of the P code elements from serial code element information; according to the serial code element information and the second time edge information, the encoding information of IRIG-B codes is analyzed; generating week information according to the encoded information; performing time correction on the coded information; according to the time-corrected coding information and week information, performing time code coding according to a DCF77 coding format, outputting a DCF77 code, and converting an IRIG-B code into the DCF77 code, the problem that in the current power system using an IRIG-B code time synchronization mode, time synchronization equipment with a DCF77 code output function is required to be additionally arranged to finish time service of equipment based on the DCF77 code can be solved.

Description

System, method, electronic device and storage medium capable of performing time code conversion

Technical Field

The present invention relates to the field of time synchronization, and in particular, to a system, a method, an electronic device, and a storage medium capable of performing time-to-code conversion.

Background

IRIG serial time code has six formats in total, namely A, B, D, E, G, H, wherein IRIG-B format time code (hereinafter abbreviated as B code) is most widely used. The time frame rate of the B code is 1 frame/s, and the B code comprises 100 bits of information which respectively represent BCD time information and control function information, and can extract 1Hz and 100Hz pulse signals. In practical applications, the time signal transmission medium between the connection time synchronization device and the secondary device being time-supplied is usually twisted pair or optical fiber, and the signal type is usually IRIG-B (DC) time-to-time code (IRIG-B (DC) code).

The DCF77 time code (DCF 77 code) is a time code of a german wireless long wave time signal, and the time format code contains complete absolute time information of year, month, day, time, minute, week, etc., and is widely used in main european countries such as france and germany. European importation equipment used in the power industry in China often adopts DCF77 code for time synchronization.

IRIG-B (DC) code is a common time synchronization mode of an electric power system, but relevant standards of the electric power system in China do not prescribe that a time synchronization device is required to have a DCF77 code output function, and in implementation, the time synchronization device with the DCF77 code output function is often required to be independently added, so that the installation is inconvenient and the cost is high.

In view of this, the present application is specifically proposed.

Disclosure of Invention

In order to solve the defects in the prior art, the invention provides a system, a method, electronic equipment and a storage medium capable of performing time-to-code conversion, and solves the problem that in the existing power system using IRIG-B (DC) code time-to-time mode, time synchronization equipment with a DCF77 code output function is required to be additionally arranged to complete time service on equipment based on the DCF77 code.

The invention is realized by the following technical scheme:

in one aspect, a system capable of performing time-to-code conversion is provided, including the following functional modules:

the constant-temperature crystal oscillator is used for generating a reference clock signal with stable frequency;

the frequency multiplication module is used for carrying out frequency multiplication processing on the reference clock signal, and driving the first counter to work through the reference clock signal after the frequency multiplication processing;

the first counter is used for counting the edges of the arriving input signals and driving the second counter to work through overflow signals; the edges of the input signal include rising and falling edges;

a second counter for counting seconds of the incoming signal;

a symbol identification module for executing the following operations: acquiring a time stamp of each code element according to the count value of the first counter and the count value of the second counter; acquiring a corresponding code element period and a code element high level width according to the time stamp of each code element; according to the symbol period and the symbol high level width of each symbol, combining the symbol characteristics of the standard signal and the IRIG-B code, and performing type identification on each symbol; generating serial code element information according to time sequence of all code elements conforming to IRIG-B code element type;

the second on-time edge extraction module is used for acquiring the position information of the P code element from the serial code element information and extracting the second on-time edge information of the IRIG-B code from the position information of the P code element;

the B code information analysis module is used for analyzing the code information of the IRIG-B code according to the serial code element information and the second punctual edge information;

the week information generation module is used for generating week information according to the coding information;

the time information correction module is used for performing time correction on the coded information;

the DCF77 code coding module is used for carrying out time code coding according to a DCF77 coding format according to the time-corrected coding information and week information and outputting a DCF77 code;

the 1PPS generation module is used for generating a 1PPS signal after delaying for 1 second according to the second on-time edge information; pulse width of 1PPS signal = symbol width of IRIG-B code;

the 1PPM generation module is used for generating a 1PPM signal according to the rising edge of the 1PPS signal and the time-corrected coding information; pulse width of 1PPM signal = pulse width of the 1PPS signal;

the DCF77 code sending module is used for sending the DCF77 code to the interface driving circuit according to the 1PPS signal and the 1PPM signal;

and the interface driving circuit is used for performing physical layer interface signal conversion on the DCF77 code and outputting the converted physical layer interface signal.

The code element identification module comprises an initialization unit, a first register group, a second register, a third register group, a fourth register, a logic judgment unit, a code element characteristic extraction unit, a code element type judgment unit and a control unit; the control unit is used for executing the following operations:

the control initialization unit initializes the value of the first register group to 0 and the value of the second register group to 1; the control logic judging module matches the IRIG-B code input signal edge with the current count value of the second register; identifying a matching result; if the current IRIG-B code input signal edge is a rising edge and the current count value of the second register is an odd number, or the current IRIG-B code input signal edge is a falling edge and the current count value of the second register is an even number, assembling the count value of the first counter and the count value of the second counter into corresponding time stamps, storing the assembled time stamps into an ith register of the first register group, wherein i=the current count value of the second register, and adding 1 to the count value of the second register; if the current IRIG-B code input signal edge is a rising edge and the current count value of the second register is even, or the current IRIG-B code input signal edge is a falling edge and the current count value of the second register is odd, setting the count value of the second register to be 1, and restarting the time sequence; monitoring the count value of the second register in real time; when the count value of the second register is even and is more than 3, the control code element characteristic extraction unit calculates each code element to carry out code element period and code element high level width; the control code element type discriminating unit discriminates the type of each code element according to the calculation result; if the error between the symbol period calculation result and the period of the standard signal is less than or equal to 100 mu s and the error between the symbol high level width calculation result and the width of the standard signal is less than or equal to 100 mu s, storing the symbol into a j-th register of the third register group, wherein j=i/2; otherwise, the count value of the second register is set to 1, and the time sequence is restarted. The symbols of the first to j-th registers of the third register group are sequentially generated into serial symbol information.

The second on-time edge extraction module comprises the following functional units:

a P symbol detection unit for detecting whether the symbol of the j-th register and the symbol of the j-1-th third register are two consecutive P symbols when a new symbol which accords with the IRIG-B symbol type is stored in the j-th register of the third register group and the count value of the fourth register is more than 1; if yes, driving the second punctual edge extraction unit to work;

a second time edge extraction unit for storing the rising edge of the j-1 th P code element into the first register of the third register group and setting the counter of the fourth register to be 2;

a start valid register setting unit that sets a start valid register of the 1PPS generation module to 1 when a new symbol conforming to an IRIG-B symbol type is stored in a jth register of the third register group and a count value of a fourth register is > 1; when the count value of the fourth register is 5, the start valid register of the 1PPS generating module is set to 0.

The B code information analysis module comprises the following functional units:

a symbol verification unit for calculating a symbol verification code in time sequence when the count value of the fourth register=100;

and a symbol information extraction unit for discarding the symbol when the symbol check code is inconsistent with the reference check code, and extracting the symbol information when the symbol check code is consistent with the reference check code.

In another aspect, a method for performing time-to-code conversion is provided, including the steps of:

s1: generating a standard signal with stable frequency, and performing frequency multiplication processing on a reference clock signal;

s2: counting the edges of the input signal, and performing second timing on the input signal;

s3: acquiring a time stamp of each code element according to the edge count value and the second timing result of the input signal;

s4: acquiring a corresponding code element period and a code element high level width according to the time stamp of each code element;

s5: according to the code element period and the code element high level width of each code element, combining the frequency multiplication processed reference clock signal and the code element characteristics of IRIG-B codes, and carrying out type identification on each code element; generating serial code element information according to time sequence of all code elements conforming to IRIG-B code element type;

s6: acquiring the position information of a P code element from serial code element information, and extracting second time edge information of IRIG-B code from the position information of the P code element;

s7: according to the serial code element information and the second time edge information, the encoding information of IRIG-B codes is analyzed;

s8: generating week information according to the encoded information;

s9: performing time correction on the coded information;

s10: according to the time-corrected coding information and week information, performing time code coding according to a DCF77 coding format, and outputting a DCF77 code;

s11: according to the second on-time edge information, delaying for 1 second to generate a 1PPS signal; pulse width of 1PPS signal = symbol width of IRIG-B code;

s12: generating a 1PPM signal according to the rising edge of the 1PPS signal and the time-corrected coding information; pulse width of 1PPM signal = pulse width of the 1PPS signal;

s13: and converting the DCF77 code into a physical layer interface signal according to the 1PPS signal and the 1PPM signal, and outputting the physical layer interface signal.

In yet another aspect, an electronic device capable of performing time-to-code conversion is provided, including a second-time-edge extractor for obtaining position information of a P symbol from serial symbol information, and extracting second-time-edge information of an IRIG-B code from the position information of the P symbol; the B code information analyzer is used for analyzing the code information of the IRIG-B code according to the serial code element information and the second punctual edge information; a week information generator for generating week information from the encoded information; the time information corrector is used for performing time correction on the coded information; and the DCF77 code encoder is used for carrying out time code encoding according to a DCF77 encoding format according to the time-corrected encoding information and week information and outputting a DCF77 code.

In yet another aspect, a storage medium is provided in which time-to-code conversion can be performed, the storage medium having stored therein a computer program executable to perform the above method.

Compared with the prior art, the invention has the following advantages and beneficial effects: extracting serial code element information and second time edge information from the input IRIG-B code according to the coding characteristics of the IRIG-B code, analyzing coding information, and extracting time information from the coding information; the extracted time information is generated into a corresponding DCF77 code according to the coding rule of the DCF77 code, so that IRIG-B code is converted into the DCF77 code, and the problem that in the current power system using IRIG-B code time synchronization mode, time synchronization equipment with a DCF77 code output function is required to be added to complete time service of equipment based on the DCF77 code can be solved. The system does not use a CPU, has simple hardware architecture, is convenient for miniaturization and modularization, is convenient to install, and has good expansion performance.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a system capable of performing time-to-code conversion according to embodiment 1 of the present invention;

FIG. 2 is a schematic symbol diagram of IRIG-B codes provided in embodiment 1 of the present invention;

FIG. 3 is a timing diagram of IRIG-B code extraction according to embodiment 1 of the present invention;

fig. 4 is a flowchart of a method for performing time-to-code conversion according to embodiment 2 of the present invention.

Detailed Description

For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.

Example 1

As shown in fig. 1, the system capable of performing time-to-code conversion provided in this embodiment is composed of a 10MHz constant temperature crystal oscillator, a 20 frequency multiplication module, a code element identification module, a second on-time edge extraction module, a B code information analysis module, a week information analysis module, a time correction module, a DCF77 code encoding module, a 1PPS generating module, a 1PPM generating module, a DCF77 code transmitting module and a borrowing driving circuit. The other modules except the interface driving circuit are all realized by the FPGA.

The function of each module of the system, the relation between each module, and the implementation process of converting IRIG-B code into DCF77 code will be explained in detail with reference to fig. 1.

The embodiment adopts a constant-temperature crystal oscillator of 10MHz, and provides a reference clock signal with stable frequency for the FPGA.

The 20 frequency multiplication module utilizes a clock management module (DCM, DLL or PLL) in the FPGA to multiply the frequency of a reference clock signal by 10MHz to 200MHz, and the first Counter-ns of 28 bits is driven by the reference clock signal of 200MHz to count the edges of the arriving input signal; in order to make the counting time length be 1 second, designing a counter of 200000000 and returning to 0 after overflowing, and circularly counting; the overflow signal of the first 28-bit Counter drives the second 30-bit Counter-s to time the arrival of the input signal for a total time period of about 34 years.

The code identification module comprises an initialization unit, which can initialize the value of the first register group to 0 and the value of the second register group to 1; a first register set bma_ts58[200] consisting of 200 58-bit registers for storing a time stamp of an edge of an input IRIG-B (DC) code signal; an 8-bit second register bma_ts_counter for storing the timestamp count value; a third register group BDC_MY [100] consisting of 100 2-bit registers for storing parsed IRIG-B code symbols; an 8-bit fourth register BDC_MY_counter for storing the resolved symbol count; and a logic judging unit, a symbol feature extracting unit, a symbol type judging unit and a control unit.

After the system is powered on, the code element identification module executes the following operations under the control of the control unit:

the value of the B code edge time stamp register BMa_TS58[200] of the initialization register is 0, the value of the B code edge time stamp Counter of the initialization register is 1, and after initialization is completed, the time stamp recording of the input IRIG-B code signal edge is started.

The control unit control logic judging module matches the IRIG-B code input signal edge with the current count value of the second register BMa_TS_counter. The specific implementation mode is as follows:

when the rising edge of the current input signal arrives, if the second register BMa_TS_counter is odd, reading the count values of the first Counter-ns and the second Counter-s, assembling the read count values of the two counters into 58-bit time stamps, storing the assembled time stamps into a register BMa_TS58[ BMa_TS_counter ] of the first register group, and adding 1 to the count value of the second register BMa_TS_counter; otherwise, the time sequence is considered to be wrong, the error processing is converted, the count value of the second register BMa_TS_counter is set to be 1, and the time sequence is restarted.

When the falling edge of the current input signal arrives, if the second register BMa_TS_counter is even, the count values of the first Counter-ns and the second Counter-s are read, the read count values of the two counters are assembled into 58-bit time stamps, the assembled time stamps are stored into a register BMa_TS58[ BMa_TS_counter ] of the first register group, and meanwhile, the count value of the second register BMa_TS_counter is added by 1; otherwise, the timing error is considered, the error processing is converted, the count value of the second register BMa_TS_counter is set to 1, and the timing is restarted.

The count value of the second register bma_ts_counter is monitored in real time. When the count value of the second register bma_ts_counter becomes even and the count value of the second register bma_ts_counter is greater than 3, the control unit controls the symbol feature extraction unit to calculate the symbol period in such a manner that the latest signal rising edge time stamp bma_ts58[ bma_ts_counter-1] minus the previous signal rising edge time stamp bma_ts58[ bma_ts_counter-3 ]; the symbol high level width is calculated by subtracting the preceding signal rising time stamp bma_ts58[ bma_ts_counter_odd-3] from the nearest signal falling time stamp bma_ts58[ bma_ts_counter-2 ].

The control unit controls the code element type distinguishing unit to distinguish the type of each code element according to the calculation result; if the error between the symbol period calculation result and the period of the standard signal is less than or equal to 100 mu s and the error between the symbol high level width calculation result and the width of the standard signal is less than or equal to 100 mu s, analyzing the symbol type according to the symbol definition rule of the IRIG-B code shown in fig. 2, sequentially storing the symbol type into BDC_ [ Bma_TS_Ccounter ] of the first register group, and simultaneously adding 1 to the Bma_TS_Ccounter count value to generate serial symbol information according to time sequence; otherwise, turning to error processing, setting the second register BMa_TS_counter to 1, and restarting the time sequence.

After generating serial symbol information, a P symbol detection unit in the second on-time edge extraction module detects whether the two newly stored symbols are continuous P symbols (P0, pr) when a new symbol which accords with the IRIG-B symbol type is stored in BDC_MY [ BDC_MY_counter ] of the third register group and the count value of a fourth register BDC_MY_counter is greater than 1, as shown in FIG. 3; if yes, storing a time stamp bma_ts58[ bdc_my_counter ] 2-1 into a bma_ts58[1] of the third register set, setting a count value of a fourth register bdc_my_counter to 2, and setting a start valid register flag_1pps of the 1PPS generating module to 1; when the count value of the fourth register bdc_my_counter is 5, the start valid register flag_1pps of the 1PPS generating module is set to 0.

Next, when the count value bdc_my_counter of the fourth register is equal to 100 (that is, 99 valid symbols are obtained, and the time is 990 ms in seconds), the B code information analysis module calculates a check code in advance according to the "IRIG-B code symbol definition" shown in table 1 and the "DCF77 code symbol definition" shown in table 2, and if the calculated check code is inconsistent with the reference check code, determines that the signal transmission has an error, and discards the signal; if the check is passed, code element information is extracted according to the bit by referring to the definition of the code element of the B code, and second, minute, time, day, month, year, leap second advance notice, summer time mark and time zone offset information are obtained by calculation.

Since the code element receiving and decoding of the IRIG-B code signal can be completed only in 1 second, the time information correction module needs to perform 1 second time processing. The processing rules are as follows:

1. at ordinary times, the maximum value of second is 59, and the carry is zeroed; when the positive leap second time comes, the maximum value of "second" is 60, and the carry is zero (the processing mode of the positive leap second is … -57 s-58 s-59 s-60 s-00 s-01 s-02 s- …, namely the total number of seconds of 59 minutes is 61 seconds); when the negative leap second time comes, the maximum value of "second" is 58, and the carry is zero (the negative leap second processing mode is … - & gt 57 s- & gt 58 s- & gt 00 s- & gt 01 s- & gt 02 s- & gt …, namely the 59 th minute total seconds is 59 seconds). Leap seconds may occur at two time points, 1 month, 1 day, 7 hours, 59 minutes, 7 months, 1 day, 7 hours, 59 minutes.

2. The "divide" maximum is 59 and the carry is zeroed.

3. The maximum value of the time is 23, and the carry is reset to zero.

4. The carry of the day is different from the different month rules, the leap years are firstly judged, Y is set as the value of the year, and the year meeting one of the following 2 conditions is the leap year: (1) the year can be divided by 4 and can not be divided by 100, and the ordinary leap year is judged; (2) the year can be divided by 400, and the leap year is judged as century. The maximum values of the corresponding 'days' of the non-leap years 1 to 12 months are 31, 28, 31, 30, 31, 30 and 31 respectively; the corresponding maximum values of "day" for leap years 1 to 12 months are 31, 29, 31, 30, 31, with the carry being zeroed.

5. The maximum value of the month is 12, and the carry is zeroed.

6. The execution of the summer system is stopped in China, the summer system advance notice and the summer system mark can be left unprocessed, and the DCF77 code internal signal is filled in to be 0.

In addition, the 1PPS generating module comprises a 10ms counter local_1PPS_counter; when flag_1pps is changed from 0 to 1, the 1PPS output signal is set to high level, and the local_1pps_counter is started to count from 0, and when the counter local_1pps_counter counts to 200000, the counting is stopped, and the 1PPS output signal is set to low level, thereby realizing generation of the 1PPS signal.

The 1PPM generation module comprises a 10ms counter local_1PPM_counter; when flag_1pps is converted from 0 to 1 and the partial information output by the time information correction module is 0, the 1PPM output signal is set to high level, and the local_1pps_counter is started to count from 0, and when the local_1ppm_counter counts to 200000, the counting is stopped, and the 1PPM output signal is set to low level, thereby realizing the generation of the 1PPM signal.

The week information generation module outputs the year, month and day information according to the time information correction module to calculate week information. The calculation formula is as follows: (y < y/4 > + < c/4 > -2c < 26 (m+1)/10 > + d-1)%7; where c represents century 1 (the first two digits of the year), y represents year (the last two digits), m represents month (m is 3 or more and 14 or less, 1 and 2 months of a certain year are calculated as 13 and 14 months of the last year, for example, 1 month and 1 day of 2003 are calculated as 13 months and 1 day of 2002), and d represents day.

When the partial information outputted by the time information correction module is changed from non-0 to 0 (59 seconds and 999 milliseconds in this time), the DCF77 coding module starts the DCF77 coding sequence, and completes the DCF77 coding meeting the requirement of "DCF77 code symbol definition" in table 2 as follows. The DCF77 coding period is 1 minute, 60 symbols total, symbol period is 1 second, there are 3 symbols, the null symbol is all low level, the pulse width is 0, the symbol 0 pulse width is 100ms, and the symbol 1 pulse width is 200ms. The DCF77 coding scheme is as follows:

1. symbol identification number 0, integral distribution transmission, set to 0;

2. symbol identification number 1-14, transmitting 1-14 seconds, and setting a reserved bit to 0;

3. symbol identification number 15, 15 th second transmission, antenna state, the device is signal conversion, and is set to 0, different from wireless reception;

4. symbol identification number 16, 16 th second transmission, time zone change notification, the device is scheduled to be used in the east-eighth zone, fixedly installed, no time zone change exists, and set to 0;

5. symbol identification numbers 17 and 18, summer time, and the summer time which is stopped to be executed in China is set to be 0;

6. symbol identification number 19, leap second notice, setting 0 when leap second notice information output by the time information correction module is valid, otherwise setting 1;

7. symbol identification number 20, start bit of time code, set to 1;

8. symbol identification numbers 21-27, BCD codes, minute information (bit weight information is 1, 2, 4, 8, 10, 20 and 40 min), and filling in the minute information output by the time information correction module;

9. symbol identification number 28, P1 test bit, parity check of identification numbers 21-28 should be even;

10. symbol identification numbers 29-34, BCD codes, hour information (bit weight information is 1, 2, 4, 8, 10 and 20 h), and filling in the hour information output by the time information correction module;

11. symbol identification number 35, P2 test bit, parity check of identification numbers 29-35 should be odd;

12. symbol identification numbers 36-41, BCD codes, day information (bit weight information is 1, 2, 4, 8, 10 and 20 days), and filling in the day information output by the time information correction module;

13. symbol identification numbers 42-44, BCD codes, week information (bit weight information is 1, 2 and 4) and filling in according to the week information output by the week information generating module;

14. symbol identification numbers 45-49, BCD codes, month information (bit weight information is 1, 2, 4, 8 and 10 days), and filling in the month information output by the time information correction module;

15. symbol identification number 50-57, BCD code, year information (bit weight information is 1, 2, 4, 8, 10, 20, 40, 80 years), according to the year information filling of time information correction module output;

16. symbol identification number 58, P3 test bit, parity check of identification numbers 36-58 should be odd;

17. symbol identification number 59, 59 th second, null symbol, i.e. no information is transmitted in this second. Also used as a start flag, indicating that the next signal start rising edge is the start of the next signal period, and also the start of one minute.

In the DCF77 sending module, when the rising edge of the 1PPM signal output by the 1PPM generating module arrives, the 1PPM signal drives a 6-bit minute Counter-sTm to count time in seconds (namely, the seconds in one minute at present), and in order to make the counting time length be 1 minute, the Counter is designed to be 60 overflows and returns to 0, and the cycle count is carried out; with the rising edge of 1PPS, the signal transmission time sequence circuit of the DCF77 transmission module transmits the code element with the corresponding identification number according to the Counter-sTm count.

The interface driving circuit completes the physical layer interface conversion of the DCF77 signal and outputs the DCF77 time code signal through the RS-485, the optical fiber interface and the empty contact.

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TABLE 1

Symbol identification number	Description of the invention
		0	Minute, usually 0
1～14	Reserved, often 0
		15	Aerial (0 represents normal aerial, 1 represents standby aerial)
16	Time zone change notification (0 indicates normal, 1 indicates standby antenna)
		17～18	Position identification flag #1
19	Leap second announcement, 1h announcement in advance (0 indicates leap, 1 indicates no leap)
		20	TimeThe start bit of the code, usually 1
21～27	Minute information (bit weights 1, 2, 4, 8, 10, 20, 40min respectively)
		28	The parity check of the P1 test bit, 21-28 bits should be even, usually 1
29～34	Hour information (bit weights 1, 2, 4, 8, 10, 20h respectively)
		35	The parity check of the P2 test bit, 29 to 35 should be odd, usually 0;
36～41	day information of the month (1, 2, 4, 8, 10, 20 days respectively)
		42～44	Week information (bit weights 1, 2, 4 respectively)
45～49	Month information (bit weights 1, 2, 4, 8, 10 months respectively)
		50～57	Year information (bit rights 1, 2, 4, 8, 10, 20, 40, 80 years respectively)
58	The parity check of the P3 test bit, the identification numbers 36-58 should be odd, usually 0
		59	Null symbols;

TABLE 2

Example 2

Corresponding to embodiment 1, the present embodiment provides a method for performing time-to-code conversion, and the basic principle and implementation flow of the method are shown in fig. 4, which includes the following steps:

s1: generating a reference clock signal with stable frequency, and performing frequency multiplication processing on the reference clock signal;

s8: generating week information according to the encoded information;

s9: performing time correction on the coded information;

Example 3

Corresponding to embodiment 1, the present embodiment provides an electronic device capable of performing time-to-code conversion, including a second-time-edge extractor for acquiring position information of a P symbol from serial symbol information and extracting second-time-edge information of an IRIG-B code from the position information of the P symbol; the B code information analyzer is used for analyzing the code information of the IRIG-B code according to the serial code element information and the second punctual edge information; a week information generator for generating week information from the encoded information; the time information corrector is used for performing time correction on the coded information; and the DCF77 code encoder is used for carrying out time code encoding according to a DCF77 encoding format according to the time-corrected encoding information and week information and outputting a DCF77 code.

Example 4

Corresponding to embodiment 2, the present embodiment provides a storage medium in which time-to-code conversion can be performed, the storage medium having stored therein a computer program executable by the method as in embodiment 2.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A system for performing time-to-code conversion, comprising

and the DCF77 code coding module is used for carrying out time code coding according to the DCF77 coding format according to the time-corrected coding information and the week information and outputting a DCF77 code.

2. The system for performing time-to-code conversion according to claim 1, further comprising

a second counter for counting seconds of the incoming signal;

a symbol identification module for executing the following operations: acquiring a time stamp of each code element according to the count value of the first counter and the count value of the second counter; acquiring a corresponding code element period and a code element high level width according to the time stamp of each code element; according to the symbol period and the symbol high level width of each symbol, combining the symbol characteristics of the standard signal and the IRIG-B code, and performing type identification on each symbol; all symbols conforming to the IRIG-B symbol type are time-sequentially generated into serial symbol information.

3. The system for performing time-to-code conversion according to claim 2, wherein the symbol recognition module comprises an initializing unit, a first register set, a second register, a third register set, a fourth register, a logic judgment unit, a symbol feature extraction unit, a symbol type judgment unit, and a control unit;

the control unit is used for executing the following operations:

the control initialization unit initializes the value of the first register group to 0 and the value of the second register group to 1;

the control logic judging module matches the IRIG-B code input signal edge with the current count value of the second register;

identifying a matching result; if the current IRIG-B code input signal edge is a rising edge and the current count value of the second register is an odd number, or the current IRIG-B code input signal edge is a falling edge and the current count value of the second register is an even number, assembling the count value of the first counter and the count value of the second counter into corresponding time stamps, storing the assembled time stamps into an ith register of the first register group, wherein i=the current count value of the second register, and adding 1 to the count value of the second register; if the current IRIG-B code input signal edge is a rising edge and the current count value of the second register is even, or the current IRIG-B code input signal edge is a falling edge and the current count value of the second register is odd, setting the count value of the second register to be 1, and restarting the time sequence;

monitoring the count value of the second register in real time; when the count value of the second register is even and is more than 3, the control code element characteristic extraction unit calculates each code element to carry out code element period and code element high level width;

the control code element type discriminating unit discriminates the type of each code element according to the calculation result; if the error between the symbol period calculation result and the period of the standard signal is less than or equal to 100 mu s and the error between the symbol high level width calculation result and the width of the standard signal is less than or equal to 100 mu s, storing the symbol into a j-th register of the third register group, wherein j=i/2; otherwise, setting the count value of the second register to be 1, and restarting the time sequence;

the symbols of the first to j-th registers of the third register group are sequentially generated into serial symbol information.

4. A system for performing time-to-code conversion according to claim 3 wherein the second on-time edge extraction module comprises

A P symbol detection unit for detecting whether the symbol of the j-th register and the symbol of the j-1-th register are two consecutive P symbols when a new symbol which accords with the IRIG-B symbol type is stored in the j-th register of the third register group and the count value of the fourth register is more than 1; if yes, driving the second punctual edge extraction unit to work;

and the second time edge extraction unit is used for storing the rising edge of the j-1 th P code element into the first register of the third register group and setting the counter of the fourth register to be 2.

5. A system for performing time-to-code conversion as in claim 3 wherein the B-code information parsing module comprises

6. A system for performing time-to-code conversion according to claim 3, further comprising

7. The system for performing time-to-code conversion according to claim 6, wherein the second on-time edge extraction module further comprises a start-point valid register setting unit for setting the start-point valid register of the 1PPS generation module to 1 in the case that a new symbol conforming to the IRIG-B symbol type is stored in the j-th register of the third register group and the count value of the fourth register is > 1; when the count value of the fourth register is 5, the start valid register of the 1PPS generating module is set to 0.

8. A method for performing time-to-code conversion, comprising the steps of:

s1: acquiring the position information of a P code element from serial code element information, and extracting second time edge information of IRIG-B code from the position information of the P code element;

s2: according to the serial code element information and the second time edge information, the encoding information of IRIG-B codes is analyzed;

s3: generating week information according to the encoded information;

s4: performing time correction on the coded information;

s5: according to the time-corrected coding information and week information, performing time code coding according to a DCF77 coding format, and outputting a DCF77 code;

the time-to-code conversion may be performed and the time-to-code conversion may be performed.

9. An electronic device capable of performing time-to-code conversion, comprising

A second on-time edge extractor for acquiring the position information of the P code element from the serial code element information and extracting the second on-time edge information of the IRIG-B code from the position information of the P code element;

the B code information analyzer is used for analyzing the code information of the IRIG-B code according to the serial code element information and the second punctual edge information;

a week information generator for generating week information from the encoded information;

the time information corrector is used for performing time correction on the coded information;

and the DCF77 code encoder is used for carrying out time code encoding according to a DCF77 encoding format according to the time-corrected encoding information and week information and outputting a DCF77 code.

10. A storage medium having stored therein a computer program executable to perform the method of claim 8.