CN106502309A - It is zeroed based on DA and keeps time domain intertexture random waveform synthesizer and the method for function - Google Patents
It is zeroed based on DA and keeps time domain intertexture random waveform synthesizer and the method for function Download PDFInfo
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Abstract
The invention discloses a kind of keep the time domain intertexture random waveform synthesizer of function and method to be arranged according to the waveform parameter of user based on DA zeros, produce random waveform data, data reading speed is calculated by sample rate and vertical resolution, Wave data is read according to reading speed, DDS Wave datas are obtained；The even number of samples point data of DDS Wave datas is transferred to the DA chips for being kept function using zero, odd samples point data is transferred to the 2nd DA chips that function is kept using zero, and the analogue signal of two-way DA chips output realizes the vector addition of two-way analogue signal through impedance matching, precision time delay adjustment and Signal averaging；Analogue signal after to addition is filtered and control signal amplitude, obtains output waveform.The present invention is zeroed using two-way DA and keeps the Signal averaging of function output, and the DA zeroth orders for being equivalent to twice sample rate keep the output signal of function, will not introduce other amplitudes and phase variant, without the need for compensation, improve sample rate.
Description
Technical field
The present invention relates to a kind of zero based on DA keeps time domain intertexture random waveform synthesizer and the method for function.
Background technology
High speed arbitrary waveform generation technique is the signal generation technique based on numeral, simulation and computer technology, extensively
General be applied in the fields such as radar, satellite communication, electronic countermeasure, radio frequency testing, integrated circuit testing, high speed arbitrary waveform occur
Technology has become the study hotspot in modern electronic technology field.High speed arbitrary waveform generator with the technology as core has
Output frequency degree of stability and high resolution, frequency error factor speed are fast, and when switching the advantages of output waveform Phase Continuation, which is rich
Rich signal fillip includes high speed waveform generator, functional generator, pulse/sequencer, frequency sweep generator, triggering
Generator, broadband white noise signal generator and amplitude modulation(PAM) source etc..There is sequence address control function simultaneously, numeral can be produced
Modulated signal, the various sophisticated signals of simulation, or even the defect in signal and transient signal etc..With the development of electronic technology,
High speed arbitrary waveform generator can be in broadband connections, radar system, high-speed pulse simulation, high-speed digital design, site environment
Multiple applications such as simulation and playback have important function.
The sample rate of high speed arbitrary waveform generation and Bandwidth-Constrained are in the sample rate and bandwidth of DA.Due to being set by DA chips
Meter level and the restriction of processing technique, the sample rate and bandwidth of single channel DA cannot meet the demand of high speed arbitrary waveform generation.Mesh
Before, DA parallel schemas are the major routes for solving the problem, mainly include interpolated waveforms synthetic method and are kept based on DA zeroth orders
The time domain intertexture Waveform composition method of function.By taking 2 road DA signal synthesis as an example, interpolated waveforms synthetic method adopts on-off circuit reality
The interpolation of existing 2 road DA analogue signals.DA-1 is arrived in the even number point output of Wave data, the odd point output of Wave data is arrived
DA-2.2：In the presence of 1 selecting switch, the output of DA-1 and DA-2 is alternately sent to outfan.Waveform sampling rate is DA
Sample rate and the twice of on-off circuit clock, effectively improve sample rate.The method requires higher to on-off circuit.It is based on DA zeroth orders
Keep the time domain intertexture Waveform composition method of function that the even number point output of Wave data is arrived DA-1, by the odd point of Wave data
Export DA-2.The clock frequency of two-way DA is the half of waveform sampling rate, phase 180 degree.Realized by adder
The superposition of DA analogue signals.The output signal of superposition can break through the restriction of single channel DA sample rate and bandwidth, realize sample rate
Improve, but also change amplitude and the initial phase of Wave data.
Some high speed arbitrary waveform generators existing adopt interpolated waveforms synthetic method, and this method is to on-off circuit
Switching time, jittering noise and service life require higher, limit larger in frequency applications.Some other high speed arbitrary waveform
Generator need to add width in Wave data using the time domain intertexture Waveform composition method for keeping function based on DA zeroth orders, the method
Degree and phase correction factor, complex operation.Meanwhile, DA zeroth orders keep function pair output signal spectrum envelope decay speed,
The 40% of waveform sampling rate can not be reached under the conditions of uncompensated.Additionally, above two method does not reduce the mistake of DA analogue signals
The measure of tune, it is impossible to ensure the quality of output signal.
Content of the invention
The present invention is in order to solve the above problems, it is proposed that a kind of zero based on DA keeps the time domain intertexture random waveform of function
Synthesizer and method, in time domain intertexture Waveform composition without the need for adding correction factor in Wave data, DA is zeroed for the invention
Keep function pair output signal spectrum envelope decay that there is gentle roll-off characteristic, with larger bandwidth, while adding impedance
Matching network and precision time delay adjustment reduce the imbalance of signal, with simple to operate, realize that difficulty is low, little excellent of distorted signals
Point.
To achieve these goals, the present invention is adopted the following technical scheme that：
A kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function, including controller, parallel signal
Generation module, time domain interleaving block and passage conditioning module, the time domain interleaving block include that two keep function using zero
DA chips, wherein：
Wave data is transferred to parallel signal and module occurs by the controller, and the parallel signal occurs module, one
The rising edge of individual sampling clock produces multiple output phases of waveform simultaneously, simultaneously waveform is looked into by the multiple phase values for exporting
Table addressing is looked for, corresponding DDS data are obtained, the even number of samples point data of DDS Wave datas is transferred to letter is kept using zero
Several DA chips, odd samples point data is transferred to the 2nd DA chips for being kept function using zero, two-way DA chips
The analogue signal of output realizes the vector addition of two-way analogue signal through impedance matching, precision time delay adjustment and Signal averaging,
Passage conditioning module to addition after analogue signal nurse one's health, form final composite result.
The DA chips for keeping function using zero, output envelope frequency spectrum have gentle roll-off characteristic.
The sample clock frequency of described two-way DA is the half of sample rate, phase 180 degree.
There are the signal of the DDS Data odd sampled points of DA chips output, the 2nd DA cores in the rising edge of sampling clock
The signal of piece is 0；Trailing edge has the signal output of the DDS Data even sampled points of the 2nd DA chips output, DA chips
Signal is 0, and the DA zeroth orders for being equivalent to twice sample rate keep the output signal of function.
The controller connects parallel signal by memory management module and module, the memory management module received wave occurs
Graphic data, and by its storage value mass storage, after storage is finished, pass through high speed serialization according to valid data transfer rate
Wave data is transferred to parallel signal and module occurs by bus.
Product of the valid data transfer rate for the vertical resolution of the sample rate and DA chips of Wave data.
The controller is configured with human-computer interaction module, enters edlin by human-computer interaction module to waveform, obtains waveform
Data, the file that Wave data is stored as .data forms quantify transmission further according to quantization digit to Wave data.
The quantization digit is determined by vertical resolution D of DA chips.
There is module in the parallel signal, including phase accumulator, the phase accumulator connects multichannel phase addition device,
Each phase addition device is addressed that equipped with waveform look-up table obtain corresponding DDS data, all DDS data are transferred to
Parallel serial conversion module；The phase accumulator is also associated with the clock unit for providing clock frequency.
The parallel way of the phase accumulator is more than or equal to Wave data sample rate and the business of clock frequency.
The time domain interleaving block includes two-way DA chips, impedance matching network, precision time delay module and vector superposed mould
Block, carries out digital-to-analogue conversion respectively to DDS Data odds sampled point and odd samples point data, and impedance matching network reduces two-way DA
Amplitude imbalance between chip signal output, the sequential that precision time delay module is used for adjusting between two-way DA chip signal outputs are lost
Adjust, vector superposed module is used for the superposition of two-way DA output signals and synthesizes.
Signal after superposition has signal output in sampling clock rising edge and trailing edge, is equivalent to zeroth order all the way and keeps
The signal output of the DA of function, its sample rate are the twices of DA chips and the 2nd DA chips.
The passage conditioning module includes that low-pass filtering module and amplitude control module, the low-pass filtering module filter band
Spurious signal outside width, amplitude control module carries out decaying, amplify and direct current biasing is processed, and makes output signal meet amplitude and partially
The requirement that puts.
A kind of zero based on DA keeps the time domain intertexture random waveform synthetic method of function, comprises the following steps：
(1) arranged according to the waveform parameter of user, produce random waveform data；
(2) data reading speed is calculated by sample rate and vertical resolution, waveform number is read according to reading speed
According to obtaining DDS Wave datas；
(3) the even number of samples point data of DDS Wave datas is transferred to the DA chips for being kept function using zero, will
Odd samples point data is transferred to the 2nd DA chips for keeping function using zero, and the analogue signal of two-way DA chips output is passed through
Impedance matching, precision time delay adjustment and Signal averaging realize the vector addition of two-way analogue signal；
(4) to addition after analogue signal be filtered and control signal amplitude, obtain output waveform.
Beneficial effects of the present invention are：
(1) present invention is zeroed using two-way DA and keeps the Signal averaging of function output, is equivalent to the DA zero of twice sample rate
Rank keeps the output signal of function, will not introduce other amplitudes and phase variant, without the need for compensation, operates relatively simple, raising
Sample rate；
(2) DA zeros of the present invention keep function pair output signal spectrum envelope decay that there is gentle roll-off characteristic, in phase
There is during with sample rate larger bandwidth；
(3) present invention reduces amplitude imbalance when time domain interweaves using impedance matching network, by precision time delay adjustment drop
Low sequential imbalance, little have the advantages that distorted signals.
Description of the drawings
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the Whole Work Flow figure of the present invention；
Fig. 3 is that the parallel signal generation module of the present invention realizes block diagram；
Fig. 4 is that the time domain interleaving block of the present invention realizes block diagram；
Fig. 5 is that the DA zeros of the present invention keep function sequential chart；
Fig. 6 is the output spectrum envelope curve figure that the DA zeros of the present invention keep function；
Fig. 7 is the Signal averaging sequential chart of the present invention；
Fig. 8 is the output envelope frequency spectrum figure after the superposition of the present invention.
Specific embodiment：
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
The present invention proposes a kind of time domain intertexture of the holding function that is zeroed based on DA occurred suitable for high speed arbitrary waveform
Random waveform synthesizer, it are zeroed by two-way and keep the DA time domains of function to interweave.Arranged according to the waveform parameter of user,
Main frame produces random waveform data and is transferred to mass storage.It is calculated from great Rong by sample rate and vertical resolution
Amount memorizer reading speed, reading Wave data from mass storage according to reading speed carries out parallel DDS signals generation,
Obtain DDS Wave datas.The even number of samples point data of DDS Wave datas is transferred to the DA cores for being kept function using zero
Piece, odd samples point data is transferred to the 2nd DA chips for being kept function using zero, and the sample clock frequency of two-way DA is equal
For the half of sample rate, phase 180 degree.Two-way DA output analogue signal through impedance matching, precision time delay adjust and
Signal averaging realizes the vector addition of two-way analogue signal.Finally to addition after analogue signal nurse one's health, main include filter
Ripple and control signal amplitude.The device output waveform sample rate is the twice of sampling clock and DA sample rates, and bandwidth can reach ripple
The 40% of shape sample rate, have the advantages that sample rate height and with roomy.
Random waveform synthesizer mainly includes that main frame, memory management module, high-speed large capacity memory, parallel signal are sent out
Raw module, time domain interleaving block, passage conditioning module and clock module.Theory diagram is as shown in Figure 1.Main frame provides man-machine interaction
Editor of the functional realiey user to waveform, obtains Wave data.Then Wave data is stored as main frame the text of .data forms
Part.Last main frame quantifies transmission according to quantization digit to Wave data.Quantization digit is determined by vertical resolution D of DA.Overall
Workflow diagram is as shown in Figure 2.
Memory management module mainly includes high-speed serial bus module, data cache module and storage control module, by
Fpga logic is realized.High-speed large capacity memory is arrived in the Wave data storage of main frame first, the capacity of memorizer is more than waveform
The data volume of data.After storage is finished, memory management module is pressed valid data transfer rate S and passes through high-speed serial bus by ripple
Graphic data is transferred to parallel signal and module occurs.
S=fs×D (1)
Wherein fsFor the sample rate of Wave data, D is vertical resolution.
There is the parallel DDS signals generation that module completes Wave data in parallel signal, realized by fpga logic.Wave data
Sampling rate to number GHz levels, phase accumulator and wave memorizer operating rate in the FPGA are only hundreds of MHz levels.For
The restriction of operating rate is broken through, when hardware is realized, by Wave data parallel memorizing and sampling, in the upper of a sampling clock
Rise along the multiple output phases for producing waveform simultaneously, by multiple phase values of output simultaneously to waveform look-up table addressing, obtain
Corresponding DDS data.Realize that block diagram is as shown in Figure 3.Hypothesis frequency control word is K, and the digit of phase accumulator is N, parallel DDS
Way be m, the sample rate of Wave data is mfa, then the frequency of output signal be represented by：
Wherein, fs=mfa, 0≤K≤2N-1.
Frequency resolution is：
The value of m is：
Wherein, fFClock frequency for FPGA steady operations.
There is module by Wave data parallel memorizing and sampling in parallel signal, produced in the rising edge of a sampling clock simultaneously
Multiple output phases of raw waveform, by multiple phase values of output simultaneously to waveform look-up table addressing, obtain corresponding DDS numbers
According to.Wherein, parallel way is more than or equal to Wave data sample rate and the business of the clock frequency of FPGA steady operations.
By formula (2) as can be seen that sample rate is faThe parallel DDS signal outputs in m roads be equivalent to sample frequency for mfaList
The output effect of DDS.Can obtain from formula (3), the parallel DDS signals in m roads occur the frequency resolution for not changing output signal, only
It is in a sampling clock cycle, while generating m phase value and m waveform data points.So as to by phase accumulator and ripple
The operating rate of shape memorizer reduces m times.Finally the DDS Data odds sampled point of generation and odd samples point are respectively transmitted to
Time domain interleaving block.
Time domain interleaving block includes two-way DA, impedance matching network, precision time delay module and vector superposed module.Realize frame
Figure is as shown in Figure 4.Two-way DA includes DA chips and the 2nd DA chips, and respectively DDS Data odds sampled point and odd number are adopted
Sampling point data carry out digital-to-analogue conversion.Two-way DA keeps function mode using zero, in the rising edge output signal of DA clocks, in DA
The trailing edge of clock is output as 0, and sequential chart is as shown in Figure 5.Keep function to carry out Fourier transformation zero and obtain output signal
Spectrum envelope function be：
Wherein, sampling periods of the T for single channel DA.Zero keeps function output envelope frequency spectrum figure as shown in fig. 6, wherein fbFor
The sample rate of single channel DA.As can be seen from the figure zero keeps function output envelope frequency spectrum that there is gentle roll-off characteristic, samples
Rate fb80% bandwidth in Amplitude Compensation be less than 3dB.In the half the time of clock cycle, signal is 0, so initial value declines
It is kept to -6dB.
Two-way DA clock phases differ 180 degree, and sampling clock is fanned out to as two-way, is input to DA chips all the way, another
The trailing edge of the corresponding 2nd DA chip clocks of the 2nd DA chips, the i.e. rising edge of DA chip clocks is input to after road is anti-phase,
Wherein sampling clock is produced by clock module.In this case, the rising edge in sampling clock has the DDS that DA chips are exported
The signal of Data odd sampled point, the signal of the 2nd DA chips is 0；Trailing edge has the DDS Data evens that the 2nd DA chips are exported
The signal output of sampled point, the signal of DA chips is 0.Impedance matching network is used for reducing between two-way DA output signals
Amplitude is lacked of proper care, and precision time delay module is used for adjusting the sequential imbalance between two-way DA output signals.Vector superposed module is used for two
The superposition synthesis of road DA output signals.Signal averaging sequential chart is as shown in fig. 7, the signal after superposition is in sampling clock rising edge
There is signal output with trailing edge, be equivalent to the signal output that zeroth order all the way keeps the DA of function, its sample rate is DA cores
Piece and the twice of the 2nd DA chips.The function that keeps after to superposition carries out the spectrum envelope letter that Fourier transformation obtains output signal
Number is：
Wherein, TsSampling period for Wave data.Output envelope frequency spectrum figure after superposition is as shown in figure 8, can from figure
To find out, -6dB the decay of initial value can be compensated as 0dB by the superposition of 2 tunnels.The sample rate of time domain interleaving block output signal
fsFor single channel DA sample rate fbTwice, i.e. fb=fs/2.According to image signal and non-linear harmonic wave principle of cancellation, in 2fbBandwidth
Interior image signal and non-linear harmonic wave are cancelled, only useful signal, and output signal bandwidth can reach output signal and adopt
Sample rate fs40%.
The DA chips that function is kept using zero, output envelope frequency spectrum have gentle roll-off characteristic.Returned using two-way DA
The output signal of zero hold function is overlapped, and two-way DA clock phases differ 180 degree, have first in the rising edge of sampling clock
The signal of the DDS Data odd sampled points of DA chips output, the signal of the 2nd DA chips is 0；Trailing edge has the 2nd DA chips defeated
The signal output of the DDS Data even sampled points for going out, the signal of DA chips is 0, is equivalent to the DA zeroth orders of twice sample rate
Keep the output signal of function.
Passage conditioning module includes that low-pass filtering and amplitude control two parts.Low-pass filtering filters the spuious letter outside bandwidth
Number.Amplitude control includes decay, amplifies and direct current biasing, makes output signal meet the requirement of amplitude and biasing.Finally by signal
Export outside device.
Clock module is memory management module, parallel signal occurs module and time domain interleaving block provides clock.
Although the above-mentioned accompanying drawing that combines is described to the specific embodiment of the present invention, not to present invention protection model
The restriction that encloses, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not
The various modifications that makes by needing to pay creative work or deformation are still within protection scope of the present invention.
Claims (10)
1. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function, it is characterized in that：Including controller and
Row signal generating module, time domain interleaving block and passage conditioning module, the time domain interleaving block include that two are protected using zero
The DA chips of function are held, wherein：
Wave data is transferred to parallel signal and module occurs by the controller, and the parallel signal occurs module, adopts at one
The rising edge of sample clock produces multiple output phases of waveform simultaneously, by multiple phase values of output simultaneously to waveform look-up table
Addressing, obtains corresponding DDS data, the even number of samples point data of DDS Wave datas is transferred to and keeps function using zero
First DA chips, odd samples point data is transferred to the 2nd DA chips for being kept function using zero, and two-way DA chips are exported
Analogue signal adjust through impedance matching, precision time delay and Signal averaging realizes the vector addition of two-way analogue signal, passage
Conditioning module to addition after analogue signal nurse one's health, form final composite result.
2. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：The DA chips for keeping function using zero, output envelope frequency spectrum have gentle roll-off characteristic.
3. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：The sample clock frequency of described two-way DA is the half of sample rate, phase 180 degree.
4. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：There is the signal of the DDS Data odd sampled points of DA chips output in the rising edge of sampling clock, the 2nd DA chips
Signal is 0；Trailing edge has the signal output of the DDS Data even sampled points of the 2nd DA chips output, the signal of DA chips
For 0, the DA zeroth orders for being equivalent to twice sample rate keep the output signal of function.
5. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：The controller connects parallel signal by memory management module and module occurs, and the memory management module receives waveform
Data, and by its storage value mass storage, after storage is finished, pass through high speed serialization according to valid data transfer rate total
Wave data is transferred to parallel signal and module occurs by line.
6. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 5, and which is special
Levying is：Product of the valid data transfer rate for the vertical resolution of the sample rate and DA chips of Wave data.
7. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：There is module in the parallel signal, including phase accumulator, the phase accumulator connects multichannel phase addition device, per
Individual phase addition device is addressed that equipped with waveform look-up table obtain corresponding DDS data, all DDS data are transferred to simultaneously
String modular converter；The phase accumulator is also associated with the clock unit for providing clock frequency.
8. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：The time domain interleaving block includes two-way DA chips, impedance matching network, precision time delay module and vector superposed module,
Digital-to-analogue conversion is carried out to DDS Data odds sampled point and odd samples point data respectively, and impedance matching network reduces two-way DA cores
Amplitude imbalance between piece output signal, the sequential that precision time delay module is used for adjusting between two-way DA chip signal outputs are lost
Adjust, vector superposed module is used for the superposition of two-way DA output signals and synthesizes；
Signal after superposition has signal output in sampling clock rising edge and trailing edge, is equivalent to zeroth order all the way and keeps function
DA signal output, its sample rate is the twice of DA chips and the 2nd DA chips.
9. a kind of zero based on DA keeps the time domain intertexture random waveform synthesizer of function as claimed in claim 1, and which is special
Levying is：The passage conditioning module includes that low-pass filtering module and amplitude control module, the low-pass filtering module filter bandwidth
Outer spurious signal, amplitude control module are carried out decaying, are amplified and direct current biasing process, make output signal meet amplitude and biasing
Requirement.
10. a kind of zero based on DA keeps the time domain intertexture random waveform synthetic method of function, it is characterized in that：Including following step
Suddenly：
(1) arranged according to the waveform parameter of user, produce random waveform data；
(2) data reading speed is calculated by sample rate and vertical resolution, Wave data is read according to reading speed, is obtained
Arrive DDS Wave datas；
(3) the even number of samples point data of DDS Wave datas is transferred to the DA chips that function is kept using zero, by odd number
Sample point data is transferred to the 2nd DA chips for keeping function using zero, and the analogue signal of two-way DA chips output is through impedance
Coupling, precision time delay adjustment and Signal averaging realize the vector addition of two-way analogue signal；
(4) to addition after analogue signal be filtered and control signal amplitude, obtain output waveform.
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| CN107589411B (en) * | 2017-08-31 | 2019-06-21 | 成都玖锦科技有限公司 | A kind of fast multi-target signal synthesis method |
| CN107589410B (en) * | 2017-08-31 | 2019-06-21 | 成都玖锦科技有限公司 | A kind of no breakpoint Multiple Target Signals synthetic method |
| CN109793567A (en) * | 2019-01-03 | 2019-05-24 | 杭州电子科技大学 | A kind of DDS waveform generating module of Medical Devices cloud system |
| CN110798212B (en) * | 2019-10-29 | 2023-03-24 | 中电科思仪科技股份有限公司 | Time domain interleaved waveform synthesis timing mismatch calibration device and method |
| CN110798212A (en) * | 2019-10-29 | 2020-02-14 | 中电科仪器仪表有限公司 | Time domain interleaved waveform synthesis timing mismatch calibration device and method |
| CN111220846A (en) * | 2020-03-10 | 2020-06-02 | 星汉时空科技(北京)有限公司 | High-speed sampling full-digitalization frequency stability testing equipment and method |
| CN111220846B (en) * | 2020-03-10 | 2022-04-19 | 星汉时空科技(北京)有限公司 | High-speed sampling full-digitalization frequency stability testing equipment and method |
| CN115097897A (en) * | 2022-05-20 | 2022-09-23 | 珠海市运泰利自动化设备有限公司 | Phase-staggered interleaving output method of signal generator |
| CN115097897B (en) * | 2022-05-20 | 2023-11-03 | 珠海市运泰利自动化设备有限公司 | Staggered weaving output method of signal generator |
| CN116055928A (en) * | 2023-04-03 | 2023-05-02 | 深圳市紫光同创电子有限公司 | Data sampling method, device, electronic equipment and storage medium |
| CN116055928B (en) * | 2023-04-03 | 2023-06-02 | 深圳市紫光同创电子有限公司 | Data sampling method, device, electronic equipment and storage medium |
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