CN112886951B - Multi-clock source seamless switching circuit and method of high-precision time keeping equipment - Google Patents
Multi-clock source seamless switching circuit and method of high-precision time keeping equipment Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- G04G—ELECTRONIC TIME-PIECES
- G04G7/00—Synchronisation
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a multi-clock source seamless switching circuit and method of high-precision time keeping equipment, and belongs to the field of high-precision time keeping equipment. According to the multi-clock source seamless switching circuit and method of the high-precision time keeping equipment, through the cooperative work of the clock monitoring module, the time correction and time keeping control module, the clock switching and output control module, all clocks in the time keeping equipment are subjected to time keeping operation, and each clock is synchronously subjected to frequency calibration with the local clock source accessed by the clock source in real time, so that when one or more clocks are abnormal in operation, automatic detection of clock abnormality and automatic seamless switching of clocks and synchronous time signals can be realized. The switching method can realize seamless switching of the local clock source, can not cause loss of second pulse and can ensure the time keeping precision of time keeping equipment to the maximum extent.
Description
Technical Field
The invention belongs to the field of high-precision time keeping equipment, and particularly relates to a multi-clock source seamless switching circuit and method of high-precision time keeping equipment.
Background
In a power system and a distributed test control equipment system, the synchronous acquisition and measurement of state parameters, synchronous instruction control and the like have great operational significance. In order to solve the problems of synchronous acquisition measurement and synchronous instruction control of the remote distributed system, high-precision time keeping equipment is required to perform time synchronization operation on the remote equipment, so that the time synchronization of the remote distributed system is realized, and the synchronous operation is realized.
The high precision time keeping device generally has three main functions: timing function, time keeping function and time service function. (1) The timing function is to calibrate the time of the device itself by the standard time provided by the external GPS receiver and/or other device interfaces, so that the local time can be aligned with the standard absolute time; (2) The time keeping function is to maintain the operation of the local time by only relying on the local high-precision clock under the condition that the GPS is unlocked or no external standard clock source is available after the time correction is completed, so that the GPS can be consistent with the standard absolute time as much as possible in a longer time. (3) The time service function is that the time keeping device outputs the standard time and second pulse signals of the internal operation for other systems or devices. In order to ensure the reliability of the local clock, a plurality of clock sources are usually arranged locally, and even if one or more local clock sources are abnormal, the clock sources can also execute the timekeeping function by depending on other clocks which normally work. When switching clock sources among a plurality of local clock sources, the conventional common switching method is usually realized by software, when a certain local clock is abnormal, an interrupt is submitted to the software, the software is used for completing the switching of the clock sources and the compensation of precision loss, and the processing method can cause the loss of time-keeping precision or the loss of second pulse.
The invention relates to a method for checking and switching two same-frequency clocks used for circuit operation, which is different from the clock concept applied to the timekeeping device, and meanwhile, the circuit only completes the clock switching function, can not retain and maintain the absolute time information in the device, and is not applicable to the timekeeping device.
Disclosure of Invention
The invention aims to overcome the defect that the loss of time keeping precision or the loss of second pulse can be caused by the conventional method for switching a plurality of local clock sources by means of software, and provides a multi-clock source seamless switching circuit and method of high-precision time keeping equipment.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a multi-clock source seamless switching circuit of high-precision time keeping equipment comprises N clock monitoring modules, N time correcting and time keeping control modules and a clock switching processing module;
the clock monitoring module is used for performing frequency multiplication processing on an input clock signal and monitoring whether an external clock signal is normal or not;
the timing and time keeping control module is used for executing synchronous alignment operation on the internal time and the external standard synchronous time when external standard second pulse and standard synchronous time are input under the drive of a local clock signal, and simultaneously performing frequency correction on the internal clock according to the externally input second pulse, and realizing the generation of the standard synchronous time through the frequency correction clock after the frequency correction is completed;
if no external standard second pulse and standard synchronization time are input and other external clock signals work abnormally, executing a time keeping function according to the internally locked synchronization time;
if no external standard second pulse and standard synchronous time are input and one of other external clock signals works normally, taking the clock signal which works normally as a standard clock source, performing frequency correction on the internal clock, and simultaneously realizing the generation of the standard synchronous time through the frequency correction clock;
the clock switching and outputting control module is used for processing the second pulse and the standard synchronous time output by the timing and time keeping control module and outputting a synchronous second pulse and a standard synchronous time;
n is a positive integer greater than or equal to 2.
Further, the clock switching and outputting control module is used for combining the second pulses generated by the N timing and time keeping control modules to generate a synchronous second pulse;
the clock switching and outputting control module is used for periodically detecting the state of the clock, detecting clock signals when synchronizing the rising edge of the second pulse, latching the synchronous time information input by the corresponding timing and time keeping control module with the normal working state of the clock based on the detection result, and outputting the latched synchronous time information as the final synchronous time.
Furthermore, the clock switching and output control module realizes periodic detection of the state of the clock based on a state machine.
Further, the clock switching and output control module combines the N time correction/time keeping control modules to generate a synchronous second pulse based on a logic or process of the N inputs.
The switching method of the multi-clock source seamless switching circuit of the high-precision time keeping device comprises the following steps:
the clock monitoring module carries out frequency multiplication processing on an input clock signal and monitors whether an external clock signal is normal or not;
the timing and time keeping control module is driven by a local clock signal, when external standard second pulses and standard synchronous time are input, the internal time and the external standard synchronous time are subjected to synchronous alignment operation, meanwhile, the internal clock is subjected to frequency correction according to the second pulses input from the outside, and standard synchronous time is generated through the frequency correction clock after the frequency correction is completed;
if no external standard second pulse and standard synchronization time are input and other external clock signals work abnormally, executing a time keeping function according to the internally locked synchronization time;
if no external standard second pulse and standard synchronous time are input and one of other external clock signals works normally, taking the clock signal which works normally as a standard clock source, performing frequency correction on the internal clock, and simultaneously realizing the generation of the standard synchronous time through the frequency correction clock;
the clock switching and outputting control module processes the second pulse and the standard synchronous time output by the timing and time keeping control module and outputs a synchronous second pulse and a standard synchronous time;
n is a positive integer greater than or equal to 2.
Further, the clock switching and outputting control module synthesizes the second pulses generated by the N timing and time keeping control modules to generate a synchronous second pulse;
the clock switching and outputting control module is used for periodically detecting the state of the clock, detecting a clock signal when the rising edge of the second pulse is synchronized, latching the synchronous time information input by the corresponding timing and time keeping control module with the normal working state of the clock based on the detection result, and outputting the latched synchronous time information as the final synchronous time.
Compared with the prior art, the invention has the following beneficial effects:
according to the multi-clock source seamless switching circuit and method of the high-precision time keeping equipment, through the cooperative work of the clock monitoring module, the timing and time keeping control module, the clock switching and output control module, all clocks in the time keeping equipment are subjected to time keeping operation, and each clock is synchronously subjected to frequency calibration with the high-priority local clock source accessed by the clock in real time, so that when one or more clocks are abnormal in operation, automatic detection of clock abnormality and automatic seamless switching of clocks and synchronous time signals can be realized. The switching method can realize seamless switching of the local clock source, can not cause loss of second pulse and can ensure the time keeping precision of time keeping equipment to the maximum extent. The invention adopts the pure hardware circuit to realize the high switching efficiency of the clock, has good real-time performance and can better reduce the clock accuracy loss caused by the clock switching process. The circuit can integrate all clock sources to maintain synchronous pulse per second signals in real time, and ensure that the pulse per second is not lost in the clock switching process.
Drawings
Fig. 1 is a circuit configuration diagram of an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention provides a multi-clock source seamless switching circuit of a timekeeping device and a control method based on a hardware circuit, which can realize smooth and seamless switching among a plurality of clock sources under the condition of no software participation, thereby avoiding the loss of precision of the timekeeping clock caused by switching the clock sources and effectively solving the problem of second pulse loss in the switching process.
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 1, fig. 1 is a circuit configuration diagram of an embodiment of the present invention; the circuit of the embodiment comprises a first clock monitoring module, a second clock monitoring module, a third clock monitoring module, a first timing and time keeping control module, a second timing and time keeping control module, a third timing and time keeping control module and a clock switching and output control module;
the input interfaces corresponding to the first clock monitoring module, the second clock monitoring module and the third clock monitoring module are used for inputting a first clock signal, a second clock signal and a third clock signal, and the output of the input interfaces corresponds to the first clock signal working state and the internal clock signal, the second clock signal working state and the internal clock signal, and the third clock signal working state and the internal clock signal respectively;
the input interface of the first timing and timekeeping control module is used for inputting the output signal of the first clock monitoring module, the external timing second pulse and the standard synchronous time input signal, and the output is connected with the clock switching and output control module;
the input interface of the second timing and time keeping control module is used for inputting the output signal of the first clock monitoring module, the output signal of the second clock monitoring module, the external timing second pulse and the standard synchronous time input signal, and the output is connected with the clock switching and output control module;
the input interface of the third timing and time keeping control module is used for inputting the output signal of the first clock monitoring module, the output signal of the second clock monitoring module, the output signal of the third clock monitoring module, the external timing second pulse and the standard synchronous time input signal, and the output is connected with the clock switching and output control module;
the input interface of the clock switching and output control module is connected with the output signal of the first clock monitoring module, the output signal of the second clock monitoring module, the output signal of the third clock monitoring module, the output signal of the first timing and time keeping control module, the output signal of the second timing and time keeping control module and the output signal of the third timing and time keeping control module, and outputs a second pulse signal and a synchronous time output signal.
The working method of the multi-clock source switching control circuit comprises the following steps:
the clock monitoring module internally comprises a PLL circuit module which is used for carrying out frequency multiplication processing on an input clock signal and monitoring whether an external clock signal works normally or not;
the timing and time keeping control module is used for timing, frequency correction and time keeping control; when external standard second pulse and standard synchronous time are input, synchronous alignment operation is carried out on the internal time and the external standard synchronous time, meanwhile, frequency correction is carried out on an internal clock according to the externally input second pulse, and internal synchronous time generation is realized through the frequency correction clock after frequency correction is finished;
the internal circuit of the module has three clock inputs, namely a first clock signal, a second clock signal and a third clock signal, and one of the three clocks is used as a local clock. The situation in which its operation is configured according to different clock inputs is divided into 3 cases: (1) Accessing a first clock signal, wherein the first clock signal is used as a local clock; (2) Accessing a first clock signal and a second clock signal, wherein the second clock signal is used as a local clock; (3) And accessing a first clock signal, a second clock signal and a third clock signal, wherein the third clock signal is used as a local clock. The three operating conditions correspond to the first, second and third timing and timekeeping control modules of fig. 1, respectively.
When the first clock signal is accessed and used as a local clock, the first timing and time keeping control module only has one clock to work: a first clock signal; under the drive of a first clock signal, if an external standard second pulse and a standard synchronous time are input, synchronous alignment operation is carried out on the internal time and the external standard synchronous time, meanwhile, the internal clock is subjected to frequency correction according to the externally input second pulse, and the internal synchronous time is generated through the frequency correction clock after the frequency correction is finished; otherwise, executing a time keeping function according to the internally locked synchronization time;
when the first clock signal and the second clock signal are accessed, the second clock signal is used as a local clock for timing, and the second timing and time keeping control module works with two clocks: a first clock signal and a second clock signal. The internal core circuit is driven by a second clock signal, when external standard second pulses and standard synchronous time are input, the internal time and the external standard synchronous time are synchronously aligned, meanwhile, the internal clock is subjected to frequency correction according to the second pulses input from the outside, and the internal synchronous time is generated through the frequency correction clock after the frequency correction is finished; when no external standard second pulse and standard synchronous time are input, the first clock signal is used as a standard clock source when the first clock signal input works normally, the frequency of the internal second clock signal is calibrated, and meanwhile, the internal synchronous time generation is realized through the frequency calibration clock. When no external standard second pulse and standard synchronous time are input and the first clock signal works abnormally, the time keeping function is executed under the drive of the second clock signal according to the internally locked synchronous time.
When the first clock signal, the second clock signal and the third clock signal are accessed, the third clock signal is used as a local clock for timing, and the third timing and time keeping control module works with 3 clocks: the first clock signal, the second clock signal and the third clock signal are driven by the third clock signal, when external standard second pulse and standard synchronous time are input, synchronous alignment operation is carried out on the internal time and the external standard synchronous time, meanwhile, frequency correction is carried out on the internal clock according to the externally input second pulse, and internal synchronous time generation is realized through the frequency correction clock after the frequency correction is finished; when no external standard second pulse and standard synchronous time are input and the first clock signal input works normally, the module takes the first clock signal as a standard clock source to calibrate the frequency of an internal third clock signal and simultaneously realizes the generation of internal synchronous time through a frequency calibration clock; when no external standard second pulse and standard synchronous time are input, the first clock signal works abnormally, and the second clock signal works normally, the second clock signal is used as a standard clock source to calibrate the frequency of the internal third clock signal, and meanwhile, the internal synchronous time is generated through a frequency calibration clock; when no external standard second pulse and standard synchronous time are input, the first clock signal and the second clock signal work abnormally, and according to the internally locked synchronous time, a time keeping function is executed under the drive of the third clock signal.
And the clock switching and outputting control module is used for comprehensively processing the second pulse and the standard synchronous time output by the first timing and time keeping control module, the second timing and time keeping control module and the third timing and time keeping control module, and finally outputting one second pulse and one standard synchronous time.
The clock switching and output control module uses a three-input logic or process to combine the second pulses generated by the three time keeping control modules to generate a second pulse pps_out, i.e. the interface signal 18, so that it can be ensured that any one of the first clock signal, the second clock signal and the third clock signal works normally to output a high-precision synchronous second pulse signal. The method comprises the steps that a state machine is used in a module to periodically detect states of three clocks, when rising edges of PPS_OUT signals are detected each time, the three clocks are detected, and if the working state of a first clock signal is normal, synchronous time information input by a first timing and time keeping control module is latched; if the working state of the first clock signal is abnormal and the working state of the second clock signal is normal, the synchronous time information input by the second timing and time keeping control module is latched; if the working states of the first clock signal and the second clock signal are abnormal, and the working state of the third clock signal is normal, the synchronous time information input by the third clock signal is latched; after the synchronous time information is latched, the latched synchronous time information is used as a final synchronous time information output signal to be output through the second interface.
According to the functional structure, the logic design of the controller is described by using the Verilog HDL language, and the logic design is applied to the development of a certain time keeping device, and the function of the time keeping device is tested. The test results show that the invention has good feasibility and the performance meets the expectations.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (6)
1. A multi-clock source seamless switching circuit of high-precision time keeping equipment is characterized by comprising N clock monitoring modules, N time correcting and time keeping control modules and a clock switching and output control module;
the clock monitoring module is used for performing frequency multiplication processing on an input clock signal and monitoring whether an external clock signal is normal or not;
the timing and time keeping control module is used for executing synchronous alignment operation on the internal time and the external standard synchronous time when external standard second pulse and standard synchronous time are input under the drive of a local clock signal, and simultaneously performing frequency correction on the internal clock according to the externally input second pulse, and realizing the generation of the standard synchronous time through the frequency correction clock after the frequency correction is completed;
if no external standard second pulse and standard synchronization time are input and other external clock signals work abnormally, executing a time keeping function according to the internally locked synchronization time;
if no external standard second pulse and standard synchronous time are input and one of other external clock signals works normally, taking the clock signal which works normally as a standard clock source, performing frequency correction on the internal clock, and simultaneously realizing the generation of the standard synchronous time through the frequency correction clock;
the clock switching and outputting control module is used for processing the second pulse and the standard synchronous time output by the timing and time keeping control module and outputting a synchronous second pulse and a standard synchronous time;
n is a positive integer greater than or equal to 2.
2. The multi-clock source seamless switching circuit of the high-precision time keeping device according to claim 1, wherein the clock switching and outputting control module is used for combining the second pulses generated by the N time correction and time keeping control modules to generate a synchronous second pulse;
the clock switching and outputting control module is used for periodically detecting the state of the clock, detecting clock signals when synchronizing the rising edge of the second pulse, latching the synchronous time information input by the corresponding timing and time keeping control module with the normal working state of the clock based on the detection result, and outputting the latched synchronous time information as the final synchronous time.
3. The multi-clock source seamless switching circuit of the high precision time keeping device according to claim 2, wherein the clock switching and output control module is used for periodically detecting the state of the clock based on a state machine.
4. The multi-clock source seamless switching circuit of the high precision time keeping apparatus of claim 2 wherein the clock switching and output control module generates a synchronized second pulse based on a N-input logic or process combining the second pulses generated by the N timing/time keeping control modules.
5. A switching method of a multi-clock source seamless switching circuit based on the high-precision time keeping device according to any one of claims 1 to 4, characterized in that:
the clock monitoring module carries out frequency multiplication processing on an input clock signal and monitors whether an external clock signal is normal or not;
the timing and time keeping control module is driven by a local clock signal, when external standard second pulses and standard synchronous time are input, the internal time and the external standard synchronous time are subjected to synchronous alignment operation, meanwhile, the internal clock is subjected to frequency correction according to the second pulses input from the outside, and standard synchronous time is generated through the frequency correction clock after the frequency correction is completed;
if no external standard second pulse and standard synchronization time are input and other external clock signals work abnormally, executing a time keeping function according to the internally locked synchronization time;
if no external standard second pulse and standard synchronous time are input and one of other external clock signals works normally, taking the clock signal which works normally as a standard clock source, performing frequency correction on the internal clock, and simultaneously realizing the generation of the standard synchronous time through the frequency correction clock;
the clock switching and outputting control module processes the second pulse and the standard synchronous time output by the timing and time keeping control module and outputs a synchronous second pulse and a standard synchronous time;
n is a positive integer greater than or equal to 2.
6. The switching method of the multi-clock source seamless switching circuit based on the high-precision time keeping device according to claim 5, which is characterized in that:
the clock switching and outputting control module synthesizes the second pulses generated by the N timing and time keeping control modules to generate a synchronous second pulse;
the clock switching and outputting control module is used for periodically detecting the state of the clock, detecting a clock signal when the rising edge of the second pulse is synchronized, latching the synchronous time information input by the corresponding timing and time keeping control module with the normal working state of the clock based on the detection result, and outputting the latched synchronous time information as the final synchronous time.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594190A (en) * | 2008-05-30 | 2009-12-02 | 华为技术有限公司 | Power system time synchronization method, device and electric power system |
| CN101825917A (en) * | 2009-03-05 | 2010-09-08 | 富士通株式会社 | Clock provides method and messaging device |
| CN103442312A (en) * | 2013-09-06 | 2013-12-11 | 国家电网公司 | Intelligent power distribution network time synchronization system and method based on PTN+EPON communication system |
| CN105119677A (en) * | 2015-09-09 | 2015-12-02 | 山东中瑞电气有限公司 | Time source selecting and switching method capable of improving time service output reliability |
| CN107257311A (en) * | 2017-08-09 | 2017-10-17 | 西安微电子技术研究所 | A kind of time triggered communication blended data based on virtual link sends dispatching method |
| CN110059036A (en) * | 2019-04-15 | 2019-07-26 | 西安微电子技术研究所 | More asynchronous interface access control apparatus and method inside a kind of memory bank |
| CN111314011A (en) * | 2020-02-24 | 2020-06-19 | 广东电网有限责任公司 | Tunnel cable partial discharge monitoring multipoint clock synchronization system and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399757B (en) * | 2007-09-25 | 2011-02-02 | 华为技术有限公司 | Method and device for tracing time clock source |
| CN101431795B (en) * | 2008-11-29 | 2012-10-10 | 中兴通讯股份有限公司 | Time synchronization method and apparatus |
| WO2017140363A1 (en) * | 2016-02-18 | 2017-08-24 | Nec Europe Ltd. | Time-guarded flow rule installation |
-
2021
- 2021-01-15 CN CN202110055998.5A patent/CN112886951B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594190A (en) * | 2008-05-30 | 2009-12-02 | 华为技术有限公司 | Power system time synchronization method, device and electric power system |
| CN101825917A (en) * | 2009-03-05 | 2010-09-08 | 富士通株式会社 | Clock provides method and messaging device |
| CN103442312A (en) * | 2013-09-06 | 2013-12-11 | 国家电网公司 | Intelligent power distribution network time synchronization system and method based on PTN+EPON communication system |
| CN105119677A (en) * | 2015-09-09 | 2015-12-02 | 山东中瑞电气有限公司 | Time source selecting and switching method capable of improving time service output reliability |
| CN107257311A (en) * | 2017-08-09 | 2017-10-17 | 西安微电子技术研究所 | A kind of time triggered communication blended data based on virtual link sends dispatching method |
| CN110059036A (en) * | 2019-04-15 | 2019-07-26 | 西安微电子技术研究所 | More asynchronous interface access control apparatus and method inside a kind of memory bank |
| CN111314011A (en) * | 2020-02-24 | 2020-06-19 | 广东电网有限责任公司 | Tunnel cable partial discharge monitoring multipoint clock synchronization system and method |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的TT数据发送调度机制设计及仿真;杨宏志 等;《机械工程与自动化》(第01期);103-104+106 * |
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