CN116027840A

CN116027840A - Adjusting circuit, resistor and electronic equipment

Info

Publication number: CN116027840A
Application number: CN202310142524.3A
Authority: CN
Inventors: 祝晓辉; 陶蕤; 陈盛文; 毛毅; 李广生
Original assignee: Chengdu Mingyi Electronic Technology Co ltd
Current assignee: Chengdu Mingyi Electronic Technology Co ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-04-28
Anticipated expiration: 2043-02-21
Also published as: CN116027840B

Abstract

The invention relates to the technical field of integrated circuit design, in particular to an adjusting circuit, a resistor and electronic equipment; generating an adjusting signal by setting the coupling of the adjusting unit and the grid electrode of the NMOS collective tube; setting a current unit, and generating a second current according to the regulating signal and the first current; the driving unit is arranged, an overdrive voltage signal is generated according to the second current, the NMOS transistor is driven to work in a deep linear region, the NMOS transistor is equivalent to a resistor, the resistance value of the NMOS transistor is regulated according to the control signal and the first current, all characteristics of source resistors are reserved, meanwhile, the resistance values of the same type of resistors are amplified and reduced, and the chip area is greatly saved.

Description

Adjusting circuit, resistor and electronic equipment

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a regulating circuit, a resistor, and an electronic device.

Background

The resistor is a basic device in the integrated circuit, and an analog circuit with different structures and different functions is built together with devices such as a capacitor, an inductor, a MODFET and the like. Adjustable resistors are often used in circuit designs, such as the high pass filter design shown in fig. 1, where R0 and C0 form the basic high pass filter. In the case that the adjustable range of C0 is limited or not adjustable, the function of adjusting the high-pass cut-off frequency can be realized by adjusting R0. Common poly resistors, well resistors, etc. are essentially non-tunable.

Common resistor types in integrated circuits are: well resistance (e.g., N-well resistance, P-well resistance), diffusion resistance (e.g., P-type diffusion resistance, N-type diffusion resistance), and Poly resistance (e.g., P + Poly resistance, N + Poly resistance, P-Poly resistance, N-Poly resistance). Different doping types and doping concentrations can obtain different temperature coefficients, different voltage coefficients and different resistance types of the block resistance values. The diffusion resistor and the Poly resistor can be matched with a silicon, namely, a layer of metal such as titanium is deposited on the surface of the polysilicon to form metal silicide, so that the square resistance of the resistor is obviously reduced.

In the circuit design stage, the above-mentioned various types of resistors are often used to meet the requirements of different temperature coefficients and voltage coefficients. A particularly large resistance is sometimes used, such as a 1pF MIM capacitor (metal-insulator-metal capacitor) in the first order high pass filter design of fig. 1, which requires a 1 mega ohm resistor to achieve a 159KHz low pass bandwidth. In order to realize the voltage coefficient with the bandwidth as small as possible along with the voltage change and the temperature coefficient with the temperature change as small as possible, a P+ doped non-silicon carbide resistor is selected. However, the temperature coefficient, the voltage coefficient and the process angle deviation are relatively large, and accurate control of circuit parameters and small matching errors are difficult to realize. This type of resistor has a square resistance of only a few hundred ohms and requires a large amount of chip area to achieve a resistance on the order of megaohms. It is difficult to implement the high pass filter in case of a limited chip area.

There is also a design need for particularly small resistance values. Such as the reference voltage generation circuit shown in fig. 2. vbg is a reference voltage generated by a bandgap reference circuit, has a small temperature and voltage coefficient, and can be regarded as a precise voltage, in order to realize the following change of vref0 along with the process angle, voltage, temperature and other factors as small as possible, and the resistors R1 and R2 are basically the same type and size. To achieve very small values of vref0, very small values of R2 are required. For a P+ doped non-silicon poly resistor with a square resistance value of hundreds of ohms, the same-size resistor with a plurality of fingers connected in parallel is needed, and the same-size resistor inevitably occupies a large area of a chip. In addition, the two different types of resistors are difficult to track each other and offset deviation, namely matching cannot be achieved in the process of manufacturing.

Disclosure of Invention

Aiming at the problems that a large amount of chip area is required to be occupied in the design of a resistor integrated circuit, the temperature coefficient, the voltage coefficient and the process angle of the resistor are larger, and accurate control of circuit parameters and small matching errors are difficult to realize, the invention provides an adjusting circuit, a resistor and electronic equipment, and an adjusting signal is generated by arranging an adjusting unit to be coupled with the grid electrode of an NMOS collective tube; setting a current unit, and generating a second current according to the regulating signal and the first current; the driving unit is arranged, an overdrive voltage signal is generated according to the second current, the NMOS transistor is driven to work in a deep linear region, the NMOS transistor is equivalent to a resistor, the resistance value of the NMOS transistor is regulated according to the control signal and the first current, all characteristics of source resistors are reserved, meanwhile, the resistance values of the same type of resistors are amplified and reduced, and the chip area is greatly saved.

The invention has the following specific implementation contents:

a regulating circuit is coupled with the grid electrode of an NMOS transistor MN4 and comprises a regulating unit, a current unit and a driving unit; the input end of the adjusting unit inputs a control signal, and the output end is coupled with the controlled end of the current unit; the input end of the current unit inputs a first current, and the output end is coupled with the driving unit; the output end of the driving unit is coupled with the grid electrode of the NMOS transistor MN 4;

an adjusting unit for generating an adjusting signal according to the control signal;

a current unit for generating a second current according to the adjustment signal and the first current;

and the driving unit is used for generating an overdrive voltage signal according to the second current, driving the MOS transistor to work in a deep linear region, enabling the NMOS transistor MN4 to be equivalent to a resistor, and adjusting the resistance value of the NMOS transistor MN4 according to the control signal and the first current.

In order to better realize the invention, the driving unit further comprises a first driving unit, a second driving unit and a third driving unit; the input end of the first driving unit is coupled with the output end of the current unit, and the output end of the first driving unit is coupled with the input end of the second driving unit; the output end of the second driving unit is coupled with the grid electrode of the MOS transistor and the input end of the third driving unit; the output end of the third driving unit is coupled with the ground;

A first driving unit for generating a first voltage signal according to the second current;

a third driving unit for generating a first overdrive voltage signal according to the first voltage signal;

and the second driving unit is used for generating a second overdrive voltage signal according to the first voltage signal, driving the MOS transistor to work in a deep linear region according to the first overdrive voltage signal and the second overdrive voltage signal, and enabling the MOS transistor to be equivalent to a resistor.

In order to better realize the invention, the device further comprises a first current mirror unit;

one end of the first current mirror unit is coupled with the first driving unit, and the other end of the first current mirror unit is coupled with the second driving unit.

In order to better realize the invention, the current unit further comprises a second current mirror unit, a third current mirror unit, a fourth current mirror unit and a fifth current mirror unit;

one end of the second current mirror unit inputs a first current signal, and the other end of the second current mirror unit is coupled with the fourth current mirror unit;

one end of the third current mirror unit is coupled with the input end of the adjusting unit, and the other end of the third current mirror unit is coupled with the second current mirror unit;

one end of the fourth current mirror unit, which is not coupled with the second current mirror unit, is coupled with the fifth current mirror unit;

One end of the fifth current mirror unit, which is not coupled with the fourth current mirror unit, is coupled with the input end of the driving unit.

In order to better implement the invention, further, the adjusting unit comprises N adjusting units; the input ends of the N regulating units are input with control signals, and the output ends of the N regulating units are coupled with the controlled end of the current unit;

the input end of the kth regulating unit of the N regulating units is coupled with a switch swp & ltk & gt and a grounded switch swn & ltk & gt, wherein k is a positive integer which is more than or equal to 2 and less than or equal to N;

the N adjusting units generate N adjusting signals corresponding to the N control signals one by one according to the N control signals.

In order to better implement the present invention, further, the first driving unit includes a resistor R1, an NMOS transistor MN1;

one end of the resistor R1 is coupled with the output end of the current unit, and the other end of the resistor R1 is coupled with the ground;

the gate of the NMOS transistor MN1 is connected between the resistor R1 and the output end of the current unit, the source is connected with the ground, and the drain is coupled with the first current mirror unit.

In order to better implement the present invention, further, the first current mirror unit includes a PMOS transistor MP1, a PMOS transistor MP2;

the gate of the PMOS transistor MP1 is coupled with the gate of the PMOS transistor MP2, and the drain of the PMOS transistor MP1 is coupled with the drain of the NMOS transistor MN1;

The drain of PMOS transistor MP2 is coupled to the second drive unit.

In order to better implement the present invention, further, the second driving unit includes NMOS transistors mn2_1, mn2_2, mn2_3, mn2_4; the third driving unit includes NMOS transistors mn3_1, mn3_2, mn3_3, and mn3_4;

the gate of NMOS transistor Mn2_1 is coupled to the drain of PMOS transistor MP2, the drain of NMOS transistor Mn2_1, the gate of NMOS transistor Mn2_2, the drain of NMOS transistor Mn2_2, the gate of NMOS transistor Mn2_3, the drain of NMOS transistor Mn2_3, the gate of NMOS transistor Mn2_4, the drain of NMOS transistor Mn2_4, and the gate of NMOS transistor MN 4;

the source of NMOS transistor mn2_1 is coupled to the source of NMOS transistor mn2_2, the source of NMOS transistor mn2_3, the source of NMOS transistor mn2_4, the gate of NMOS transistor mn3_1, the drain of NMOS transistor mn3_1, the gate of NMOS transistor mn3_2, the drain of NMOS transistor mn3_2, the gate of NMOS transistor mn3_3, the drain of NMOS transistor mn3_3, the gate of NMOS transistor mn3_4, and the drain of NMOS transistor mn3_4;

the source of NMOS transistor Mn3_1 is coupled to the source of NMOS transistor Mn3_2, the source of NMOS transistor Mn3_3, the source of NMOS transistor Mn3_4, and ground.

In order to better implement the present invention, further, the channel lengths and channel widths of the NMOS transistors MN1, MN2_1, MN2_2, MN2_3, MN2_4, MN3_1, MN3_2, MN3_3, and MN3_4 are equal.

In order to better implement the present invention, further, the second current mirror unit includes a PMOS transistor MP4, a PMOS transistor MP5; the third current mirror unit comprises a PMOS transistor MP3 and a PMOS transistor MP5; the fourth current mirror unit comprises an NMOS transistor MN5 and an NMOS transistor MN6; the fifth current mirror unit comprises a PMOS transistor MP6 and a PMOS transistor MP7;

the gate of the PMOS transistor MP4 inputs the first current and is coupled to the gate of the PMOS transistor MP5, the drain of the PMOS transistor MP4, and the gate of the PMOS transistor MP 3;

the drain electrode of the PMOS transistor MP3 is coupled with the regulating unit;

the drain of the PMOS transistor MP5 is coupled with the output end of the regulating unit, the drain of the NMOS transistor MN5, the grid of the NMOS transistor MN5 and the grid of the NMOS transistor MN6;

the source of NMOS transistor MN5 is coupled to ground;

the drain of NMOS transistor MN6 is coupled to the drain of PMOS transistor MP6, the gate of PMOS transistor MP6 and the gate of PMOS transistor MP7;

The source of NMOS transistor MN6 is coupled to ground;

the drain of PMOS transistor MP7 is coupled to the input of the drive unit.

To better implement the invention, further, the regulating unit comprises N NMOS transistors MN8; n-1 switches swp < N >, N-1 switches swn < N >;

the gate of NMOS transistor Mn8_1 is coupled to the drain of NMOS transistor Mn8_1, the input of switch swp < N > and the drain of PMOS transistor MP 3; the source electrode of the NMOS transistor MN8_1 is connected with the ground terminal;

the drain of NMOS transistor Mn8_N is lapped between the drain of PMOS transistor MP5 and the drain of NMOS transistor MN 5; the grid electrode of the NMOS transistor Mn8_N is coupled with the output end of the switch swp < N > and the input end of the switch swn < N > which is grounded;

the source of NMOS transistor Mn8_N is coupled to ground.

In order to better implement the present invention, further, channel lengths and channel widths of the PMOS transistors MP3, MP4, MP5, MP6, and MP7 are equal; the channel length and channel width of the NMOS transistor MN5 and the NMOS transistor MN6 are equal.

Based on the above mentioned regulating circuit, in order to better realize the present invention, further, a regulating resistor is proposed, comprising the above mentioned regulating circuit and an NMOS transistor MN4; the input end of the regulating circuit inputs a first current and a control signal, and the output end of the regulating circuit is coupled with the grid electrode of the NMOS transistor MN4;

And the adjusting circuit is used for adjusting the resistance value of the NMOS transistor MN4 according to the first current and the control signal.

Based on the above mentioned regulating circuit, in order to better implement the present invention, further, an electronic device is proposed, comprising the above mentioned regulating resistor; and the adjusting resistor is used for adjusting the resistance value of the resistor according to the input first current and the control signal.

The invention has the following beneficial effects:

(1) According to the invention, the NMOS transistor is driven to work in a deep linear region by generating the overdrive voltage signal, the NMOS transistor is equivalent to a resistor, and the resistance value of the NMOS transistor is regulated according to the input control signal and the first current, so that the amplification and the reduction of the resistance value of the same type of resistor are realized while all the characteristics of the source resistor are reserved.

(2) According to the invention, a traditional mode of connecting a plurality of resistors finger in series is not needed in realizing the resistor with a particularly large resistance, and only the size of the input first current is required to be adjusted, and the MOSFET transistor is easy to integrate, so that the chip area is greatly saved.

(3) According to the invention, N adjusting units and N-1 switches are arranged to generate N adjusting signals, so that the adjustment of the resistance from 1 to N is realized, and N-gear adjustment of the resistance is realized.

Drawings

Fig. 1 is a schematic diagram of a first-order high-pass filter circuit according to the present embodiment;

FIG. 2 is a schematic diagram of a reference voltage generating circuit according to the present embodiment;

fig. 3 is a schematic structural diagram of the adjusting circuit according to the present embodiment;

fig. 4 is a schematic diagram of a circuit structure of an adjusting resistor according to the present embodiment;

fig. 5 is a schematic diagram of a circuit structure of a current unit according to the present embodiment.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments, and therefore should not be considered as limiting the scope of protection. All other embodiments, which are obtained by a worker of ordinary skill in the art without creative efforts, are within the protection scope of the present invention based on the embodiments of the present invention.

In the description of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; or may be directly connected, or may be indirectly connected through an intermediate medium, or may be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

Example 1:

the resistor is a basic device in the integrated circuit, and an analog circuit with different structures and different functions is built together with devices such as a capacitor, an inductor, an MODFET and the like.

In the circuit design stage, the above-mentioned various types of resistors are often used to meet the requirements of different temperature coefficients and voltage coefficients. A particularly large resistance is sometimes used, such as a 1pF MIM capacitor (metal-insulator-metal capacitor) in the first order high pass filter design of fig. 1, which requires a 1 mega ohm resistor to achieve a 159KHz low pass bandwidth. In order to realize the voltage coefficient with the bandwidth as small as possible along with the voltage change and the temperature coefficient with the temperature change as small as possible, a P+ doped non-silicon carbide resistor is selected. However, this type of resistor has a square resistance of only a few hundred ohms, and occupies a large amount of chip area to achieve a resistance in the order of megaohms. It is difficult to implement the high pass filter in case of a limited chip area.

There is also a design need for particularly small resistance values. Such as the reference voltage generation circuit shown in fig. 2. vbg is a reference voltage generated by a bandgap reference circuit, has a small temperature and voltage coefficient, and can be regarded as a precise voltage. vref0 is a reference voltage signal as shown in equation (23). In order to achieve a following variation of vref0 with process angle, voltage, temperature, etc. as small as possible, R2 and R3 in principle use the same type of resistance of the same size. To achieve very small values of vref0, very small values of R3 are required. For a P+ doped non-silicon poly resistor with a square resistance value of hundreds of ohms, the same-size resistor with a plurality of fingers connected in parallel is needed, and the same-size resistor inevitably occupies a large area of a chip. In fig. 2, MP9 is a PMOS transistor MP9, MP10 is a PMOS transistor MP10, MN7 is an NMOS transistor MN7, C1 is a capacitor C1, and OPAMP0 is an operational amplifier OPAMP0.

（21）

Where ib0 is a current flowing through the resistor R2, and vbg is a bandgap reference voltage.

（22）

（23）

vref0 is a reference voltage, ib1 is a current flowing through resistor R3, and x is a multiplication symbol, which indicates that current ib1 multiplies resistor R3.

Conventionally, in order to realize a resistor with a large resistance, a P-poly resistor of non-silicon is selected. The low doping concentration and the silicon barrier layer can realize a block resistance of about 1k ohm. However, the temperature coefficient, the voltage coefficient and the process angle deviation are relatively large, and accurate control of circuit parameters and small matching errors are difficult to realize.

Conventionally, in order to realize a resistor with a small resistance value, a p+ or n+ heavily doped diffusion resistor is selected. The high doping concentration and the silicon oxide barrier layer can realize the block resistance of about tens of ohms. However, the temperature coefficient, the voltage coefficient and the process angle deviation are also larger, and accurate control of circuit parameters and small matching errors are difficult to realize. A metal resistor may also be used. Block resistance in milliohm level. However, the resistance is greatly deviated by the process manufacturing, and the etching error of metal can introduce resistance deviation. And matching with other types of resistors is difficult to achieve. For example, in fig. 2, if a p+ doped non-silicon poly resistor is selected as R2 and a metal resistor is selected as R3, the two different types of resistors are difficult to track each other and offset in the process of manufacturing, i.e. matching cannot be realized.

The embodiment proposes a regulating circuit, as shown in fig. 3, coupled to the gate of the NMOS transistor MN4, including a regulating unit, a current unit, and a driving unit; the input end of the adjusting unit inputs a control signal, and the output end is coupled with the controlled end of the current unit; the input end of the current unit inputs a first current, and the output end is coupled with the driving unit; the output end of the driving unit is coupled with the grid electrode of the NMOS transistor MN 4;

Working principle: in the embodiment, the adjusting unit is arranged to be coupled with the grid electrode of the NMOS collective tube to generate an adjusting signal; setting a current unit, and generating a second current according to the regulating signal and the first current; the driving unit is arranged, an overdrive voltage signal is generated according to the second current, the NMOS transistor is driven to work in a deep linear region, the NMOS transistor is equivalent to a resistor, the resistance value of the NMOS transistor is regulated according to the control signal and the first current, all characteristics of source resistors are reserved, meanwhile, the resistance values of the same type of resistors are amplified and reduced, and the chip area is greatly saved.

Example 2:

in this embodiment, on the basis of embodiment 1 described above, as shown in fig. 3, the driving unit includes a first driving unit, a second driving unit, and a third driving unit; the input end of the first driving unit is coupled with the output end of the current unit, and the output end of the first driving unit is coupled with the input end of the second driving unit; the output end of the second driving unit is coupled with the grid electrode of the MOS transistor and the input end of the third driving unit; the output end of the third driving unit is coupled with the ground;

Further, the first current mirror unit is also included;

Other portions of this embodiment are the same as those of embodiment 1 described above, and thus will not be described again.

Example 3:

in this embodiment, on the basis of any one of the above embodiments 1 to 2, N adjusting units are provided, the input ends of the N adjusting units input control signals, and the output ends of the N adjusting units are coupled with the controlled end of the current unit;

Other portions of this embodiment are the same as any of embodiments 1 to 2, and thus will not be described again.

Example 4:

in this embodiment, a specific configuration of the regulator circuit is described based on any one of embodiments 1 to 3 described above, as shown in fig. 4 and 5.

As shown in fig. 4, the first driving unit includes a resistor R1, an NMOS transistor MN1;

The first current mirror unit comprises a PMOS transistor MP1 and a PMOS transistor MP2;

the gate of the PMOS transistor MP1 is coupled with the gate of the PMOS transistor MP2, and the drain of the PMOS transistor MP1 is coupled with the drain of the NMOS transistor MN 1;

the drain of PMOS transistor MP2 is coupled to the second drive unit.

The second driving unit includes NMOS transistors mn2_1, mn2_2, mn2_3, and mn2_4; the third driving unit includes NMOS transistors mn3_1, mn3_2, mn3_3, and mn3_4;

The channel lengths and channel widths of the NMOS transistors MN1, MN2_1, MN2_2, MN2_3, MN2_4, MN3_1, MN3_2, MN3_3, and MN3_4 are equal.

The second current mirror unit comprises a PMOS transistor MP4 and a PMOS transistor MP5; the third current mirror unit comprises a PMOS transistor MP3 and a PMOS transistor MP5; the fourth current mirror unit comprises an NMOS transistor MN5 and an NMOS transistor MN6; the fifth current mirror unit comprises a PMOS transistor MP6 and a PMOS transistor MP7;

the source of NMOS transistor MN5 is coupled to ground;

The source of NMOS transistor MN6 is coupled to ground;

the drain of PMOS transistor MP7 is coupled to the input of the drive unit.

The regulating unit comprises N NMOS transistors MN8; n-1 switches swp < N >, N-1 switches swn < N >;

the source of NMOS transistor Mn8_N is coupled to ground.

The channel lengths and channel widths of the PMOS transistors MP3, MP4, MP5, MP6 and MP7 are equal; the channel length and channel width of the NMOS transistor MN5 and the NMOS transistor MN6 are equal.

Other portions of this embodiment are the same as any of embodiments 1 to 3, and thus will not be described again.

Example 5:

this embodiment is described in detail with reference to one specific embodiment, as shown in fig. 4 and 5, based on any one of embodiments 1 to 4.

The embodiment provides an adjusting circuit, which adopts a MOSFET transistor to realize resistance, and based on any type of resistance, the resistance of the same type of resistance is amplified and reduced. All the characteristics of the source resistance (characteristics with temperature variation, resistance shift with process angle, etc.) can be preserved. And because the MOSFET transistor is easy to integrate, the method is very suitable for occasions needing to occupy a large chip area to realize a certain resistance.

As shown in fig. 4, which is a schematic circuit diagram of the regulating circuit, PMOS transistors MP1 and MP2 form 1:1 in order to equalize the currents flowing through MP1 and MP2, as shown in equation (2).

（2）

i1 is a current flowing through the PMOS transistor MP1, and i2 is a current flowing through the PMOS transistor MP 2.

The NMOS transistors MN1, MN2_1-MN2_4, MN3_1-MN3_4 and MN4 have the same size, the channel width is W, and the channel length is L. Compared with MN1, the four MOS transistors MN2_1-MN2_4 have the same channel current as MN1 and have 4 times of W/L ratio, so that MN2_1-MN2_4 have half of overdrive voltage of MN 1. As shown in formula (5).

（5）

Wherein, vgs2 is the gate-source voltage of Mn2_1~ Mn2_4, i2 is the current flowing through PMOS transistor MP2, W is the channel width, L is the channel length, μn is the electron mobility of nmos tube, cox is the oxide layer capacitance, and vth is the threshold voltage of MOS tube.

The overdrive voltage of the MOSFET is referred to as vg-vth, the voltage difference. Similarly, MN3_1-MN3_4 also has half of the overdrive voltage of MN1, as shown in equation (6).

（6）/>

Wherein, vgs3 is the gate-source voltage of M3_1-M3_4, i2 is the current flowing through the PMOS transistor MP2, W is the channel width, L is the channel length, μn is the electron mobility of the nmos transistor, cox is the oxide layer capacitance, and vth is the threshold voltage of the MOS transistor.

The gate voltage of MN1 is generated from an adjustable current source IDAC flowing through a fixed resistor R1, and the gate voltage vgs1 is represented by formula (3).

（3）

Where vgs1 is the gate voltage of MN1 and IDAC is the output adjustable current of the adjustable current source.

The gate voltage vgs1 of MN1 and the channel current i1 have a relational expression represented by expression (4).

（4）

Wherein, vgs1 is the gate voltage of MN1, vth is the threshold voltage of the MOS transistor, i1 is the current flowing through PMOS transistor MP1, W is the channel width, L is the channel length, μn is the electron mobility of the nmos transistor, cox is the oxide layer capacitance, and vth is the threshold voltage of the MOS transistor.

The gate-source voltage vgs2 of Mn2_1 to Mn2_4 and the channel current i2 have a relational expression represented by expression (5).

The gate-source voltage vgs3 of Mn3_1 to Mn3_4 and the channel current i2 have a relational expression represented by expression (6).

The gate-source voltage vgs4 of MN4 is shown in equation (7).

（7）

Wherein, vgs4 is the gate-source voltage of MN4, vgs2 is the gate-source voltage of mn2_1 to mn2_4, vgs3 is the gate-source voltage of mn3_1 to mn3_4, vth is the threshold voltage of the MOS transistor, i1 is the current flowing through PMOS transistor MP1, W is the channel width, L is the channel length, μn is the electron mobility of the nmos transistor, cox is the oxide layer capacitance, vth is the threshold voltage of the MOS transistor.

The two half overdrive voltages are superimposed to make the same overdrive voltage as MN1, i.e. the rooted part can be matched with MN 1. The final objective is to obtain an expression of vgs4=vgs1+vth as shown in formula (8), and to obtain formula (8) from formulas (1), (2) and (7).

（1）

Wherein Ron is the on-resistance of the MOS tube, μn is the electron mobility of the nmos tube, cox is the oxide layer capacitance, vth is the threshold voltage of the MOS tube, W is the channel width, L is the channel length, vth is the threshold voltage of the MOS tube, and vgs is the gate voltage.

（8）

Wherein, vgs4 is the gate-source voltage of MN4, vgs2 is the gate-source voltage of Mn2_1 to Mn2_4, vgs3 is the gate-source voltage of Mn3_1 to Mn3_4, and vth is the threshold voltage of the MOS transistor.

MN4, by operating in the deep linear region, behaves as a resistor Radj. According to equation (1), the resistance Radj is shown in equation (9).

（9）/>

Where Radj is the on-resistance of MN 4.

vgs4=vgs1+vth, vth is used to cancel out the vth term in the denominator in expression (1). The MOS resistor obtained in this way is independent of the threshold voltage of the MOSFET, does not generate great fluctuation along with the manufacturing process, and is relatively stable. After cancellation of the vth term, the MOS resistor Ron is only related to Vgs 1. And then the vgs1 is made into an adjustable voltage, so that a relatively stable voltage-controlled resistor can be realized.

The current source IDAC shown in fig. 5 may be built according to the circuit shown in fig. 4, with N-order adjustable, where N is an integer greater than or equal to 2. PMOSMP 3-PMOSMP 7 have the same size: wp and Lp. I0 is a fixed bias current. MP3, MP4, and MP5 have the same width, length dimensions, composition 1:1:1, the channel currents flowing through MP3, MP4 and MP5 are the same, I0.MN5 and MN6 are also of the same width, length dimensions, composition 1:1, the channel currents flowing through MN5 and MN6 are the same. MP6 and MP7 are also of the same width, length dimensions, composition 1:1, the channel currents flowing through MP6 and MP7 are the same.

NMOSMN8_1-NMOSMN8_N form a group of current mirrors, i3 < j > is channel current flowing through Mn8_j, and j is an integer greater than or equal to 2 and less than or equal to N. The switches swp & ltj & gt and swn & ltj & gt are connected to the grid of the MN8_j to determine whether the MN8_j is conducted or not. If swp < j > closed and swn < j > open, mn8_j is on.

If swp < j > open and swn < j > closed, mn8_j is not conductive.

enp _sw < j > is swp < j >. enp _sw < j > = 1, swp < j > switch closed; enp _sw < j > =0, swp < j > switch open.

enn _sw < j > is swn < j >. enn _sw < j > = 1, swn < j > switch closed; enn _sw < j > = 0, swn < j > switch open.

The switch closure logic is shown in table 1. enn _sw < j > is a logical inversion signal enp _sw < j > and j is an integer of 2 or more and N or less. Radj has N total adjustable gears, N being an integer greater than or equal to 2.

1 st gear: enp _sw < j > (j=from 2 to N) =0, swp < j > (j=from 2 to N) switch open; enn _sw < j > (j=from 2 to N) =1, and swn < j > (j=from 2 to N) switch closure. Mn8_j (j=from 2 to N) is non-conductive.

Gear 2: enp _sw < j > (j=from 3 to N) =0, swp < j > (j=from 3 to N) switch open. enp _sw < j > (j=2) =1, swp < j > (j=2) switch closed; enn _sw < j > (j=from 3 to N) =1, and swn < j > (j=from 3 to N) switch closure. enn _sw < j > (j=2) =0, and the swn < j > (j=2) switch is turned off. Mn8_j (j=from 3 to N) is non-conductive. Mn8_j (j=2) is on.

The kth gear: k is an integer of 2 or more and N or less. enp _sw < j > (j=from k+1 to N) =0, swp < j > (j=from k+1 to N) switch is turned off. enp _sw < j > (j=from 2 to k) =1, swp < j > (j=from 2 to k) switch closed; enn _sw < j > (j=from k+1 to N) =1, and swn < j > (j=from k+1 to N) switch closure. enn _sw < j > (j=from 2 to k) =0, and swn < j > (j=from 2 to k) switch is turned off. Mn8_j (j=from k+1 to N) is non-conductive. Mn8_j (j=from 2 to k) is on.

Last gear: enp _sw < j > (j=from 2 to N) =1, swp < j > (j=from 2 to N) switch closed; enn _sw < j > (j=from 2 to N) =0, and swn < j > (j=from 2 to N) switch is turned off. Mn8_j (j=from 2 to N) is on.

Table 1 switch closure logic table

/>

i3_sum is the sum of MN8_N channel currents of MN8_2 to MN8_N, and is shown in the formula (10):

（10）

in combination with the switch closure logic table, the non-conducting NMOS channel current is 0. In the first gear of Radj, equation (10) may be expressed as equation (11):

（11）

in the kth gear of Radj (k is an integer of 2 or more and N or less), the expression (10) can be expressed by the expression (12):

（12）

mn8_1 has a W/L dimension, the channel width of Mnj (j is an integer of 2 or more and N or less) is W, and the channel length is j (j-1) L, which is the same as Mn8_1, and j (j-1) times the channel length of Mn8_1. Therefore, the channel current expression when mn8_j is on is as shown in formula (13):

（13）

Wherein I0 is a fixed bias current.

According to equation (13), in the kth gear of Radj (k is an integer of 2 or more and N or less), equation (12) can be expressed as:

（14）

NMOSMN 5-NMOSMN 6 are a group of 1:1 current mirrors, and channel currents of i4 and i5 respectively flow as shown in formula (15).

（15）

PMOSMP 6-PMOSMP 7 are a set of 1:1 current mirrors, channel currents respectively flowing through i5 and IDAC, which are shown in formula (16).

（16）

Substituting equation (14) into equation (16) yields an expression of IDAC:

（17）

substituting formula (11) into formula (16) yields an expression of IDAC:

（18）

combining formula (17) and formula (18) to obtain an expression of IDAC:

（19）

substituting formula (19) into the expression of Radj:

（20）

as can be seen from the k-th gear expression of the Radj, the Radj increases linearly from 1 to N, N gears are adjustable, and the resistance value is from

To->

The gear steps are increased one by one.

Other portions of this embodiment are the same as any of embodiments 1 to 4, and thus will not be described again.

Example 6:

the present embodiment proposes a regulating resistor including the regulating circuit and the NMOS transistor MN4 described above on the basis of any one of the above embodiments 1 to 5; the input end of the regulating circuit inputs a first current and a control signal, and the output end of the regulating circuit is coupled with the grid electrode of the NMOS transistor MN4;

Further, an electronic device is provided, which comprises the adjusting resistor; and the adjusting resistor is used for adjusting the resistance value of the resistor according to the input first current and the control signal.

The embodiment also provides a chip system. The system-on-chip includes at least one processor and at least one interface circuit. The at least one processor and the at least one interface circuit may be interconnected by wires. The processor is configured to support the system-on-a-chip to perform the functions or steps of the method embodiments described above, and at least one interface circuit may be configured to receive signals from other devices (e.g., memory) or to transmit signals to other devices (e.g., communication interfaces). The system-on-chip may include a chip, and may also include other discrete devices.

The present embodiment also provides a computer-readable storage medium comprising instructions which, when executed on the above-described electronic device, cause the above-described electronic device to perform the various functions or steps of the above-described second aspect.

The processor referred to in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processor unit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microprocessor (micro controller unit, MCU), a programmable processor (programmable logic device, PLD) or other integrated chip.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules or components may be combined or integrated into another device, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.

The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated in one device, or each module may exist alone physically, or two or more modules may be integrated in one device.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, a website, computer, server, or data center via a wired (e.g., coaxial cable, fiber optic, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An adjusting circuit is characterized by being coupled with the grid electrode of an NMOS transistor MN4 and comprising an adjusting unit, a current unit and a driving unit; the input end of the regulating unit inputs a control signal, and the output end of the regulating unit is coupled with the controlled end of the current unit; the input end of the current unit inputs a first current, and the output end of the current unit is coupled with the driving unit; the output end of the driving unit is coupled with the grid electrode of the NMOS transistor MN 4;

the adjusting unit is used for generating an adjusting signal according to the control signal;

the current unit is used for generating a second current according to the regulating signal and the first current;

the driving unit is configured to generate an overdrive voltage signal according to the second current, drive the MOS transistor to operate in a deep linear region, equivalent the NMOS transistor MN4 to a resistor, and adjust a resistance value of the NMOS transistor MN4 according to the control signal and the first current.

2. An adjusting circuit as claimed in claim 1, wherein the driving unit comprises a first driving unit, a second driving unit, and a third driving unit; the input end of the first driving unit is coupled with the output end of the current unit, and the output end of the first driving unit is coupled with the input end of the second driving unit; the output end of the second driving unit is coupled with the grid electrode of the MOS transistor and the input end of the third driving unit; the output end of the third driving unit is coupled with the ground;

the first driving unit is used for generating a first voltage signal according to the second current;

the third driving unit is used for generating a first overdrive voltage signal according to the first voltage signal;

the second driving unit is configured to generate a second overdrive voltage signal according to the first voltage signal, and drive the MOS transistor to operate in a deep linear region according to the first overdrive voltage signal and the second overdrive voltage signal, so that the MOS transistor is equivalent to a resistor.

3. A regulating circuit as claimed in claim 2, further comprising a first current mirror unit;

4. A regulating circuit according to claim 3, wherein the current cells comprise a second current mirror cell, a third current mirror cell, a fourth current mirror cell, a fifth current mirror cell;

one end of the third current mirror unit is coupled with the input end of the regulating unit, and the other end of the third current mirror unit is coupled with the second current mirror unit;

5. An adjusting circuit as claimed in claim 4, wherein said adjusting unit comprises N of said adjusting units; the input ends of the N regulating units are input with control signals, and the output ends of the N regulating units are coupled with the controlled ends of the current units;

6. A regulating circuit as claimed in claim 3, characterized in that the first driving unit comprises a resistor R1, an NMOS transistor MN1;

one end of the resistor R1 is coupled with the output end of the current unit, and the other end of the resistor R1 is coupled with ground;

the gate of the NMOS transistor MN1 is lapped between the resistor R1 and the output end of the current unit, the source is connected with the ground, and the drain is coupled with the first current mirror unit.

7. The regulation circuit of claim 6, wherein the first current mirror unit includes a PMOS transistor MP1, a PMOS transistor MP2;

the drain of the PMOS transistor MP2 is coupled with the second driving unit.

8. The regulation circuit of claim 7, wherein the second drive unit includes NMOS transistors Mn2_1, mn2_2, mn2_3, mn2_4; the third driving unit comprises NMOS transistors Mn3_1, mn3_2, mn3_3 and Mn3_4;

The gate of the NMOS transistor mn2_1 is coupled to the drain of the PMOS transistor MP2, the drain of the NMOS transistor mn2_1, the gate of the NMOS transistor mn2_2, the drain of the NMOS transistor mn2_2, the gate of the NMOS transistor mn2_3, the drain of the NMOS transistor mn2_3, the gate of the NMOS transistor mn2_4, the drain of the NMOS transistor mn2_4, and the gate of the NMOS transistor MN 4;

the source of the NMOS transistor mn2_1 is coupled to the source of the NMOS transistor mn2_2, the source of the NMOS transistor mn2_3, the source of the NMOS transistor mn2_4, the gate of the NMOS transistor mn3_1, the drain of the NMOS transistor mn3_1, the gate of the NMOS transistor mn3_2, the drain of the NMOS transistor mn3_2, the gate of the NMOS transistor mn3_3, the drain of the NMOS transistor mn3_3, the gate of the NMOS transistor mn3_4, and the drain of the NMOS transistor mn3_4;

the source of the NMOS transistor Mn3_1 is coupled with the source of the NMOS transistor Mn3_2, the source of the NMOS transistor Mn3_3, the source of the NMOS transistor Mn3_4, and ground.

9. The regulation circuit of claim 8 wherein the channel lengths and channel widths of the NMOS transistor MN1, the NMOS transistor mn2_1, the NMOS transistor mn2_2, the NMOS transistor mn2_3, the NMOS transistor mn2_4, the NMOS transistor mn3_1, the NMOS transistor mn3_2, the NMOS transistor mn3_3, and the NMOS transistor mn3_4 are equal.

10. The regulation circuit of claim 5, wherein the second current mirror unit includes a PMOS transistor MP4, a PMOS transistor MP5; the third current mirror unit comprises a PMOS transistor MP3 and a PMOS transistor MP5; the fourth current mirror unit comprises an NMOS transistor MN5 and an NMOS transistor MN6; the fifth current mirror unit comprises a PMOS transistor MP6 and a PMOS transistor MP7;

the gate of the PMOS transistor MP4 inputs a first current and is coupled with the gate of the PMOS transistor MP5, the drain of the PMOS transistor MP4, and the gate of the PMOS transistor MP 3;

the drain electrode of the PMOS transistor MP5 is coupled with the output end of the regulating unit, the drain electrode of the NMOS transistor MN5, the grid electrode of the NMOS transistor MN5 and the grid electrode of the NMOS transistor MN6;

the source of the NMOS transistor MN5 is coupled with the ground terminal;

the drain of the NMOS transistor MN6 is coupled with the drain of the PMOS transistor MP6, the gate of the PMOS transistor MP6 and the gate of the PMOS transistor MP7;

the source of the NMOS transistor MN6 is coupled with the ground terminal;

the drain of the PMOS transistor MP7 is coupled to the input of the drive unit.

11. A regulating circuit as claimed in claim 10, characterized in that the regulating unit comprises N NMOS transistors MN8; n-1 switches swp < N >, N-1 switches swn < N >;

the drain of NMOS transistor Mn8_N is lapped between the drain of PMOS transistor MP5 and the drain of NMOS transistor MN 5; the gate of the NMOS transistor M8_N is coupled to the output of the switch swp < N > and the input of the grounded switch swn < N >;

the source of the NMOS transistor Mn8_N is coupled to ground.

12. The regulation circuit of claim 10 wherein the channel lengths and channel widths of the PMOS transistors MP3, MP4, MP5, MP6, and MP7 are equal; the channel length and the channel width of the NMOS transistor MN5 and the NMOS transistor MN6 are equal.

13. A regulating resistor comprising a regulating circuit according to any of claims 1-12 and an NMOS transistor MN4; the input end of the regulating circuit inputs a first current and a control signal, and the output end of the regulating circuit is coupled with the grid electrode of the NMOS transistor MN4;

The adjusting circuit is used for adjusting the resistance value of the NMOS transistor MN4 according to the first current and the control signal.

14. An electronic device comprising the tuning resistor of claim 13; the adjusting resistor is used for adjusting the resistance value of the resistor according to the input first current and the control signal.