CN107368143A - A kind of reference voltage source of low-power consumption - Google Patents
A kind of reference voltage source of low-power consumption Download PDFInfo
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Abstract
The invention belongs to technical field of integrated circuits, and in particular to a kind of reference voltage source of low-power consumption.The present invention is designed using non-resistance, is influenceed by voltage x current and voltage-current converter circuit with eliminating the temperature of metal-oxide-semiconductor；Reach high-order temperature compensated effect while positive temperature coefficient compensation is carried out, it is high-order temperature compensated to carry out to avoid designing other circuits, saves chip area and power consumption；Meanwhile although circuit employs cascode structure and improves PSRR, its supply voltage can still reach 0.9V, and this further reduces power consumption, can reach nanowatt rank.In summary, the present invention realizes low-power consumption, and chip area is small, and has high-order temperature compensated reference voltage source.
Description
Technical field
It is more particularly to a kind of low the invention belongs to technical field of integrated circuits, the specially reference circuit in integrated circuit
The reference voltage source of power consumption.
Background technology
For reference voltage source as a module essential in integrated circuit, it can be other simulations, digital module
There is provided not with temperature, supply voltage, process reform accurately output signal, data converter, linear voltage regulator, switch electricity
Suffer from being widely applied in source and digital storage.With the development that society is with rapid changepl. never-ending changes and improvements, portable set is in order to more
The good market competitiveness under different temperature environments, has stable power supply, it is necessary to lower power consumption and longer life-span
Voltage, therefore a kind of low-power consumption, the reference voltage source of nearly zero-temperature coefficient are designed as inevitable.
In traditional electric current modular form reference circuit design, using the negative of transistor base-emitter voltage VBE
Temperature coefficient characteristics produce the electric current of negative temperature coefficient, and the difference of transistor base-emitter voltage of two different areas produces
With the positively related voltage of temperature, by resistance be converted into the positively related electric current of temperature, the related electric current of positive and negative temperature is added
Obtain the electric current of nearly zero-temperature coefficient.But because transistor base-emitter voltage VBE temperature coefficient is approximately -2mV/
DEG C, thermoelectrical potential VT temperature coefficient is approximately 0.087mV/ DEG C, and it is about 23 that the ratio between resistance, which multiplies in triode area ratio, and this is not
The evitable area for increasing domain, and mismatch between resistance influences the precision of output voltage, the design method is only in addition
Single order temperature-compensating is carried out, under different temperature ranges, output reference voltage variation with temperature is bigger.Therefore design
Going out a kind of high-order temperature compensated reference circuit of low-power consumption turns into popular domain.
To reach low power capabilities, it is necessary to which metal-oxide-semiconductor is operated in into sub-threshold region, to prevent metal-oxide-semiconductor to be operated in sub-threshold region
With the border of saturation region, the gate source voltage of metal-oxide-semiconductor should be less than threshold voltage, and drain-source voltage is at least above 0.1V；It is high to reach
Rank compensation effect, most of past research is all the extra circuit of increase, and this increases not only circuit power consumption to also increase version
The area of pictural surface, this proposes a new challenge to researcher.
The content of the invention
Problem or deficiency be present for above-mentioned, to realize low-power consumption, chip area is small, has high-order temperature compensated benchmark
Voltage source, the invention provides a kind of reference voltage source of low-power consumption.
The reference voltage source of the low-power consumption, including biasing circuit, PTAT current generation circuit, CTAT current generation circuit,
High temperature adjustment circuit, electric current summation and current-voltage conversion circuit.
Biasing circuit produces bias voltage and provides biasing for PTAT current generation circuit.
PTAT current generation circuit is used for producing and the positively related linear current of temperature, the electric current by weighting thermoelectrical potential VT
Electric current summing circuit is mirrored to by cascade current mirror.
The CTAT current generation circuit includes 7 PMOSs, 2 NMOS tubes and 1 PNP type triode；CTAT current
Generation circuit is by adjusting the ratio of the breadth length ratio of different type metal-oxide-semiconductor, on transistor base-emitter voltage VBE basis
One linear current negatively correlated with temperature of one non-linear voltage of upper superposition and then generation, the electric current pass through cascade electric current
Mirror is mirrored to electric current summing circuit.
PMOS：MP17、MP18、MP19、MP20、MP21、MP22、MP23；NMOS tube：MN11、MN12；The pole of positive-negative-positive three
Pipe Q1；Wherein MP17, MP18, MP19, MP20 form common-source common-gate current mirror and substrate all connects respective source electrode, MP17 grid
The drain electrode of MP17 drain electrode, MP18 grid and MN11 is connect, MP17 source electrode meets MP19 drain electrode, MP19 grid and MP20
Grid, MP18 drain electrode connect the MN12 drain electrode of grid, MN12 and MN11 grid, and MP18 source electrode connects MP20 drain electrode,
The substrate that MP19 and MP20 source electrode all meets supply voltage VDD, MP21, MP22, MP23 all connects respective source electrode, MP21, MP22,
MP23 grid all earthing potentials, MP21 drain electrode connect MP22 source electrode, and MP21 source electrode connects MN11 source electrode, MP22 drain electrode
Connect MP23 source electrode, MP23 grounded drain current potential；PNP type triode Q1 base stage and grounded collector current potential, emitter stage connects
MN12 source electrode, substrate all earthing potentials of two NMOS tubes.
MN11, MN12 pipe are operated in sub-threshold region, and the ratio of the breadth length ratio of MN11, MN12 pipe is K：1, K is positive integer, and
The type of two pipes is different, and the electric current for flowing through two pipes is equal.
Understand that the expression formula of CTAT current is by the connected mode of CTAT current generation circuit：
Wherein, VEBThe emitter base voltage of PNP triode is represented,Represent the ratio of the breadth length ratio of metal-oxide-semiconductor, η generations
The table sub-threshold slope factor, VT represent thermoelectrical potential, μnRepresent the mobility of NMOS tube, CoxnRepresent the unit area grid of NMOS tube
Aoxidize layer capacitance, VthnRepresent the threshold voltage of NMOS tube, VGSpRepresent the gate source voltage of PMOS, VthpRepresent the threshold of PMOS
Threshold voltage.R1Represent PMOS and be operated in the equivalent resistance value of linear zone.
High temperature adjustment circuit can produce the other electric current of na level at temperature >=60 DEG C, electricity of being summed to more than 60 DEG C of electric currents
Electric current compensates caused by road.
Electric current summing circuit is used for summing above-mentioned PTAT current generation circuit and CTAT current generation circuit, and exports near
The electric current of zero-temperature coefficient is to current-voltage conversion circuit.
The electric current that electric current summing circuit exports is converted into voltage by current-voltage conversion circuit.
Metal-oxide-semiconductor is operated in sub-threshold region, to prevent metal-oxide-semiconductor to be operated in the border of sub-threshold region and saturation region, the grid of metal-oxide-semiconductor
Source voltage should be less than threshold voltage, and drain-source voltage is at least above 0.1V.
Further, biasing circuit includes, PMOS：MP1, MP2, MP3, MP4, NMOS tube：MN1、MN2、MN3、MN4、
MN5；Wherein, 4 PMOSs form common-source common-gate current mirrors and substrate all connects respective source electrode, and MP1 grid connects MP2 leakage
The drain electrode of pole, MP2 grid and MN2, MP1 drain electrode connect the grid of MN1 drain electrode, MN1 grid and MN2, and MP1 source electrode connects
MP3 drain electrode, MP2 source electrode connect the grid of MP4 drain electrode, MP4 grid and MP3, and MP3, MP4 source electrode connect supply voltage
VDD；In order to reach the source ground current potential of the effect of isolation, 5 NMOS tube substrates and MN1 pipes, MN2 source electrode connects MN3 leakage
Pole, the source electrode that MN3, MN4, MN5 grid all meets output reference voltage VREF, MN3 connect MN4 drain electrode, and MN4 source electrode meets MN5
Drain electrode, MN5 source ground current potential.
Further, PTAT current generation circuit includes, PMOS：MP5、MP6、MP7、MP8、MP9、MP10、MP11、
MP12, MP13, MP14, MP15, MP16, NMOS tube：MN6, MN7, MN8, MN9, MN10, operational amplifier：OPA；Wherein, MP5,
MP6, MP7, MP8 pipe form common-source common-gate current mirror and substrate all connects respective source electrode, and MP5 grid connects MP1 grid and MP6
Grid, MP5 drain electrode connects the grid of MN6 drain electrode, MN6 grid and MN7, and MP5 source electrode connects MP7 drain electrode, MP6 leakage
Pole connects the grid of MN8 drain electrode, MN8 grid and MN9, and MP6 source electrode connects MP8 drain electrode, and MP7 grid connects MP3 grid
With MP8 grid, MP7 and MP8 source electrode all connect supply voltage VDD, MP9, MP10, MP11, MP12 pipe and form another common source
Source common-gate current mirror and substrate all connect respective source electrode, and MP9 grid connects the drain electrode of MP9 drain electrode, MP10 grid and MN10,
MP9 source electrode connects the grid of MP11 drain electrode, MP11 grid and MP12, and MP10 drain electrode connects MP16 source electrode, MP10 source
Pole connects MP12 drain electrode, and the substrate that MP11 and MP12 source electrode all meets supply voltage VDD, MP13, MP14, MP15, MP16 all connects
Respective source electrode, the drain electrode of MP13, MP14, MP15, MP16 grid, MP13 and MP14 drain electrode all earthing potentials, MP13's
Source electrode connects MP15 drain electrode, and MP14 source electrode connects MP16 drain electrode, and MP15 source electrode connects MN10 source electrode and operational amplifier OPA
Reverse input end, formed negative-feedback；The substrate of 5 NMOS tubes is all connected to ground potential, and MN6 source electrode meets MN7 drain electrode and MN9
Source electrode, MN7 source ground current potential, MN8 source electrode meets MN9 drain electrode and operational amplifier OPA input in the same direction, MN10
Grid connect operational amplifier OPA output end.
Further, the ratio of the breadth length ratio of MN7 and MN6 pipes is 1：The ratio of the breadth length ratio of N, MN9 and MN8 pipe is 1：M,
Wherein N and M is positive integer, and the two ratios are determined by circuit power consumption, flows through electric current all phases of MN6, MN7, MN8, MN9 pipe
Deng being equal to PTAT current caused by biasing circuit.
Understand that the expression formula of PTAT current is by the connected mode of PTAT current generation circuit：
Wherein, R2It is the equivalent resistance value μ that PMOS is operated in linear zonepRepresent the mobility of PMOS, CoxpRepresent
The unit area gate oxide capacitance of PMOS.
Further, electric current summing circuit includes, PMOS：MP24, MP25, MP26, MP27, MP28, MP29, switch：
SW1、SW2；Wherein, the substrate of 6 PMOSs is all connected to respective source electrode, and MP24 grid connects MP9 grid, MP24 drain electrode
The source electrode for meeting output reference voltage VREF, MP24 connects MP25 drain electrode, and MP25 grid connects MP11 grid, MP26 grid and
MP27 grid connects MP17 grid, and MP26 drain electrode connects switch SW1 one end, and MP26 source electrode meets MP28 drain electrode, MP27
Drain electrode connect switch SW2 one end, MP27 source electrode connects MP29 drain electrode, and M28 grid and MP29 grid connect MP19 grid
Pole, MP25, MP28, MP29 source electrode all meet supply voltage VDD；Switch SW1 and SW2 another termination output reference voltage
VREF。
Further, current-voltage conversion circuit includes, PMOS：MP32、MP33、MP34；The grid of 3 PMOSs
All connect " " current potential, substrate all connects respective source electrode, and MP32 drain electrode connects MP33 source electrode, and MP32 source electrode connects output with reference to electricity
VREF is pressed, MP33 drain electrode connects MP34 source electrode, MP34 grounded drain current potential.
Further, high temperature adjustment circuit includes, PMOS：MP30, MP31, NMOS tube：MN13, MN14, switch：SW3、
SW4、SW5、SW6；The grid that the substrate of 2 PMOSs all meets supply voltage VDD, MP30 connects MP30 source electrode and supply voltage
VDD, MP30 drain electrode connect switch SW3 one end, and MP31 grid connects the drain electrode of MP31 source electrode and supply voltage VDD, MP31
Connect switch SW4 one end；Switch SW3 and SW4 another termination output reference voltage VREF；MN13 grid connects MN13 source electrode
With switch SW5 one end, MN14 grid connects MN14 source electrode and switch SW6 one end, and MN13 and MN14 drain electrode connect output
Reference voltage VREF；Switch SW5 and SW6 another terminal ground potential.
Further, after considering high temperature adjustment circuit, the expression formula in output reference voltage source is：
VREF=(AIPTAT+B·ICTAT+IHT)·R3 (5)
Wherein, R3Also the equivalent resistance that PMOS is operated in linear zone, I are representedHTRepresent compensation electric current during high temperature, A,
B is current ratio constant.As long as it follows that form R1、R2、R3Metal-oxide-semiconductor type it is the same, then their temperature coefficient can be with
Cancel out each other, on the temperature coefficient in output reference voltage source without influence.
The present invention is designed using non-resistance, first determines the temperature coefficient of PTAT current, then determines the temperature system of CTAT current
Number reaches high-order temperature compensated effect simultaneously, and resistance is replaced with the metal-oxide-semiconductor for being operated in deep linear zone；Secondly, temperature is being aligned
Coefficient carries out eliminating high-order temperature coefficient while temperature-compensating；Finally, carried out for temperature coefficient of temperature when higher
The adjustment of temperature high-order is smaller to reach temperature coefficient in whole temperature range.It is different from traditional method, the temperature in the case of without hindrance
Coefficient is very low.Influenceed by voltage-to-current and current/charge-voltage convertor with eliminating the temperature of metal-oxide-semiconductor；Carrying out positive temperature system
Reach high-order temperature compensated effect while number compensation, it is high-order temperature compensated to carry out to avoid designing other circuits, saves
Chip area and power consumption；Meanwhile although circuit employs cascode structure and improves PSRR, its supply voltage is still
0.9V can be reached, this further reduces power consumption, can reach nanowatt rank.
In summary, the present invention realizes low-power consumption, and chip area is small, and has high-order temperature compensated reference voltage
Source.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention；
Fig. 2 is the circuit diagram of embodiment；
Fig. 3 is the detailed circuit diagram of embodiment CTAT current generation circuit；
Fig. 4 is the temperature characterisitic schematic diagram of embodiment.
Embodiment
With reference to the accompanying drawings and examples, the present invention is described in detail：
Physical circuit framework as shown in Fig. 2 including biasing circuit, PTAT current generation circuit, CTAT current generation circuit,
High temperature adjustment circuit, electric current summation and current-voltage conversion circuit.
Biasing circuit includes, PMOS：MP1, MP2, MP3, MP4, NMOS tube：MN1、MN2、MN3、MN4、MN5；Wherein, 4
Individual PMOS forms common-source common-gate current mirror and substrate all connects respective source electrode, and MP1 grid connects MP2 drain electrode, MP2 grid
With MN2 drain electrode, MP1 drain electrode connects the grid of MN1 drain electrode, MN1 grid and MN2, and MP1 source electrode connects MP3 drain electrode,
MP2 source electrode connects the grid of MP4 drain electrode, MP4 grid and MP3, and MP3, MP4 source electrode meet supply voltage VDD；In order to reach
The source ground current potential of the effect of isolation, 5 NMOS tube substrates and MN1 pipes, MN2 source electrode connect MN3 drain electrode, MN3, MN4,
The source electrode that MN5 grid all meets output reference voltage VREF, MN3 connects MN4 drain electrode, and MN4 source electrode connects MN5 drain electrode, MN5's
Source ground current potential.
PTAT current generation circuit includes, PMOS：MP5、MP6、MP7、MP8、MP9、MP10、MP11、MP12、MP13、
MP14, MP15, MP16, NMOS tube：MN6, MN7, MN8, MN9, MN10, operational amplifier：OPA；Wherein, MP5, MP6, MP7,
MP8 pipes form common-source common-gate current mirror and substrate all connects respective source electrode, and MP5 grid connects MP1 grid and MP6 grid,
MP5 drain electrode connects the grid of MN6 drain electrode, MN6 grid and MN7, and MP5 source electrode connects MP7 drain electrode, and MP6 drain electrode meets MN8
Drain electrode, MN8 grid and MN9 grid, MP6 source electrode connects MP8 drain electrode, and MP7 grid connects MP3 grid and MP8
Grid, MP7 and MP8 source electrode all connect supply voltage VDD, MP9, MP10, MP11, MP12 pipe and form another cascode current
Mirror and substrate all connect respective source electrode, and MP9 grid connects the drain electrode of MP9 drain electrode, MP10 grid and MN10, MP9 source electrode
The grid of MP11 drain electrode, MP11 grid and MP12 is connect, MP10 drain electrode connects MP16 source electrode, and MP10 source electrode connects MP12's
The substrate that drain electrode, MP11 and MP12 source electrode all meet supply voltage VDD, MP13, MP14, MP15, MP16 all connects respective source electrode,
The drain electrode of MP13, MP14, MP15, MP16 grid, MP13 and MP14 drain electrode all earthing potentials, MP13 source electrode connect MP15's
Drain electrode, MP14 source electrode connect MP16 drain electrode, and MP15 source electrode connects the reverse input of MN10 source electrode and operational amplifier OPA
End, form negative-feedback；The substrate of 5 NMOS tubes is all connected to ground potential, and MN6 source electrode meets MN7 drain electrode and MN9 source electrode, MN7
Source ground current potential, MN8 source electrode connects MN9 drain electrode and operational amplifier OPA input in the same direction, and MN10 grid connects fortune
Calculate amplifier OPA output end.
CTAT current generation circuit includes, PMOS：MP17, MP18, MP19, MP20, MP21, MP22, MP23, NMOS
Pipe：MN11, MN12, PNP type triode Q1；Wherein MP17, MP18, MP19, MP20 form common-source common-gate current mirror and substrate
Respective source electrode is connect, MP17 grid connects the drain electrode of MP17 drain electrode, MP18 grid and MN11, and MP17 source electrode connects MP19's
The grid of drain electrode, MP19 grid and MP20, MP18 drain electrode connect the MN12 drain electrode of grid, MN12 and MN11 grid,
MP18 source electrode connects MP20 drain electrode, and MP19 and MP20 source electrode all connect supply voltage VDD, MP21, MP22, MP23 substrate all
Respective source electrode, MP21, MP22, MP23 grid all earthing potentials are connect, MP21 drain electrode connects MP22 source electrode, MP21 source electrode
MN11 source electrode is connect, MP22 drain electrode connects MP23 source electrode, MP23 grounded drain current potential；PNP type triode Q1 base stage and
Grounded collector current potential, emitter stage connect MN12 source electrode, substrate all earthing potentials of two NMOS tubes.
Electric current summing circuit includes, PMOS：MP24, MP25, MP26, MP27, MP28, MP29, switch：SW1、SW2；Its
In, the substrate of 6 PMOSs is all connected to respective source electrode, and MP24 grid connects MP9 grid, and MP24 drain electrode connects output reference
Voltage VREF, MP24 source electrode connect MP25 drain electrode, and MP25 grid connects MP11 grid, MP26 grid and MP27 grid
MP17 grid is connect, MP26 drain electrode connects switch SW1 one end, and MP26 source electrode connects MP28 drain electrode, and MP27 drain electrode connects out
Closing SW2 one end, MP27 source electrode connects MP29 drain electrode, and M28 grid and MP29 grid connect MP19 grid, MP25,
MP28, MP29 source electrode all meet supply voltage VDD；Switch SW1 and SW2 another termination output reference voltage VREF.
Current-voltage conversion circuit includes, PMOS：MP32、MP33、MP34；The grid of 3 PMOSs all connects " " electricity
Position, substrate all connect respective source electrode, and MP32 drain electrode connects MP33 source electrode, and MP32 source electrode meets output reference voltage VREF,
MP33 drain electrode connects MP34 source electrode, MP34 grounded drain current potential.
High temperature adjustment circuit includes, PMOS：MP30, MP31, NMOS tube：MN13, MN14, switch：SW3、SW4、SW5、
SW6；The grid that the substrate of 2 PMOSs all meets supply voltage VDD, MP30 connects MP30 source electrode and supply voltage VDD, MP30's
Drain electrode connects switch SW3 one end, and the drain electrode that MP31 grid connects MP31 source electrode and supply voltage VDD, MP31 connects switch SW4's
One end；Switch SW3 and SW4 another termination output reference voltage VREF；MN13 grid connects MN13 source electrode and switchs SW5's
One end, MN14 grid connect MN14 source electrode and switch SW6 one end, and MN13 and MN14 drain electrode connect output reference voltage
VREF；Switch SW5 and SW6 another terminal ground potential.
Fig. 4 shows the temperature characterisitic of the present embodiment.
The present invention operation principle be：
In PTAT current generation circuit, MN6, MN7, MN8, MN9 are the metal-oxide-semiconductors of core, for producing and temperature positive correlation
Voltage, and except for replacing the metal-oxide-semiconductor of resistance to be all operated in sub-threshold region in the circuit, the electric current of sub-threshold region metal-oxide-semiconductor-
Voltage expression is
Because metal-oxide-semiconductor drain-source voltage VDS is more than 0.1V, the item in bracket can be ignored, and MN7 is selected according to circuit power consumption
Ratio with the breadth length ratio of MN6 pipes is 1：The ratio of the breadth length ratio of N, MN9 and MN8 pipe is 1：M, flow through MN6, MN7, MN8 and MN9
Electric current it is equal and pipe type is identical, therefore voltage is V at VAA=η VTLn (MN), because thermoelectrical potential VT has positive temperature
Coefficient, so voltage VAWith positive temperature coefficient, the in the same direction of operational amplifier, reverse input end voltage are equal, by the electricity at VA
Pressing tongs position is to VB, the electric current by current/charge-voltage convertor by the voltage conversion of positive temperature coefficient for positive temperature coefficient.
In CTAT current generation circuit, MN11, MN12 pipe are core metal-oxide-semiconductors, and Q1 is core triode, for producing and temperature
Spend negatively correlated voltage while carry out high-order temperature compensated.Except being all operated in Asia for the metal-oxide-semiconductor of replacement resistance in the circuit
Threshold zone, the ratio of the breadth length ratio of MN11, MN12 pipe is K：1, and the type of two pipes is different, therefore they have different move
Shifting rate, unit gate oxide capacitance and threshold voltage, the electric current for flowing through two branch roads are equal.According to Kirchhoff's second law
Know, VC=VGSn12-VGSn11+VEB, wherein,
It is exactly thermoelectrical potential VT, about 25.9mV at room temperature, q=1.6 × 1019C, is electronic charge, and T is Kai Er
Literary temperature, k=1.38 × 10-23J/ DEG C, be Boltzmann constant, VGSnRepresent the gate source voltage of NMOS tube, VG0It is silicon in Kai Er
Band gap voltage when literary temperature is zero, about 1.206V, ρ are the temperatures coefficient related to technique, and θ is the rank related to temperature
Number, TrIt is reference temperature；In formula (10) first two it is related to temperature linearity, latter is related to nonlinear temperature, joint (8),
(9), (10) formula, the expression formula for obtaining voltage at VC are：
Threshold voltage VthIt is negatively correlated with nonlinear temperature, it can be seen that as long as selecting suitable MN11, MN12 to manage, by
Nonlinear terms caused by nonlinear temperature coefficient caused by above formula Section 3 and Section 5 can be offset, only remaining and temperature
Linearly related item, this has reached the effect for producing linear negative temperature term and counteracting nonlinear temperature item simultaneously.Theoretical according to zero-temperature coefficient, the size of positive temperature coefficient is equal to the size of negative temperature coefficient,
I.e.COEFFICIENT K is determined by following formula：
In high temperature adjustment circuit, MN13, MN14, MP30, MP31 pipe are core metal-oxide-semiconductors, metal-oxide-semiconductor grid source short circuit used,
So VGS=0, sub-threshold region is operated in, shown in its I-E characteristic such as formula (13), tandem tap is opened under various circumstances
Or shut-off, ensure that the temperature coefficient of whole circuit under various circumstances is all good.
Due to grid source short circuit, metal-oxide-semiconductor is not turned on, and in room temperature, electric current is very small, when the temperature increases, in view ofInfluence, electric current can become big, the effect for the current compensation that reaches a high temperature.
In current-voltage conversion circuit, replace resistance that the current signal after weighting is converted into voltage signal with metal-oxide-semiconductor,
Its equivalent resistance is：
Output reference voltage expression formula is：
VREF=(AIPTAT+B·ICTAT+IHT)·R3 (15)
It is clear that the PMOS for choosing same type forms equivalent resistance, for carrying out Voltage-current conversion and electricity
Stream-voltage conversion, then their mobility, unit gate oxide capacitance and threshold voltage all, therefore, although single in theory
The equivalent resistance that individual MOS is formed is relevant with temperature, but their ratio is temperature independent, so as to which output reference voltage source obtains more
Good temperature characterisitic.
Claims (5)
1. a kind of reference voltage source of low-power consumption, including biasing circuit, PTAT current generation circuit, CTAT current generation circuit,
High temperature adjustment circuit, electric current summation and current-voltage conversion circuit, it is characterised in that：
Biasing circuit produces bias voltage and provides biasing for PTAT current generation circuit；
PTAT current generation circuit is used for producing passing through with the positively related linear current of temperature, the electric current by weighting thermoelectrical potential VT
Cascade current mirror is mirrored to electric current summing circuit；
The CTAT current generation circuit includes 7 PMOSs, 2 NMOS tubes and 1 PNP type triode；CTAT current produces
Circuit is folded by adjusting the ratio of the breadth length ratio of different type metal-oxide-semiconductor on the basis of transistor base-emitter voltage VBE
Add a non-linear voltage and then produce a linear current negatively correlated with temperature, the electric current passes through cascade current mirror mirror
As arriving electric current summing circuit；
PMOS：MP17、MP18、MP19、MP20、MP21、MP22、MP23；NMOS tube：MN11、MN12；PNP type triode Q1；
Wherein MP17, MP18, MP19, MP20 form common-source common-gate current mirror and substrate all connects respective source electrode, and MP17 grid connects
The drain electrode of MP17 drain electrode, MP18 grid and MN11, MP17 source electrode connect the grid of MP19 drain electrode, MP19 grid and MP20
Pole, MP18 drain electrode connect the MN12 drain electrode of grid, MN12 and MN11 grid, and MP18 source electrode meets MP20 drain electrode, MP19
The substrate that supply voltage VDD, MP21, MP22, MP23 are all met with MP20 source electrode all meets respective source electrode, MP21, MP22, MP23
Grid all earthing potentials, MP21 drain electrode connects MP22 source electrode, and MP21 source electrode connects MN11 source electrode, and MP22 drain electrode connects
MP23 source electrode, MP23 grounded drain current potential；PNP type triode Q1 base stage and grounded collector current potential, emitter stage connects
MN12 source electrode, substrate all earthing potentials of two NMOS tubes；
MN11, MN12 pipe are operated in sub-threshold region, and the ratio of the breadth length ratio of MN11, MN12 pipe is K：1, K is positive integer, and two
The type of pipe is different, and the electric current for flowing through two pipes is equal；
Understand that the expression formula of CTAT current is by the connected mode of CTAT current generation circuit：
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Wherein, VEBThe emitter base voltage of PNP triode is represented,The ratio η for representing the breadth length ratio of metal-oxide-semiconductor represents subthreshold
It is worth slope factor, VT represents thermoelectrical potential, μnRepresent the mobility of NMOS tube, CoxnRepresent the unit area gate oxide of NMOS tube
Electric capacity, VthnRepresent the threshold voltage of NMOS tube, VGSpRepresent the gate source voltage of PMOS, VthpThe threshold voltage of PMOS is represented,
R1Represent PMOS and be operated in the equivalent resistance value of linear zone；
High temperature adjustment circuit can produce the other electric current of na level at temperature >=60 DEG C, and more than 60 DEG C of electric current summing circuits are produced
Raw electric current compensates；
Electric current summing circuit is used for summing above-mentioned PTAT current generation circuit and CTAT current generation circuit, and exports nearly zero temperature
The electric current of coefficient is spent to current-voltage conversion circuit；
The electric current that electric current summing circuit exports is converted into voltage by current-voltage conversion circuit；
Metal-oxide-semiconductor is operated in sub-threshold region, to prevent metal-oxide-semiconductor to be operated in the border of sub-threshold region and saturation region, the grid source electricity of metal-oxide-semiconductor
Pressure should be less than threshold voltage, and drain-source voltage is at least above 0.1V.
2. the reference voltage source of low-power consumption as claimed in claim 1, it is characterised in that：
The biasing circuit includes, PMOS MP1, MP2, MP3, MP4 and NMOS tube MN1, MN2, MN3, MN4, MN5；Wherein, 4
Individual PMOS forms common-source common-gate current mirror and substrate all connects respective source electrode, and MP1 grid connects MP2 drain electrode, MP2 grid
With MN2 drain electrode, MP1 drain electrode connects the grid of MN1 drain electrode, MN1 grid and MN2, and MP1 source electrode connects MP3 drain electrode,
MP2 source electrode connects the grid of MP4 drain electrode, MP4 grid and MP3, and MP3, MP4 source electrode meet supply voltage VDD；5 NMOS
Tube lining bottom and the source ground current potential of MN1 pipes, MN2 source electrode connect MN3 drain electrode, and MN3, MN4, MN5 grid all connect output ginseng
The source electrode for examining voltage VREF, MN3 connects MN4 drain electrode, and MN4 source electrode connects MN5 drain electrode, MN5 source ground current potential.
3. the reference voltage source of low-power consumption as claimed in claim 1, it is characterised in that：
The PTAT current generation circuit includes, PMOS MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13,
MP14, MP15, MP16, NMOS tube MN6, MN7, MN8, MN9, MN10 and operational amplifier OPA；Wherein, MP5, MP6, MP7, MP8
Pipe forms common-source common-gate current mirror and substrate all connects respective source electrode, and MP5 grid meets MP1 grid and MP6 grid, MP5
Drain electrode connect the grid of MN6 drain electrode, MN6 grid and MN7, MP5 source electrode connects MP7 drain electrode, and MP6 drain electrode connects MN8's
The grid of drain electrode, MN8 grid and MN9, MP6 source electrode connect MP8 drain electrode, and MP7 grid connects MP3 grid and MP8 grid
Pole, MP7 and MP8 source electrode all connect supply voltage VDD, MP9, MP10, MP11, MP12 pipe and form another common-source common-gate current mirror
And substrate all connects respective source electrode, MP9 grid connects the drain electrode of MP9 drain electrode, MP10 grid and MN10, and MP9 source electrode connects
The grid of MP11 drain electrode, MP11 grid and MP12, MP10 drain electrode connect MP16 source electrode, and MP10 source electrode connects MP12 leakage
The substrate that pole, MP11 and MP12 source electrode all meet supply voltage VDD, MP13, MP14, MP15, MP16 all connects respective source electrode,
The drain electrode of MP13, MP14, MP15, MP16 grid, MP13 and MP14 drain electrode all earthing potentials, MP13 source electrode connect MP15's
Drain electrode, MP14 source electrode connect MP16 drain electrode, and MP15 source electrode connects the reverse input of MN10 source electrode and operational amplifier OPA
End, form negative-feedback；The substrate of 5 NMOS tubes is all connected to ground potential, and MN6 source electrode meets MN7 drain electrode and MN9 source electrode, MN7
Source ground current potential, MN8 source electrode connects MN9 drain electrode and operational amplifier OPA input in the same direction, and MN10 grid connects fortune
Calculate amplifier OPA output end.
The ratio of the breadth length ratio of MN7 and MN6 pipes is 1：The ratio of the breadth length ratio of N, MN9 and MN8 pipe is 1：M, wherein N and M are
Positive integer, the two ratios are determined by circuit power consumption, and it is all equal to flow through the electric current of MN6, MN7, MN8, MN9 pipe, is equal to partially
PTAT current caused by circuits；
The ratio of the breadth length ratio of MN7 and MN6 pipes is 1：The ratio of the breadth length ratio of N, MN9 and MN8 pipe is 1：M, wherein N and M are
Positive integer, the two ratios are determined by circuit power consumption, and it is all equal to flow through the electric current of MN6, MN7, MN8, MN9 pipe, is equal to partially
PTAT current caused by circuits；
Understand that the expression formula of PTAT current is by the connected mode of PTAT current generation circuit：
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Wherein, R2It is the equivalent resistance value that PMOS is operated in linear zone, μpRepresent the mobility of PMOS, CoxpRepresent
The unit area gate oxide capacitance of PMOS.
4. the reference voltage source of low-power consumption as claimed in claim 1, it is characterised in that：
The electric current summing circuit includes, PMOS MP24, MP25, MP26, MP27, MP28, MP29 and switch SW1, SW2；Its
In, the substrate of 6 PMOSs is all connected to respective source electrode, and MP24 grid connects MP9 grid, and MP24 drain electrode connects output reference
Voltage VREF, MP24 source electrode connect MP25 drain electrode, and MP25 grid connects MP11 grid, MP26 grid and MP27 grid
MP17 grid is connect, MP26 drain electrode connects switch SW1 one end, and MP26 source electrode connects MP28 drain electrode, and MP27 drain electrode connects out
Closing SW2 one end, MP27 source electrode connects MP29 drain electrode, and M28 grid and MP29 grid connect MP19 grid, MP25,
MP28, MP29 source electrode all meet supply voltage VDD；Switch SW1 and SW2 another termination output reference voltage VREF.
5. the reference voltage source of low-power consumption as claimed in claim 1, it is characterised in that：
The high temperature adjustment circuit includes, PMOS MP30, MP31, NMOS tube MN13, MN14 and switch SW3, SW4, SW5,
SW6；The grid that the substrate of 2 PMOSs all meets supply voltage VDD, MP30 connects MP30 source electrode and supply voltage VDD, MP30's
Drain electrode connects switch SW3 one end, and the drain electrode that MP31 grid connects MP31 source electrode and supply voltage VDD, MP31 connects switch SW4's
One end；Switch SW3 and SW4 another termination output reference voltage VREF；MN13 grid connects MN13 source electrode and switchs SW5's
One end, MN14 grid connect MN14 source electrode and switch SW6 one end, and MN13 and MN14 drain electrode connect output reference voltage
VREF；Switch SW5 and SW6 another terminal ground potential；
After high temperature adjustment circuit, the expression formula in output reference voltage source is：
VREF=(AIPTAT+B·ICTAT+IHT)·R3 (5)
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Wherein, R3Also the equivalent resistance that PMOS is operated in linear zone, I are representedHTCompensation electric current during high temperature is represented, A, B are
Current ratio constant.
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Cited By (13)
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|---|---|---|---|---|
| CN108196614A (en) * | 2018-01-03 | 2018-06-22 | 何金昌 | A kind of band gap reference and supply unit with temperature-compensating |
| CN109495078A (en) * | 2019-01-14 | 2019-03-19 | 上海艾为电子技术股份有限公司 | A kind of reference voltage generating circuit and Switching Power Supply |
| CN109901655A (en) * | 2019-03-29 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | Generating circuit from reference voltage |
| WO2019157992A1 (en) * | 2018-02-13 | 2019-08-22 | 杭州芯元微电子有限公司 | Cmos high temperature reference voltage source |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
| CN110502060A (en) * | 2018-05-18 | 2019-11-26 | 华润矽威科技（上海）有限公司 | Constant current start-up circuit |
| CN110794889A (en) * | 2019-10-29 | 2020-02-14 | 刘洋 | Temperature control system for slice dyeing reaction cabin |
| CN111552342A (en) * | 2020-05-21 | 2020-08-18 | 东南大学 | Low-power-consumption reference voltage and reference current generating circuit |
| CN112000171A (en) * | 2020-09-04 | 2020-11-27 | 中筑科技股份有限公司 | Voltage reference source circuit applied to low-power-consumption ultrasonic gas flowmeter |
| CN112947668A (en) * | 2021-05-13 | 2021-06-11 | 上海类比半导体技术有限公司 | Band-gap reference voltage generation circuit with high-order temperature compensation |
| CN114265038A (en) * | 2021-11-22 | 2022-04-01 | 电子科技大学 | High-precision switch type phase-shifting unit with temperature compensation effect |
| CN115437447A (en) * | 2022-10-26 | 2022-12-06 | 电子科技大学 | MOS tube temperature sensor with low-temperature leakage compensation |
| CN116027840A (en) * | 2023-02-21 | 2023-04-28 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
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| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108196614A (en) * | 2018-01-03 | 2018-06-22 | 何金昌 | A kind of band gap reference and supply unit with temperature-compensating |
| WO2019157992A1 (en) * | 2018-02-13 | 2019-08-22 | 杭州芯元微电子有限公司 | Cmos high temperature reference voltage source |
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| CN109495078A (en) * | 2019-01-14 | 2019-03-19 | 上海艾为电子技术股份有限公司 | A kind of reference voltage generating circuit and Switching Power Supply |
| CN109901655A (en) * | 2019-03-29 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | Generating circuit from reference voltage |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
| CN110794889A (en) * | 2019-10-29 | 2020-02-14 | 刘洋 | Temperature control system for slice dyeing reaction cabin |
| CN111552342A (en) * | 2020-05-21 | 2020-08-18 | 东南大学 | Low-power-consumption reference voltage and reference current generating circuit |
| CN112000171A (en) * | 2020-09-04 | 2020-11-27 | 中筑科技股份有限公司 | Voltage reference source circuit applied to low-power-consumption ultrasonic gas flowmeter |
| CN112947668A (en) * | 2021-05-13 | 2021-06-11 | 上海类比半导体技术有限公司 | Band-gap reference voltage generation circuit with high-order temperature compensation |
| CN114265038A (en) * | 2021-11-22 | 2022-04-01 | 电子科技大学 | High-precision switch type phase-shifting unit with temperature compensation effect |
| CN114265038B (en) * | 2021-11-22 | 2024-02-09 | 电子科技大学 | High-precision switch type phase shifting unit with temperature compensation effect |
| CN115437447A (en) * | 2022-10-26 | 2022-12-06 | 电子科技大学 | MOS tube temperature sensor with low-temperature leakage compensation |
| CN115437447B (en) * | 2022-10-26 | 2023-08-01 | 电子科技大学 | MOS tube temperature sensor with low-temperature leakage compensation |
| CN116027840A (en) * | 2023-02-21 | 2023-04-28 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
| CN116027840B (en) * | 2023-02-21 | 2023-05-23 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
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