CN115997272A - 在衬底上沉积硅锗层的方法 - Google Patents
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 91
- 239000000758 substrate Substances 0.000 title claims abstract description 70
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 238000000151 deposition Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000006911 nucleation Effects 0.000 description 5
- 238000010899 nucleation Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000003517 fume Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Abstract
一种在衬底(1)上异质外延沉积硅锗层(3)的方法,包括:在衬底(1)的顶部设置掩模层(4);去除所述掩模层(4)的外侧部分,以提供到达所述衬底的环形自由表面(6)的通路,其中所述环形自由表面(6)位于所述衬底的边缘区域中并围绕所述掩模层(4)的剩余部分(5);在所述衬底的环形自由表面(6)的顶部沉积圆筒形硅锗层(2);去除所述掩模层的剩余部分;以及在所述衬底(1)的顶部和所述圆筒形硅锗层(2)的顶部沉积所述硅锗层(3),所述硅锗层(3)接触所述圆筒形硅锗层(2)的内侧表面。
Description
技术领域
本发明涉及一种在衬底上沉积硅锗(SiGe)层的方法。
背景技术
使用SiGe沟道的半导体器件代表了对于仅基于硅的相应器件的一种令人感兴趣的替代方案。为了提供用于集成SiGe沟道的SiGe层,SiGe层通常必须被异质外延沉积于衬底(例如硅单晶晶圆)的顶部。众所周知,由于衬底与异质外延SiGe层的晶格失配,在沉积工艺的过程中会形成错配位错(MD)、穿线位错(TD)和穿线位错的位错堆积(DP)。
为了减少与MD、TD和DP的存在以及与使异质外延SiGe层的表面粗糙化的交叉网线有关的问题,已经做了许多尝试。
US 2010 0 291 761A1提出了提供沉积在衬底的背面的应力补偿SiGe层。
US 2010 0 317 177A1公开了一种方法,该方法包括在衬底上沉积第一SiGe层以及在第一SiGe层的顶部沉积第二SiGe层。
根据US 2004 0 075 105A1,可以通过一种方法减少DP的形成,该方法包括在其表面上具有大致均匀分布的多个TD的第一半导体层上形成大致弛豫的帽盖层。
最近,一篇论文(Fabrizio Rovaris,Continuum modeling of heteroepitaxy atthe mesoscale:tackling elastic and plastic relaxation,University of Milano-Bicocca DEPARTMENT OF MATERIALS SCIENCE,Academic year2019/2020)被发表,该论文报告称,在衬底的边缘处的高缺陷区域的存在提供了穿线臂的贮存器,一旦生长膜达到临界厚度,其便可以弛豫,并且作为效果,通过消除第一弛豫阶段的环的随机成核,观察到了TD密度的显著降低。该论文的作者(其与本发明的发明人已进行过合作)没有公布通过在衬底的背面沉积应力补偿SiGe层来获得衬底的边缘处的高缺陷区域。
发明内容
本发明的目的在于进一步降低异质外延沉积在衬底上的SiGe层的TD密度。
该目的通过一种在衬底上异质外延沉积硅锗层的方法来实现,该方法包括:
在所述衬底的顶部设置(提供)掩模层;
去除所述掩模层的外侧部分,以提供到达所述衬底的环形自由表面的通路,其中所述环形自由表面位于所述衬底的边缘区域中并围绕所述掩模层的剩余部分;
在所述衬底的所述环形自由表面的顶部沉积圆筒形硅锗层;
去除所述掩模层的剩余部分;以及
在所述衬底的顶部以及所述圆筒形硅锗层的顶部沉积所述硅锗层,所述硅锗层接触所述圆筒形硅锗层的内侧表面。
硅单晶衬底上的SiGe缓冲层通过在优先成核位点处的异质成核而弛豫,因为衬底中不存在预先存在的位错。众所周知,Si晶圆的边缘表现出机械缺陷,这些机械缺陷用作优先成核位点。应变能在生长期间的外延层中积累,一旦达到用于该过程的激活能,位错便在这些位点处迅速成核,从而形成厚的位错束。这些错配位错束导致穿线位错堆积的形成,因为它们能有效地阻挡其他位错的滑移。由于位错被阻挡,更多的位错需要被成核,以完全弛豫该层,这导致更高的穿线位错密度(TDD)。为了更受控制的弛豫过程并防止错配位错束,需要具有低激活能的均匀分布的位错源。
本发明提出一种在SiGe层的边缘区域中实现这种源的方式。该边缘贮存器由在SiGe层之前沉积的弛豫或部分弛豫的SiGe层(以下称为圆筒形SiGe层)构成。SiGe层与圆筒形SiGe层具有竖直接触,或具有竖直接触和水平接触两者。通过在达到临界厚度后朝向晶圆的中心自由滑移,包含在该边缘贮存器中的预先存在的位错被用于在初始弛豫阶段中弛豫SiGe层,从而留下极长的错配位错区段而不被阻挡。该过程通过晶圆边缘处的异质成核防止了厚位错束的形成,从而防止了DP的形成并降低了总TDD。
尽管下面的描述涉及在硅单晶衬底上沉积SiGe层,但也可以使用如绝缘体上硅(SOI)晶圆的其他衬底。根据本发明的一个优选实施例,衬底为具有200mm或300mm的直径的硅单晶晶圆。
为了提供在衬底的边缘处的圆筒形SiGe层,采用了掩蔽方案(手段)。原则上,可以使用用于暂时排除衬底的表面区域的SiGe层沉积的任何掩蔽机制(机构)。根据本发明的一个优选实施例,使用如SiO2的氧化材料、例如低温氧化物(LTO)作为掩蔽材料。LTO可以在含有硅烷(SiH4)和氧气(O2)的气氛中、在300℃与500℃之间的温度下通过化学气相沉积(CVD)沉积在衬底的顶部。可替代地,可以使用用于沉积氧化层的其他已知方法,或者可以在850℃与1200℃之间的温度下、在快速热退火(RTP)炉中通过干式氧化来生长氧化层。
接下来,在衬底的边缘区域中去除掩模层,以提供衬底的环形自由表面,该环形自由表面从衬底的边缘朝向衬底的中心延伸。边缘区域中的掩模层可以例如通过利用氢氟酸的湿法蚀刻或利用氟化铵和氢氟酸的湿法蚀刻来去除,或者通过利用例如CF4等的等离子体蚀刻来去除。根据本发明的一个实施例,衬底的边缘区域中的掩模层可以通过将衬底面朝下放置在支撑件上并通过在工艺室中引入HF烟气来去除,在支撑件与掩模之间扩散的HF烟气腐蚀掉具有最多为1.5mm的宽度的掩模部分。
根据本发明的一个实施例,衬底的环形自由表面在优选地不小于200μm且不超过1.5mm的距离上从衬底的边缘朝向其中心径向延伸。衬底的环形自由表面的宽度甚至可以与衬底的边缘部分(在所述边缘部分处,衬底的厚度减小)的长度一样小,或者甚至可以更小。
接下来,圆筒形SiGe层被外延沉积在衬底的环形自由表面上。根据本发明的一个实施例,执行大气压下的CVD,以用于圆筒形硅锗层的沉积。该沉积工艺的细节是众所周知的,并且例如在US 2010 0 317 177A1中被讨论。可替代地,沉积可以在降低的压力和较低的温度下执行。根据本发明的一个实施例,圆筒形SiGe层的组分(成分)为Si1-xGex,其中0.01≤x≤1。根据本发明的另一优选实施例,圆筒形SiGe层具有不小于10nm且不超过10μm的厚度,并且圆筒形SiGe层被部分或完全弛豫。圆筒形SiGe层的上述特性允许适当地控制圆筒形SiGe层的TDD,这对于满足本发明的目的至关重要。圆筒形SiGe层的TDD优选地至少为1.0×103cm-2。
在衬底的边缘区域中提供圆筒形SiGe层之后,被圆筒形SiGe层包围的剩余掩模层被去除,并且由掩模层覆盖的衬底的表面变得可到达(可接近、可触及或可使用)以用于沉积与衬底的表面以及圆筒形SiGe层的内表面和上表面接触的SiGe层。根据本发明的一个优选实施例,SiGe层在大气压下经由CVD被外延沉积。根据本发明的另一优选实施例,SiGe层的组分为Si1-xGex,其中0.01≤x≤1。根据本发明的一个实施例,SiGe层为分级(级配)缓冲层或恒定组分层。SiGe层被部分或完全弛豫,并与衬底和圆筒形SiGe层的内表面或衬底以及圆筒形SiGe层的内表面和上表面两者接触。圆筒形SiGe层的锗含量可以低于、等于或高于SiGe层的锗含量。SiGe层具有优选地不小于0.01μm且不超过10μm的厚度。
包含在圆筒形SiGe层中的穿线位错通过在达到临界厚度后朝向中心滑移而使得SiGe层弛豫。其结果是,与现有技术的方案相比,减小了堆积密度和穿线位错密度,以及改善了表面粗糙度和总体均匀性。
下文将参照附图公开本发明。
附图说明
图1呈现了处于其最终生产状态下的晶圆的实施例的剖视图。
图2呈现了显示图1所示的晶圆的边缘区域的剖视图。
图3与图2的不同之处仅在于,晶圆的边缘区域以晶圆的中间生产状态示出。
图4是根据图3的晶圆的顶视图呈现。
图5以顶视图呈现的方式显示了在起始于衬底并终止于根据图3和图4的晶圆的中间生产状态的所要求保护的工艺的过程中的晶圆的状态。
图6示出了起始于根据图3的晶圆的中间生产状态并终止于根据图2的最终生产状态的TD的演变。
图7呈现了处于其最终生产状态下的晶圆的另一实施例的剖视图。
图8呈现了处于其最终生产状态下的晶圆的又一实施例的剖视图。
图9呈现了衬底的边缘区域的剖视图。
采用的附图标记列表
1衬底
2圆筒形硅锗层
3硅锗层
4掩模层
5掩模层的剩余部分
6衬底的环形自由表面
7边缘部分
I边缘部分的长度
w宽度
t厚度
TD穿线位错
具体实施方式
在最终生产状态下,根据本发明生产的晶圆可以具有图1所显示的结构。该结构包括衬底1、圆筒形硅锗层2以及接触圆筒形硅锗层2的内表面和上表面的硅锗层3。在图2中,示出了该晶圆的边缘区域,其在箭头的方向上从晶圆的边缘朝向晶圆的中心延伸。
在沉积硅锗层3之前,晶圆处于图3所显示的中间状态。中间状态的结构包括衬底1以及具有径向宽度w和厚度t的圆筒形硅锗层2。图4呈现了处于中间状态的晶圆的顶视图。
为了实现中间状态,如图5所示,在衬底1的上表面的顶部(或之上)设置掩模层4。然后,掩模层4的外侧部分被去除,以提供到达衬底1的在衬底1的边缘区域中的环形自由表面6的通路。接下来,圆筒形硅锗层2被沉积在环形自由表面6上,并包围掩模层4的剩余部分5。随后,掩模层4的剩余部分6也被去除,以提供中间状态,用于随后在衬底1和圆筒形硅锗层2上沉积硅锗层3。
图6示出了起始于中间生产状态直到最终生产状态为止的TD的演变。一旦达到临界厚度,包含在圆筒形硅锗层2中的穿线位错便通过朝向中心滑移来促进硅锗层3的弛豫。
在最终生产状态下,根据本发明生产的晶圆也可以具有图7或图8所显示的结构。根据图7所显示的实施例,硅锗层3接触衬底1的表面以及圆筒形硅锗层2的内表面,直至达到其一定的高度。根据图8所显示的实施例,硅锗层3和圆筒形硅锗层2具有相同的厚度。
如图9所示,衬底的环形自由表面的宽度甚至可以与衬底1的边缘部分7(在所述边缘部分7处,衬底的厚度减小)的长度I一样小,或者甚至可以比长度I小。
上文对说明性实施例的描述应被理解为是示例性的。
Claims (7)
1.一种在衬底(1)上异质外延沉积硅锗层(3)的方法,包括:
在所述衬底(1)的顶部设置掩模层(4);
去除所述掩模层(4)的外侧部分,以提供到达所述衬底的环形自由表面(6)的通路,其中所述环形自由表面(6)位于所述衬底的边缘区域中并围绕所述掩模层(4)的剩余部分(5);
在所述衬底的环形自由表面(6)的顶部沉积圆筒形硅锗层(2);
去除所述掩模层的剩余部分;以及
在所述衬底(1)的顶部以及所述圆筒形硅锗层(2)的顶部沉积所述硅锗层(3),所述硅锗层(3)接触所述圆筒形硅锗层(2)的内侧表面。
2.根据权利要求1所述的方法,包括:
提供低温氧化物材料作为掩模层(4)。
3.根据权利要求1或权利要求2所述的方法,包括:
在所述衬底的环形自由表面(6)的顶部沉积所述圆筒形硅锗层(2),使得其具有不超过1.5mm的宽度以及不小于10nm且不超过10μm的厚度。
4.根据权利要求1至3中的一项所述的方法,包括:
在所述衬底(1)的顶部以及所述圆筒形硅锗层(2)的顶部沉积所述硅锗层(3),使得其具有不小于0.01μm且不超过10μm的厚度。
5.根据权利要求1至4中的一项所述的方法,其中,
所述硅锗层(3)为恒定组分层。
6.根据权利要求1至4中的一项所述的方法,其中,
所述硅锗层(3)为分级组分层。
7.根据权利要求1至6中的一项所述的方法,其中,
所述圆筒形SiGe层(2)的锗含量低于、等于或高于所述SiGe层(3)的锗含量。
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