CN115996045A

CN115996045A - Multiphase signal control circuit and method

Info

Publication number: CN115996045A
Application number: CN202310123631.1A
Authority: CN
Inventors: 陈悦; 汪家轲; 陈亮
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-04-18
Filing date: 2019-04-18
Publication date: 2023-04-21
Also published as: CN113302827A; US11558042B2; EP3958453A4; US20220038082A1; CN113302827B; EP3958453A1; WO2020211059A1

Abstract

The application provides a multiphase signal control circuit and a multiphase signal control method, relates to the technical field of electronics, and is used for solving the problem that in the prior art, when the switching period of a PWM signal is unstable, the work of a later-stage power stage circuit is abnormal. The multiphase signal control circuit includes: the comparator is used for comparing the triangular wave signal with a feedback control signal to output a first pulse width modulation signal, and the feedback control signal is a signal fed back by the power stage circuit; and the phase-cutting circuit is used for receiving the phase switching signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, and the first phase signal and the second phase signal are used for controlling the power stage circuit to generate an output voltage signal.

Description

Multiphase signal control circuit and method

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a multiphase signal control circuit and method.

Background

A voltage converter is a circuit topology that converts an input voltage to an output voltage according to voltage requirements, and generally includes an inductance-based type of voltage converter and a switched capacitor (switched capacitor, SC) -based type of voltage converter. The voltage converter based on the switch capacitor type has the advantages of high power density, high response speed, high efficiency and the like because the main power device is a capacitor, so the voltage converter is widely used in more and more scenes. The voltage converter based on the switched capacitor type is realized through a charge-discharge working cycle of a capacitor, but because the existence of charging time can limit the continuous output capacity and output ripple of the voltage converter, the voltage converter generally adopts two-phase or multi-phase alternating working to ensure the stability of output.

As shown in fig. 1, in a conventional switched capacitor type voltage converter, a triangular wave signal and a feedback control signal determined by an error between an actual output voltage and an ideal output voltage are generally taken as inputs of a comparator to generate a pulse width modulation (pulse width modulation, PWM) signal for controlling output power, and the PWM signal is subjected to a down-conversion process by a frequency divider; and then, the down-converted signal and the PWM signal are processed by an AND gate to obtain a multiphase signal, and the down-converted signal is processed by an NOT gate and then is processed by another AND gate together with the PWM signal to obtain another phase signal. Fig. 2 is a signal timing diagram corresponding to fig. 1, taking a multiphase signal including a P1 signal and a P2 signal as an example for explanation, the P1 enable signal represents a signal after the PWM signal is down-converted, the P2 enable signal represents a signal after the P1 enable signal is logically not operated, the P1 enable signal and the PWM signal are logically and operated to generate a P1 signal, and the P2 enable signal and the PWM signal are logically and operated to generate a P2 signal. The P1 signal and the P2 signal ensure the stability of the output of the voltage converter through alternate charging and discharging.

However, the above method of generating the allowable operation signals of the respective phases by directly down-converting the PWM signal is only applicable to the case where the switching period of the PWM signal is stable. When the switching period of the PWM signal is unstable, the switching period of the signal divided by the frequency divider is also unstable. Therefore, the P1 signal and the P2 signal generated by the PWM signal and the divided PWM signal may not meet the normal operating conditions of the post-stage power stage circuit, resulting in abnormal operation of the power stage circuit, such as locking or other reliability problems.

Disclosure of Invention

The application provides a multiphase signal control circuit and a multiphase signal control method, which are used for solving the problem that in the prior art, when the switching period of a PWM signal is unstable, the power stage circuit works abnormally.

In a first aspect, a multiphase signal control circuit is provided, comprising: a signal generating circuit for generating a triangular wave signal and a phase switching signal; the comparator is used for comparing the triangular wave signal with a feedback control signal to output a first Pulse Width Modulation (PWM) signal, wherein the feedback control signal is a signal fed back by the power stage circuit; and the phase-cutting circuit is used for receiving the phase switching signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, and the first phase signal and the second phase signal are used for controlling the power stage circuit to generate an output voltage signal.

In the above technical solution, the phase switching signal generated by the signal generating circuit in the multiphase signal control circuit is independent of the first PWM signal, i.e. the phase switching signal is not affected by the switching period variation of the first PWM signal. Therefore, when the switching period of the first PWM signal is unstable, the phase switching signal can still stably control the phase switching circuit to generate a first phase signal and a second phase signal, and the first phase signal and the second phase signal can meet the normal working condition of the rear-stage power stage circuit, so that the power stage circuit can work normally, and the performance of the multiphase signal control circuit is improved.

In a possible implementation manner of the first aspect, the signal generating circuit includes: the signal generator is used for generating the triangular wave signal and a trigger signal with the same frequency as the triangular wave signal; and the frequency divider is used for carrying out frequency division processing on the trigger signal so as to obtain the phase switching signal. Optionally, the position of the jump edge of the trigger signal corresponds to the position of the peak or trough of the triangular wave signal. According to the possible implementation manner, the signal generating circuit can correspondingly divide the frequency of the trigger signal generated by the signal generator through the frequency divider according to different frequency requirements, so that the phase switching signal meeting the frequency requirements is obtained, and the accuracy of generating the phase switching signal is improved.

In a possible implementation manner of the first aspect, the multiphase signal control circuit further includes: and the latch is used for latching the first pulse width modulation signal to generate a second pulse width modulation signal and outputting the second pulse width modulation signal to the phase-cut circuit. According to the possible implementation manner, the first pulse width modulation signal is latched to generate the second pulse width modulation signal, so that the charge-discharge time of the multiphase signal generated by the phase-cut circuit can be further ensured to meet the normal working condition of the power stage circuit, and the load capacity of the voltage converter and the stability of output ripple waves are further ensured.

In a possible implementation manner of the first aspect, the phase-cut circuit includes: the first AND gate is used for carrying out logical AND operation on the phase switching signal and the second pulse width modulation signal so as to output a first phase signal; a first NOT gate for performing a logical NOT operation on the phase switching signal; and the second AND gate is used for carrying out logical AND operation on the signal subjected to logical NOT operation and the second pulse width modulation signal so as to output a second phase signal. The phase-cut circuit provided by the possible implementation manner has simple and effective structure, so that the structure of the multiphase signal control circuit can be simplified to a certain extent.

In a possible implementation manner of the first aspect, the signal generator includes: the device comprises a ring oscillator, a buffer, a first delay circuit and an integrating circuit; the ring oscillator is used for generating an oscillation signal; a buffer for buffering the oscillation signal to output a clock signal; a first delay circuit for delaying the clock signal by a first phase to output the trigger signal; and the integrating circuit is used for carrying out integration processing on the trigger signal so as to output the triangular wave signal. Alternatively, the signal generator includes: a relaxation oscillator and a first delay circuit; a relaxation oscillator for generating a clock signal and generating the triangular wave signal according to the clock signal; the first delay circuit is used for receiving the clock signal and delaying the clock signal by a first phase so as to output the trigger signal. The above possible implementation manner can improve the diversity and flexibility of the design of the signal generator, thereby further improving the diversity and flexibility of the design of the multiphase signal control circuit.

In a possible implementation manner of the first aspect, the signal generator is further configured to: generating a pulse holding signal, and outputting the pulse holding signal to an enabling end of the latch, wherein the position of a high-level pulse width of the pulse holding signal corresponds to the position of a high-level pulse width of the trigger signal. According to the possible implementation manner, when the rising edge of the phase switching signal overlaps with the high-level pulse width of the first pulse width modulation signal, the first phase signal and the second phase signal generated by the phase switching circuit can meet the requirement of normal operation of the power level circuit.

In a possible implementation manner of the first aspect, the signal generator further includes: a second delay circuit and a D flip-flop; the second delay circuit is used for delaying the clock signal by a second phase to output a clock delay signal, and the second phase is equal to twice of the first phase; and the D trigger is used for receiving the clock signal through a clock input end and receiving the clock delay signal through a setting end and generating the pulse holding signal according to the clock signal and the clock delay signal. Alternatively, the signal generator further includes: a second delay circuit and a logic operation circuit; the second delay circuit is used for delaying the clock signal by a second phase to output a clock delay signal, and the second phase is equal to twice of the first phase; and the logic operation circuit is used for carrying out logical negation operation on the clock delay signal and carrying out logical AND operation on the operated signal and the clock signal so as to generate the pulse holding signal. The above possible implementation manner can further improve the diversity and flexibility of the design of the signal generator, thereby further improving the diversity and flexibility of the design of the multiphase signal control circuit.

In a possible implementation manner of the first aspect, the high level pulse width of the pulse hold signal is equal to any one of the following cases: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time. In the possible implementation manner, the signal generator can flexibly set the high-level pulse width of the pulse holding signal according to actual requirements, so that the accuracy of the generated pulse holding signal is improved.

In a possible implementation manner of the first aspect, the frequency of the phase switching signal is N times that of the triangular wave signal, where N is an integer greater than or equal to 1; the result of the logical OR of the first phase signal and the second phase signal is a first pulse width modulated signal. The possible implementation manner can enable the first phase signal and the second phase signal generated by the switching circuit to meet the requirement of normal operation of the power level circuit, and simultaneously improve the performance of the multiphase signal control circuit.

In a second aspect, there is provided a multiphase signal control circuit comprising: a signal generating circuit for generating a triangular wave signal and a phase switching signal, the frequency of the phase switching signal being N times that of the triangular wave signal, N being an integer greater than or equal to 1; the comparator is used for comparing the triangular wave signal with a feedback control signal to output a first Pulse Width Modulation (PWM) signal, wherein the feedback control signal is a signal fed back by the power stage circuit; and the phase-cutting circuit is used for carrying out phase-cutting processing on the first pulse width modulation by utilizing the phase switching signal so as to obtain a first phase signal and a second phase signal, wherein the logic or result of the first phase signal and the second phase signal is the first pulse width modulation signal, and the first phase signal and the second phase signal are used for controlling the power stage circuit to generate an output voltage signal. In the above technical solution, the phase switching signal generated by the signal generating circuit in the multiphase signal control circuit is independent of the first PWM signal, i.e. the phase switching signal is not affected by the switching period variation of the first PWM signal. Therefore, when the switching period of the first PWM signal is unstable, the phase switching signal can still stably control the phase switching circuit to generate a first phase signal and a second phase signal which are alternately charged and discharged, and the first phase signal and the second phase signal can meet the normal working condition of the power stage circuit at the rear stage, so that the power stage circuit can normally generate a stable output voltage signal, and meanwhile, the load capacity of the voltage converter and the stability of output ripple can be ensured.

In a possible implementation manner of the second aspect, the signal generator is configured to generate the triangular wave signal and a trigger signal with the same frequency as the triangular wave signal; and the frequency divider is used for carrying out frequency division processing on the trigger signal to obtain the phase switching signal, and the position of the jump edge of the trigger signal corresponds to the position of the wave crest or the wave trough of the triangular wave signal. According to the possible implementation manner, the signal generating circuit can correspondingly divide the frequency of the trigger signal generated by the signal generator through the frequency divider according to different frequency requirements, so that the phase switching signal meeting the frequency requirements is obtained, and the accuracy of generating the phase switching signal is improved.

In a possible implementation manner of the second aspect, the multiphase signal control circuit further includes: the latch is used for latching the first pulse width modulation signal to output a second pulse width modulation signal and outputting the second pulse width modulation signal to the phase-cut circuit; optionally, the signal generator is further configured to: generating a pulse hold signal, the position of the high-level pulse width of the pulse hold signal may correspond to the position of the high-level pulse width of the trigger signal, and the high-level pulse width of the pulse hold signal may be greater than or equal to the high-level pulse width of the trigger signal at the corresponding position; the latch is specifically configured to latch the first pulse width modulation signal according to the pulse holding signal, so as to output the second pulse width modulation signal. According to the possible implementation manner, the first pulse width modulation signal is latched through the pulse holding signal to output the second pulse width modulation signal, so that the charge and discharge time of the multiphase signal generated by the second pulse width modulation signal can be ensured to meet the requirements of the power level circuit on the minimum turn-off time and the minimum turn-on time, and the load capacity of the voltage converter and the stability of output ripple waves are further ensured.

In a possible implementation manner of the second aspect, the high level pulse width of the pulse hold signal is equal to any one of the following cases: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time. According to the possible implementation manner, the signal generator can flexibly set the high-level pulse width of the pulse holding signal according to actual requirements, so that the accuracy of the generated pulse holding signal is improved.

In a possible implementation manner of the second aspect, the phase-cut circuit includes: the first AND gate is used for carrying out logical AND operation on the phase switching signal and the second pulse width modulation signal so as to output a first phase signal; a first NOT gate for performing a logical NOT operation on the phase switching signal; and the second AND gate is used for carrying out logical AND operation on the signal subjected to logical NOT operation and the second pulse width modulation signal so as to output a second phase signal. In the possible implementation manner, the phase switching signal is utilized to phase-cut the second pulse width modulation signal, and the charge and discharge time of the generated multiphase signal can meet the requirements of the power stage circuit on the minimum turn-off time and the minimum turn-on time, so that the load capacity of the voltage converter and the stability of output ripple are ensured.

In a possible implementation manner of the second aspect, the signal generator includes: the device comprises a ring oscillator, a buffer, a first delay circuit and an integrating circuit; the ring oscillator is used for generating an oscillation signal; a buffer for buffering the oscillation signal to output a clock signal; a first delay circuit for delaying the clock signal by a first phase to output the trigger signal; and the integrating circuit is used for carrying out integration processing on the trigger signal so as to output the triangular wave signal. Alternatively, the signal generator includes: a relaxation oscillator and a first delay circuit; a relaxation oscillator for generating a clock signal and generating the triangular wave signal according to the clock signal; the first delay circuit is used for receiving the clock signal and delaying the clock signal by a first phase so as to output the trigger signal. The above possible implementation manner can improve the diversity and flexibility of the design of the signal generator, thereby further improving the diversity and flexibility of the design of the multiphase signal control circuit.

In a possible implementation manner of the second aspect, the signal generator further includes: a second delay circuit and a D flip-flop; the second delay circuit is used for delaying the clock signal by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase; and the D trigger is used for receiving the clock signal through a clock input end and receiving the clock delay signal through a setting end and generating the pulse holding signal according to the clock signal and the clock delay signal. Alternatively, the signal generator further includes: a second delay circuit and a logic operation circuit; the second delay circuit is used for delaying the clock signal by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase; the logic operation circuit is used for performing logic NOT operation on the clock delay signal and performing logic AND operation on the operated signal and the clock signal so as to generate the pulse holding signal. The above possible implementation manner can further improve the diversity and flexibility of the design of the signal generator, thereby further improving the diversity and flexibility of the design of the multiphase signal control circuit.

In a third aspect, a multiphase signal control method is provided, the method comprising: generating a triangular wave signal and a phase switching signal, wherein the frequency of the phase switching square wave signal is N times of that of the triangular wave signal, and N is an integer greater than or equal to 1; comparing the triangular wave signal with a feedback control signal to output a first pulse width modulation signal, the feedback control signal being related to an error between the output voltage signal and a preset voltage signal; and carrying out phase-cutting processing on the first pulse width modulation signal by utilizing the phase switching signal to obtain a first phase signal and a second phase signal, wherein the logic or result of the first phase signal and the second phase signal is the first pulse width modulation signal, and the first phase signal and the second phase signal are used for generating the output voltage signal.

In a possible implementation manner of the third aspect, generating the triangular wave signal and the phase switching signal includes: generating the triangular wave signal and a trigger signal with the same frequency as the triangular wave signal; and carrying out frequency division processing on the trigger signal to obtain the phase switching signal, wherein the position of the jump edge of the trigger signal corresponds to the position of the wave crest or the wave trough of the triangular wave signal.

In a possible implementation manner of the third aspect, the method further includes: latching the first pulse width modulation signal to output a second pulse width modulation signal; correspondingly, the phase switching signal is utilized to carry out phase switching processing on the first pulse width modulation signal, so as to obtain a first phase signal and a second phase signal, which are specifically as follows: and carrying out phase cutting processing on the second pulse width modulation signal by utilizing the phase switching signal to obtain a first phase signal and a second phase signal. Optionally, the method further comprises: generating a pulse holding signal, wherein the position of a high-level pulse width of the pulse holding signal corresponds to the position of a high-level pulse width of the trigger signal; accordingly, latching the first pulse width modulated signal to output a second pulse width modulated signal, comprising: the first pulse width modulation signal is latched according to the pulse holding signal to output a second pulse width modulation signal.

In a possible implementation manner of the third aspect, the high level pulse width of the pulse hold signal is equal to any one of the following cases: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time.

In a possible implementation manner of the third aspect, performing phase-cut processing on the pulse width modulated signal by using the phase switching signal to obtain a first phase signal and a second phase signal, including: performing logical AND operation on the phase switching signal and the second pulse width modulation signal to output a first phase signal; and performing logical negation operation on the phase switching signal, and performing logical AND operation on the operated signal and the second pulse width modulation signal to output a second phase signal.

In a possible implementation manner of the third aspect, generating a triangular wave signal and generating a trigger signal with the same frequency as the triangular wave signal includes: generating an oscillation signal; buffering the oscillation signal to output a clock signal; delaying the clock signal by a first phase to output the trigger signal; and integrating the trigger signal to output the triangular wave signal.

Alternatively, generating a triangular wave signal and generating a trigger signal of the same frequency as the triangular wave signal, includes: generating a clock signal and generating the triangular wave signal according to the clock signal; the clock signal is delayed by a first phase to output the trigger signal.

In a possible implementation manner of the third aspect, generating the pulse-hold signal includes: delaying the clock signal by a second phase to output a clock delayed signal, the second phase being equal to twice the first phase; the pulse hold signal is generated based on the clock signal and the clock delay signal.

In a fourth aspect, there is provided a voltage converter comprising: and a power stage circuit, and a multiphase signal control circuit as provided in the first aspect or any one of the possible implementations of the first aspect; the multi-phase signal control circuit is used for generating a first phase signal and a second phase signal according to a feedback control signal, and the power stage circuit is used for generating an output voltage signal according to the first phase signal and the second phase signal.

In a fifth aspect, there is provided a voltage conversion chip including: a multiphase signal control circuit as provided in the first aspect or any one of the possible implementations of the first aspect.

In a sixth aspect, there is provided a voltage conversion chip including: a power stage circuit, and a multiphase signal control circuit as provided in the first aspect or any one of the possible implementations of the first aspect; the multi-phase signal control circuit is used for generating a first phase signal and a second phase signal according to a feedback control signal, and the power stage circuit is used for generating an output voltage signal according to the first phase signal and the second phase signal.

In a seventh aspect, a communication device is provided, which may be a terminal or a base station, the communication device comprising: a processing chip, and a voltage conversion chip as provided in the sixth aspect, the voltage conversion chip being configured to supply power to the processing chip.

It can be appreciated that any of the above-mentioned multi-phase signal control methods, voltage converters, voltage conversion chips, communication devices, etc. may be implemented by the corresponding multi-phase signal control circuit provided above, and therefore, the beneficial effects thereof may be referred to the beneficial effects in the multi-phase signal control circuit provided above, and will not be described herein.

Drawings

FIG. 1 is a schematic diagram of a multi-phase signal control circuit according to the prior art;

FIG. 2 is a signal timing diagram of a prior art method for generating a multi-phase signal;

fig. 3 is a schematic structural diagram of a voltage converter according to an embodiment of the present disclosure;

FIG. 4 is a signal timing diagram for generating a multi-phase signal according to an embodiment of the present disclosure;

FIG. 5 is a second signal timing diagram for generating a multi-phase signal according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a multiphase signal control circuit according to an embodiment of the present application;

fig. 7 is a timing chart of a phase switching signal according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram ii of a multiphase signal control circuit according to an embodiment of the present application;

FIG. 9 is a third signal timing diagram for generating a multi-phase signal according to the embodiment of the present application;

FIG. 10 is a signal timing diagram for generating a multi-phase signal according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram III of a multiphase signal control circuit according to an embodiment of the present application;

FIG. 12 is a fifth signal timing diagram for generating a multi-phase signal according to the embodiment of the present application;

FIG. 13 is a schematic diagram of a signal generator according to an embodiment of the present disclosure;

fig. 13A is a schematic diagram of a second structure of a signal generator according to an embodiment of the present application;

Fig. 13B is a schematic structural diagram III of a signal generator according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a signal generator according to an embodiment of the present application;

fig. 14A is a schematic diagram of a signal generator according to an embodiment of the present disclosure;

fig. 14B is a schematic structural diagram of a signal generator according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a power stage circuit according to an embodiment of the present disclosure;

fig. 16 is a flow chart of a multiphase signal control method according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple. The character "/" generally indicates that the context-dependent object is an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and the order of execution.

In this application, the terms "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

Fig. 3 is a schematic structural diagram of a voltage converter provided in an embodiment of the present application, referring to fig. 3, the voltage converter includes a multiphase signal control circuit 110 and a power stage circuit 120. Wherein the multiphase signal control circuit 110 is configured to generate a pulse width modulation (pulse width modulation, PWM) signal according to a feedback control signal fed back by the power stage circuit 120, and generate a multiphase signal alternately charged and discharged based on the PWM signal, for example, the multiphase signal may be a two-phase signal or a three-phase signal with different phases; the power stage circuit 120 is configured to generate a stable output voltage signal from the multiphase signal. It should be noted that, the specific process of the power stage circuit 120 to generate the stable output voltage signal according to the multiphase signal may be referred to as related description in fig. 13 below, and the embodiments of the present application will not be described herein.

Currently, in voltage converters based on the switched capacitor (switched capacitor, SC) type, the permissible operating signals for the respective phases are usually generated by down-converting pulse width modulated (pulse width modulation, PWM) signals; the enable signals for each phase are then logically operated with the PWM signals to produce alternately operated multiphase signals. For example, in the signal timing diagram shown in fig. 2, the PWM signal is logically and-operated with the P1 enable operation signal and the P2 enable operation signal, respectively, to generate the P1 signal and the P2 signal, and the P1 signal and the P2 signal ensure the stability of the output of the voltage converter by alternately charging and discharging. However, this method is only applicable to cases where the switching period of the PWM signal is stable and at non-extreme frequencies. When the switching period of the PWM signal is unstable and the frequency is too low or too high, the allowable operation signals of the respective phases cannot be normally generated.

For example, as shown in fig. 4, when the frequency of the PWM signal is too low, the voltage converter needs to discharge in a full period due to insufficient output capability, which results in that the PWM signal is in a dead-through state (i.e., the PWM signal is always in a high level state and cannot realize phase switching) in a period t01 shown in fig. 4, at this time, a P1 enable signal and a P2 enable signal for phase switching cannot be generated through frequency reduction, which results in abnormal operation state of the voltage converter. In this case, the clock reset clk_resetn signal shown in the dashed line box in fig. 4 and the PWM signal (denoted as pwm_comp signal in the dashed line box) that is directly locked may be used to perform a logic operation to generate a new PWM signal, and further, the phase switching is implemented by the new PWM signal.

For example, as shown in fig. 5, when the frequency of the PWM signal is too high, a situation of discharging after short charging occurs after a long discharging period, for example, a situation of discharging in a t3 period after long discharging in a t11 period and short charging in a t12 period shown in fig. 5 (P1 allows the high level in the working signal and P2 allows the high level in the working signal to be discharged and the low level to be charged) occurs, at this time, parasitic inductance of a switching tube in the power stage circuit may be suddenly converted into discharging in a high current charging state, and after the current direction is suddenly changed, a very high burr voltage on the switching tube in the power stage circuit may be caused, thereby affecting the reliability of the voltage converter and further causing an abnormal working state of the voltage converter. In this case, the reliability of the voltage converter may be ensured by increasing the shortest pulse width corresponding to the high level (denoted as T1 in fig. 5) and the shortest pulse width corresponding to the low level (denoted as T2 in fig. 5) in the PWM signal as shown by the dashed line box in fig. 5, for example, setting the shortest pulse width corresponding to the high level equal to the minimum on time minTon and setting the shortest pulse width corresponding to the low level equal to the minimum off time minToff. The minimum on-time and the minimum off-time are determined by the response time of the power stage circuit to control the charging and discharging, and are used for avoiding the condition that the output voltage signal generated by the power stage circuit is short-circuited between the power supply end and the ground end.

However, in the mode shown in fig. 4, if the frequency of clk_resetn is too high, the PWM signal is easily triggered to flip by mistake, which affects the normal operation of the voltage converter, and if the frequency of clk_resetn is too low, the switching frequency of charging and discharging is reduced, thereby reducing the load capacity of the voltage converter. In the manner shown in fig. 5, increasing the shortest pulse width corresponding to the high level in the PWM signal decreases the maximum output duty cycle, and increasing the shortest pulse width corresponding to the low level in the PWM signal decreases the minimum output duty cycle, which results in an earlier start-up cycle of the output voltage signal, which results in a decrease in the load carrying capability of the voltage converter and an increase in the output ripple.

Based on this, the embodiment of the application provides a multiphase signal control circuit, which can still normally generate the allowed working signals of each phase under the condition that the switching period of the PWM signal is unstable, and further generate multiphase signals for alternately charging and discharging according to the PWM signal and the allowed working signals of each phase, so that the power stage circuit can generate stable output voltage signals according to the multiphase signals, and meanwhile, the load capacity of the voltage converter and the stability of output ripple can be ensured.

Fig. 6 is a schematic structural diagram of a multiphase signal control circuit according to an embodiment of the present application, where the multiphase signal control circuit includes: a signal generating circuit 201, a comparator 202 and a phase cut circuit 203.

In the embodiment of the present application, the signal generating circuit 201 is configured to generate a triangular wave signal and a phase switching signal, where the frequency of the phase switching signal may be N times that of the triangular wave signal, and N is an integer greater than or equal to 1. The signal generating circuit 201 may be configured to generate a clock signal, and generate the triangular wave signal and the phase switching signal according to the clock signal, where the phase switching signal may be a signal generated near a peak or a trough of the triangular wave signal, and the phase switching signal may be a pulse signal, a square wave signal, a sawtooth wave signal, or any specific signal. For example, taking the phase switching signal as a square wave signal, the phase switching signal shown in fig. 7 (a) is a signal generated near the peak of the triangular wave signal, and the phase switching signal shown in fig. 7 (b) is a signal generated near the trough of the triangular wave signal. Optionally, as shown in fig. 8, the signal generating circuit 201 includes a signal generator 2011 and a frequency divider 2012; the signal generator 2011 is specifically configured to generate a triangular wave signal and a trigger signal (the trigger signal may be a pulse signal, a square wave signal, a sawtooth wave signal, or any specific signal) with the same frequency as the triangular wave signal (i.e. the frequency is the same), where a position of a jump edge of the trigger signal may be the same as a position of a peak or a trough of the triangular wave signal, and the frequency divider 2012 is specifically configured to divide the trigger signal to obtain the phase switching signal. It should be noted that, the signal generating circuit 201 may only include the signal generator 2011, at this time, the phase switching signal is the trigger signal, and the frequency of the phase switching signal is the same as the frequency of the triangular wave signal; when the signal generating circuit 201 includes both the signal generator 2011 and the frequency divider 2012, the frequency of the phase switching signal is an integer multiple of the frequency of the triangular wave signal. In addition, the frequency of the triangular wave signal generated by the signal generator 2011 may be stable.

The comparator 202 is configured to compare the triangular wave signal with a feedback control signal, and the feedback control signal is a signal fed back by the power stage circuit, so as to output a first pulse width modulation PWM signal. The feedback control signal may be an arbitrary waveform signal, and the feedback control signal may be a signal generated by the power stage circuit according to an error between an actual output voltage and a preset output voltage, that is, the feedback control signal is related to the error between the output voltage signal and the preset voltage signal. In addition, the comparator 202 may specifically be configured to receive the triangular wave signal generated by the signal generating circuit 201 and the feedback control signal output by the power stage circuit, and compare the triangular wave signal and the feedback control signal to output the first PWM signal. For example, the comparator 202 may output a high level when the feedback control signal is greater than the triangular wave signal and a low level when the feedback control signal is less than the triangular wave signal, thereby obtaining the first PWM signal.

The phase-cutting circuit 203 is configured to perform phase-cutting processing on the first PWM signal by using the phase switching signal, to obtain a first phase signal and a second phase signal, where the first phase signal and the second phase signal are used to control the power stage circuit to generate an output voltage signal. Alternatively, the phase-cut circuit 203 may divide the high-level pulse width of the first PWM signal into at least one of the first phase signal or the second phase signal by using the phase-switching signal (for example, divide the first high-level pulse width of the first PWM signal into the first phase signal, divide the second high-level pulse width into the second phase signal, divide a part of the third high-level pulse width into the first phase signal, and divide the other part into the second phase signal); alternatively, the phase-cut circuit 203 may divide the low-level pulse width of the first PWM signal by using the phase-switching signal, and process the divided two signals through inverters, respectively, to obtain the first phase signal and the second phase signal. Wherein the result of the logical or of the first phase signal and the second phase signal may be the first PWM signal.

In one possible implementation, the phase cut circuit 203 may include a first and gate 2031, a not gate 2032, and a second and gate 2033; the first and gate 2031 is configured to logically and-gate the phase switching signal and the first PWM signal to obtain a first phase signal P1 (i.e., via an and gate process), the not gate 2032 is configured to logically and-gate the phase switching signal and the first PWM signal to obtain a second phase signal P2, and the second and gate 2033 is configured to logically and-gate the signal obtained by logically and-gate the first PWM signal to obtain a second phase signal P2.

The timing of the signals generated in the multiphase signal control circuit may be as shown in fig. 9, for example. Wherein S is _TR Represents a triangular wave signal S _PH The phase switching signal is represented by a PWM1 signal, the first PWM signal output from the comparator 202, the first phase signal output from the phase-cut circuit 203 is represented by P1, and the second phase signal output from the phase-cut circuit 203 is represented by P2.

In the timing chart shown in fig. 9, neither the shortest pulse width corresponding to the high level nor the shortest pulse width corresponding to the low level in the first PWM signal is identical to the phase switching signal S _PH Overlapping of the rising edges of (i.e. using phase-switching signal S) _PH The charge and discharge time of the P1 signal and the P2 signal generated by the phase-cut processing of the first PWM signal may not be smaller than the minimum pulse width corresponding to the high level or the minimum pulse width corresponding to the low level in the first PWM signal. For example, minTon in fig. 9 represents the shortest pulse width corresponding to the high level in the first PWM signal, minToff represents the shortest pulse width corresponding to the low level in the first PWM signal, the discharging time in the P1 signal and the discharging time in the P2 signal are both greater than or equal to minTon, and the charging time in the P1 signal and the P2 signal are both greater than or equal to minToff, which can enable the power stage circuit to generate the output voltage signal according to the P1 signal and the P2 signalAnd the load capacity and the stability of output ripple of the voltage converter can be ensured.

As shown in fig. 10, when the shortest pulse width corresponding to the high level (minTon in fig. 10) or the shortest pulse width corresponding to the low level (minToff in fig. 10) in the first PWM signal overlaps with the rising edge of the phase switching signal, i.e., the phase switching signal S is used _PH The charge/discharge time of the P1 signal and the P2 signal generated by the phase-cut processing of the first PWM signal may be less than the minimum pulse width corresponding to the high level or the minimum pulse width corresponding to the low level in the first PWM signal, and at this time, the multiphase signal control circuit may specifically generate the multiphase signal in the following manner.

As shown in fig. 11, the multiphase signal control circuit may further include: and a latch 204, wherein the latch 204 is used for latching the first PWM signal to output the second PWM signal. The signal generator 2011 is further configured to: the pulse holding signal is generated, the position of the high level pulse width of the pulse holding signal corresponds to the position of the high level pulse width of the trigger signal (i.e. the high level duration of the pulse holding signal is greater than or equal to the high level duration of the trigger signal in the same time period), and the clock for generating the pulse holding signal can be homologous to the clock for generating the triangular wave signal and the phase switching signal. Accordingly, the first PWM signal output by the comparator 202 may also be referred to as a pwm_cmp signal), the latch 204 is specifically configured to latch the first PWM signal according to the pulse-holding signal, so as to output the second PWM signal, for example, the latch 204 may be configured to hold the current state of the first PWM signal for a period of time when the first PWM signal overlaps with the rising edge of the pulse-holding signal, where the period of time corresponds to the high-level pulse width of the pulse-holding signal. The phase-cutting circuit 203 may be specifically configured to perform phase-cutting processing on the second PWM signal by using the phase switching signal, so as to output a first phase signal and a second phase signal, where a logical or result of the first phase signal and the second phase signal may be the second PWM signal.

Alternatively, the high pulse width of the pulse hold signal may be equal to 2 times the minimum on time (i.e., 2 minTon), 2 times the minimum off time (i.e., 2 minToff), or 2 times the maximum of the minimum on time and the minimum off time (i.e., 2×max (minTon, minToff)). In one possible implementation, the high-level pulse width of the pulse hold signal may be equal to 2 times the minimum off-time when the phase switch signal is a signal generated near the valley of the triangular wave signal, and may be equal to 2 times the minimum on-time when the phase switch signal is a signal generated near the peak of the triangular wave signal.

In this case, for example, the timing of each signal generated in the multiphase signal control circuit may be as shown in fig. 12. Wherein S is _TR Represents the triangular wave signal S generated by the signal generating circuit 201 _PH Represents the phase switching signal S generated by the signal generating circuit 201 _HOLD Representing the pulse hold signal S generated by the signal generating circuit 201 _HOLD The high level pulse width of (2×max (minTon, minToff)) pwm_cmp represents the first PWM signal output from the comparator 202, PWM2 represents the second PWM signal output from the latch 204, P1 represents the first phase signal output from the phase-cut circuit 203, and P2 represents the second phase signal output from the phase-cut circuit 203.

As can be seen from fig. 12, the signal S is held by the pulse _HOLD The latch processing of the PWM1 signal (namely PWM_CMP signal) can lead the minimum pulse width corresponding to the high level or the minimum pulse width corresponding to the low level in the output PWM2 signal to be larger than or equal to the pulse holding signal S _HOLD To thereby utilize the phase switching signal S _PH The PWM2 signal is subjected to phase-cut processing, and the charge and discharge time of the generated P1 signal and P2 signal can meet the requirements of the minimum on time and the minimum off time of the power stage circuit, so that the power stage circuit can generate stable output voltage signals according to the P1 signal and the P2 signal, and meanwhile, the load capacity of the voltage converter and the stability of output ripple waves can be guaranteed.

Further, the signal generator 2011 in the multiphase signal control circuit may specifically include the following two different configurations, which are described in detail below.

The first group, as shown in fig. 13, the signal generator 2011 may include: a ring oscillator 11, a buffer 12, a first delay circuit 13 and an integrating circuit 14. The ring oscillator 11 is configured to output an oscillation signal, where the ring oscillator 11 may be an N-stage ring oscillator including N not gates, and output ends and input ends of the N not gates are connected end to end, where N is an integer greater than or equal to 3. The buffer 12 is configured to receive an oscillation signal generated by the ring oscillator, and buffer the oscillation signal to output a clock signal, where buffering the oscillation signal may specifically refer to shaping a waveform of the oscillation signal. The first delay circuit 13 is configured to receive the clock signal and delay the clock signal by a first phase to output a trigger signal. And an integrating circuit 14 for integrating the trigger signal to generate a triangular wave signal.

Further, referring to fig. 13A, the signal generator 2011 may further include: a second delay circuit 15 and a D flip-flop 16. Wherein the second delay circuit 15 is configured to delay the clock signal output by the buffer 12 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase. The D flip-flop 16 is configured to receive the clock signal output from the buffer 12 through the clock input terminal (CLK), receive the clock delay signal output from the second delay circuit 15 through the set terminal (RESET), and generate a pulse hold signal according to the clock signal and the clock delay signal, the pulse hold signal being output from the Q output terminal of the D flip-flop 16, and the D input terminal of the D flip-flop 16 being set to a high level "1".

Alternatively, referring to fig. 13B, the signal generator 2011 may further include: the second delay circuit 15 and the logic operation circuit 17, the logic operation circuit 17 includes an not gate 171 and an and gate 172. Wherein the second delay circuit 15 is configured to delay the clock signal output by the buffer 12 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase. The logic operation circuit 17 performs a logical not operation on the clock delay signal output from the second delay circuit 15 through the not gate 171, and performs a logical and operation on the operated signal and the clock signal output from the buffer 12 through the and gate 172, so as to generate a pulse hold signal.

Note that a in fig. 13, 13A, and 13B may represent the clock signal output from the buffer 12, B may represent the trigger signal output from the first delay circuit 13, and C may represent the clock delay signal output from the second delay circuit 15.

The second group, as shown in fig. 14, the signal generator 2011 may include: a relaxation oscillator 21 and a first delay circuit 22. Wherein the relaxation oscillator 21 is used for generating a clock signal and generating a triangular wave signal according to the clock signal; the first delay circuit 22 is configured to receive the clock signal output by the relaxation oscillator 21 and delay the clock signal by a first phase to output a trigger signal. Specifically, the relaxation oscillator 21 may include a charge-discharge circuit 211, a first comparator 212, a second comparator 213, and an RS flip-flop 214; the Q output terminal of the RS flip-flop 214 is used to control the switch of the power supply terminal of the charge/discharge circuit 211 (when the Q output terminal is at a high level, the switch of the power supply terminal is closed, the power supply terminal charges the capacitor by the charging current), and the QB output terminal of the RS flip-flop 214 is used to control the switch of the ground terminal of the charge/discharge circuit (when the QB output terminal is at a low level, the switch of the ground terminal is closed, and the ground terminal discharges the capacitor by the discharging current); the output terminal of the charge-discharge circuit 211 is connected to one input terminal of the first comparator 212 and one input terminal of the second comparator 213, respectively, the other input terminal of the first comparator 212 is configured to receive a high reference voltage, the other input terminal of the second comparator 213 is configured to receive a low reference voltage, the output terminal of the first comparator 212 is connected to the R input terminal of the RS flip-flop 214 (the first comparator 212 controls the R input terminal to be high or low by comparing the output voltages of the high reference circuit and the charge-discharge circuit 211), and the output terminal of the second comparator 213 is connected to the S input terminal of the RS flip-flop 214 (the second comparator 213 controls the S input terminal to be high or low by comparing the output voltages of the low reference circuit and the charge-discharge circuit 211).

Further, referring to fig. 14A, the signal generator 2011 may further include: a second delay circuit 23 and a D flip-flop 24. Wherein the second delay circuit 23 is configured to delay the clock signal output by the relaxation oscillator 21 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase. And a D flip-flop 24 for receiving the clock signal output from the relaxation oscillator 21 through a clock input terminal (CLK), receiving the clock delay signal output from the second delay circuit 23 through a set terminal (RESET), and generating a pulse hold signal based on the clock signal and the clock delay signal, the pulse hold signal being output from the Q output terminal of the D flip-flop 24, the D input terminal of the D flip-flop 24 being set to a high level "1".

Alternatively, referring to fig. 14B, the signal generator 2011 may further include: the second delay circuit 23 and the logic operation circuit 25, the logic operation circuit 25 includes a not gate 251 and an and gate 252. Wherein the second delay circuit 23 is configured to delay the clock signal output by the relaxation oscillator 21 by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase. The logic operation circuit 25 is configured to perform a logical not operation on the clock delay signal output from the second delay circuit 23 through the not gate 251, and perform a logical and operation on the operated signal and the clock signal output from the relaxation oscillator 21 through the and gate 252, so as to generate a pulse hold signal.

In fig. 14, 14A and 14B, a may represent a clock signal output from the relaxation oscillator 21, B may represent a trigger signal output from the first delay circuit 22, and C may represent a clock delay signal output from the second delay circuit 23.

Further, as shown in fig. 15, a schematic structural diagram of a power stage circuit according to an embodiment of the present application is provided, referring to fig. 15, the power stage circuit includes: the first signal control circuit, the second signal control circuit, and the voltage output circuit between the first signal control circuit and the second signal control circuit.

Wherein the first signal control circuit may include: a first capacitor C1, two switches (denoted as SW11 and SW12 in fig. 15) controlled by a first phase signal P1, and an inverse signal of the first phase signal

Two switches (denoted as SW13 and SW14 in fig. 15) are controlled. First signal control circuitThere are a plurality of switches (i.e., SW11 to SW 14) available for receiving the first phase signal P1 and controlling the first signal control circuit according to the first phase signal P1 and the inverse signal P1 of the first phase signal.

Similarly, the second signal control circuit may include: a second capacitor C2, two switches (denoted as SW21 and SW22 in fig. 15) controlled by the second phase signal P2, and two switches (denoted as SW23 and SW24 in fig. 15) controlled by the inverse signal P __ of the second phase signal. The second signal control circuit has a plurality of switches (i.e., SW21 to SW 24) operable to receive the second phase signal P2 and control the plurality of switches in the second signal control circuit according to the second phase signal P2 and the inverse signal P __2 of the second phase signal.

The voltage output circuit may include: the inductor L, the third capacitor C3, and the switch controlled by the N signal (indicated as SW0 in fig. 15), the N signal being the inverse of the PWM signal. One end of the inductor L and one end of the switch SW0 are connected with the coupling ends LX of the first control circuit and the second control circuit, the other end of the switch SW0 is coupled with the ground end, the other end of the inductor L is coupled with one end of the third capacitor C3 as a voltage output end, and the other end of the third capacitor C3 is coupled with the ground end.

Specifically, in the first signal control circuit, when the first phase signal P1 is at a low level and the inverse signal P __1 of the first phase signal is at a high level, SW11 and SW12 are both opened, SW13 and SW14 are both closed, and both ends of the first capacitor C1 are respectively power and Ground (GND), so that the power charges the first capacitor C1; when the first phase signal P1 is at a high level and the inverse signal P __1 of the first phase signal is at a low level, SW11 and SW12 are both closed, SW13 and SW14 are both opened, two ends of the first capacitor C1 are respectively a power supply and an LX end of the inductor L, and at this time, according to the principle of unchanged capacitance charge, the voltage of the LX end connected with the upper electrode plate after the lower electrode plate of the first capacitor C1 is connected with the power supply is 2 times of the power supply voltage. The working principle of the second signal control circuit is similar to that of the first signal control circuit, and the embodiments of the present application are not repeated here.

Since the first phase signal P1 and the second phase signal P2 are obtained by phase-cutting the PWM signal, when the PWM signal is at a high level, one of the first phase signal P1 and the second phase signal P2 is always at a high level, so that the first phase signal P1 and the second phase signal P2 can ensure that the voltage of the LX terminal is always 2 times the voltage of the power terminal through logic alternation. When the PWM signal is at a low level, the inverse signal N of the PWM signal is at a high level, and the LX end node and the inductor L are in a discharge state.

Based on the foregoing, the embodiment of the present application further provides a voltage converter, where the structure of the voltage converter may be shown in fig. 3, and the voltage converter may include: a multiphase signal control circuit as shown in fig. 6, 8 or 11, and a power stage circuit as shown in fig. 15; the multiphase signal control circuit can be used for generating a first phase signal and a second phase signal according to a feedback control signal fed back by the power stage circuit; the power stage circuit is operable to generate an output voltage signal from the first phase signal and the second phase signal. The specific description of the multiphase signal control circuit and the power stage circuit may be referred to above, and the embodiments of the present application will not be repeated here.

In another possible embodiment, the present application further provides a voltage conversion chip, where the structure of the voltage conversion chip may be as shown in fig. 3, and the voltage conversion chip may include: such as the multiphase signal control circuit shown in fig. 6, 8 or 11. Further, the voltage conversion chip may further include: a power stage circuit, the structure of which may be as shown in fig. 15.

In another possible embodiment, the present application further provides a communication device, which may be a terminal or a base station, and the device may include: a processing chip, and a voltage conversion chip provided above, the voltage conversion chip being for powering the processing chip.

Fig. 16 is a schematic diagram of a multiphase signal control method according to an embodiment of the present application, including the following steps: S301-S303.

S301: generating a triangular wave signal and a phase switching signal.

Wherein, the generation of the triangular wave signal and the phase switching signal may be specifically: generating a triangular wave signal and generating a trigger signal according to the triangular wave signal; and carrying out frequency division processing on the trigger signal to obtain the phase switching signal, wherein the position of a jump edge of the trigger signal corresponds to the position of a wave crest or a wave trough of the triangular wave signal, the frequency of the phase switching square wave signal is N times of that of the triangular wave signal, and N is an integer greater than or equal to 1.

S302: the triangular wave signal is compared with a feedback control signal to output a first pulse width modulated signal, the feedback control signal being related to an error between the output voltage signal and a preset voltage signal.

S303: a first phase signal and a second phase signal are generated based on the phase switching signal and the first pulse width modulation signal. The result of the logical OR of the first phase signal and the second phase signal is the first pulse width modulation signal, and the first phase signal and the second phase signal are used for generating the output voltage signal.

Further, the method further comprises: latching the first pulse width modulation signal to generate a second pulse width modulation signal; correspondingly, according to the phase switching signal and the first pulse width modulation signal, a first phase signal and a second phase signal are generated, specifically: and generating a first phase signal and a second phase signal according to the phase switching signal and the second pulse width modulation signal. In one possible implementation, the method further includes: generating a pulse hold signal, the position of the high level pulse width of which may correspond to the position of the high level pulse width of the trigger signal; accordingly, latching the first pwm signal to generate the second pwm signal may be: the first pulse width modulation signal is latched according to the pulse holding signal to output a second pulse width modulation signal. Optionally, the high pulse width of the pulse hold signal is equal to any one of the following: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time.

Correspondingly, in S303, according to the phase switching signal and the first pulse width modulation signal, a first phase signal and a second phase signal are generated, specifically: performing logical AND operation on the phase switching signal and the second pulse width modulation signal to output a first phase signal; and performing logical negation operation on the phase switching signal, and performing logical AND operation on the operated signal and the second pulse width modulation signal to output a second phase signal.

In one possible implementation manner, the generating of the triangular wave signal and the generating of the trigger signal with the same frequency as the triangular wave signal may be specifically: generating an oscillation signal; buffering the oscillation signal to output a clock signal; delaying the clock signal by a first phase to output the trigger signal; and integrating the trigger signal to output the triangular wave signal.

In another possible implementation manner, the generating a triangular wave signal and the generating a trigger signal with the same frequency as the triangular wave signal may specifically be: generating a clock signal and generating the triangular wave signal according to the clock signal; the clock signal is delayed by a first phase to output the trigger signal.

Further, the pulse hold signal may be generated specifically as follows: delaying the clock signal by a second phase to output a clock delayed signal, the second phase being equal to twice the first phase; the clock signal and the clock delay signal are respectively input to a clock input terminal and a set terminal of the D flip-flop to generate the pulse hold signal. Alternatively, the pulse hold signal may be generated specifically as follows: delaying the clock signal by a second phase to output a clock delayed signal, the second phase being equal to twice the first phase; and performing logical negation operation on the clock delay signal, and performing logical AND operation on the operated signal and the clock signal to generate the pulse holding signal.

It should be noted that, for detailed description of the multiphase signal control method provided in the embodiments of the present application, reference may be made to the corresponding description in the multiphase signal control circuit, and the embodiments of the present application are not repeated here.

In the embodiment of the application, the generated phase switching signal is independent of the first PWM signal, i.e. the phase switching signal is not affected by the switching period variation of the first PWM signal. Therefore, when the switching period of the first PWM signal is unstable, the phase switching signal is utilized to switch the first PWM signal, so that the first phase signal and the second phase signal which are alternately charged and discharged can still be stably generated, and the first phase signal and the second phase signal can meet the normal working condition of a power stage circuit at a later stage, thereby enabling the power stage circuit to generate a stable output voltage signal according to the first phase signal and the second phase signal, and simultaneously ensuring the load carrying capacity of the voltage converter and the stability of output ripple.

In the several embodiments provided in this application, it should be understood that the disclosed circuits and methods may be implemented in other ways. For example, the above-described circuit embodiments are merely illustrative, e.g., the division of the described modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another device, or some features may be omitted, or not performed.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Finally, it should be noted that: the foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A multiphase signal control circuit, comprising:

a signal generating circuit for generating a triangular wave signal and a phase switching signal;

the comparator is used for comparing the triangular wave signal with a feedback control signal to output a first pulse width modulation signal, and the feedback control signal is a signal fed back by the power stage circuit;

and the phase-cutting circuit is used for receiving the phase switching signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, and the first phase signal and the second phase signal are used for controlling the power stage circuit to generate an output voltage signal.

2. The multiphase signal control circuit of claim 1, further comprising:

and the latch is used for latching the first pulse width modulation signal to generate a second pulse width modulation signal and outputting the second pulse width modulation signal to the phase-cut circuit.

3. The multiphase signal control circuit of claim 2, wherein the phase cut circuit comprises:

the first AND gate is used for carrying out logical AND operation on the phase switching signal and the second pulse width modulation signal so as to output the first phase signal;

the first NOT gate is used for carrying out logical NOT operation on the phase switching signal;

and the second AND gate is used for carrying out logical AND operation on the signal subjected to logical NOT operation and the second pulse width modulation signal so as to output the second phase signal.

4. The multiphase signal control circuit of claim 1, wherein the signal generator comprises: a ring oscillator, a buffer, a first delay circuit and an integrating circuit; wherein,

the ring oscillator is used for generating an oscillation signal;

the buffer is used for buffering the oscillation signal to output a clock signal;

The first delay circuit is used for delaying the clock signal by a first phase to output the trigger signal;

and the integrating circuit is used for carrying out integration processing on the trigger signal so as to output the triangular wave signal.

5. The multiphase signal control circuit of claim 1, wherein the signal generator comprises: a relaxation oscillator and a first delay circuit;

the relaxation oscillator is used for generating a clock signal and generating the triangular wave signal according to the clock signal;

the first delay circuit is used for receiving the clock signal and delaying the clock signal by a first phase so as to output the trigger signal.

6. The multiphase signal control circuit of claim 2, wherein the signal generator is further configured to:

and generating a pulse holding signal and outputting the pulse holding signal to an enabling end of the latch, wherein the position of a high-level pulse width of the pulse holding signal corresponds to the position of a high-level pulse width of the trigger signal.

7. The multiphase signal control circuit of claim 6, wherein the signal generator further comprises: a second delay circuit and a D flip-flop; wherein,

The second delay circuit is used for delaying a clock signal by a second phase to output a clock delay signal, and the second phase is equal to twice the first phase;

the D trigger is used for receiving the clock signal through a clock input end, receiving the clock delay signal through a setting end and generating the pulse holding signal according to the clock signal and the clock delay signal.

8. The multiphase signal control circuit of claim 6, wherein the signal generator further comprises: a second delay circuit and a logic operation circuit; wherein,

the logic operation circuit is used for performing logic NOT operation on the clock delay signal and performing logic AND operation on the operated signal and the clock signal so as to generate the pulse holding signal.

9. The multiphase signal control circuit according to any one of claims 6 to 8, wherein the high level pulse width of the pulse hold signal is equal to any one of: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time.

10. The multiphase signal control circuit of claim 1, wherein:

the frequency of the phase switching signal is N times of that of the triangular wave signal, and N is an integer greater than or equal to 1;

the result of the logical OR of the first phase signal and the second phase signal is the first pulse width modulated signal.

11. The multiphase signal control circuit of claim 1, wherein the location of the transition edge of the trigger signal corresponds to the location of a peak or trough of the triangular wave signal.

12. A multiphase signal control circuit, comprising:

a signal generating circuit for generating a triangular wave signal and a phase switching signal, the frequency of the phase switching signal being N times that of the triangular wave signal, N being an integer greater than or equal to 1;

and the phase-cutting circuit is used for carrying out phase-cutting processing on the first pulse width modulation signal by utilizing the phase switching signal to obtain a first phase signal and a second phase signal, wherein the result of the logical OR of the first phase signal and the second phase signal is the first pulse width modulation signal, and the first phase signal and the second phase signal are used for controlling the power stage circuit to generate an output voltage signal.

13. The multiphase signal control circuit of claim 12, further comprising:

and the latch is used for latching the first pulse width modulation signal to output a second pulse width modulation signal and outputting the second pulse width modulation signal to the phase-cut circuit.

14. The multiphase signal control circuit of claim 13, wherein the phase cut circuit comprises:

15. The multiphase signal control circuit of claim 13, wherein the signal generator comprises: the device comprises a ring oscillator, a buffer, a first delay circuit and an integrating circuit; wherein,

the ring oscillator is used for generating an oscillation signal;

16. The multiphase signal control circuit of claim 12, wherein the signal generator comprises: a relaxation oscillator and a first delay circuit;

17. The multiphase signal control circuit of claim 13, wherein the signal generator is further configured to:

18. The multiphase signal control circuit of claim 17, wherein the signal generator further comprises: a second delay circuit and a D flip-flop; wherein,

19. The multiphase signal control circuit of claim 17, wherein the signal generator further comprises: a second delay circuit and a logic operation circuit; wherein,

20. The multiphase signal control circuit according to any one of claims 17 to 19, wherein the high level pulse width of the pulse hold signal is equal to any one of: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time.

21. A method of multiphase signal control, comprising:

generating a triangular wave signal and a phase switching signal;

comparing the triangular wave signal with a feedback control signal to output a first pulse width modulation signal, the feedback control signal being related to an error between an output voltage signal and a preset voltage signal;

and generating a first phase signal and a second phase signal according to the phase switching signal and the first pulse width modulation signal, wherein the first phase signal and the second phase signal are used for generating the output voltage signal.

22. The method of claim 21, wherein the method further comprises: latching the first pulse width modulated signal to generate a second pulse width modulated signal;

the generating a first phase signal and a second phase signal according to the phase switching signal and the first pulse width modulation signal specifically includes: and generating the first phase signal and the second phase signal according to the phase switching signal and the second pulse width modulation signal.

23. The method of claim 22, wherein generating the first phase signal and the second phase signal from the phase switching signal and the second pulse width modulated signal comprises:

Performing logical AND operation on the phase switching signal and the second pulse width modulation signal to output the first phase signal;

and performing logical negation operation on the phase switching signal, and performing logical AND operation on the signal subjected to logical negation operation and the second pulse width modulation signal to output the second phase signal.

24. The method of claim 21, wherein generating the triangular wave signal and the trigger signal co-frequency with the triangular wave signal comprises:

generating an oscillation signal;

buffering the oscillation signal to output a clock signal;

delaying the clock signal by a first phase to output the trigger signal;

and integrating the trigger signal to output the triangular wave signal.

25. The method of claim 21, wherein generating the triangular wave signal and the trigger signal co-frequency with the triangular wave signal comprises:

generating a clock signal and generating the triangular wave signal according to the clock signal;

the clock signal is delayed by a first phase to output the trigger signal.

26. The method of claim 22, wherein the method further comprises: generating a pulse holding signal, wherein the position of a high-level pulse width of the pulse holding signal corresponds to the position of a high-level pulse width of the trigger signal;

The latching of the first pulse width modulated signal to generate a second pulse width modulated signal is specifically: the first pulse width modulation signal is latched according to the pulse holding signal to generate a second pulse width modulation signal.

27. The method of claim 26, wherein generating a pulse-hold signal comprises:

delaying a clock signal by a second phase to output a clock delayed signal, the second phase being equal to twice the first phase;

the pulse hold signal is generated based on the clock signal and the clock delay signal.

28. The method of claim 26 or 27, wherein the high level pulse width of the pulse hold signal is equal to any one of: twice the minimum off time, twice the minimum on time, or twice the maximum of the minimum off time and the minimum on time.

29. The method according to claim 21, wherein:

30. The method of claim 21, wherein a location of a transition edge of the trigger signal corresponds to a location of a peak or trough of the triangular wave signal.

31. A voltage conversion chip, the voltage conversion chip comprising: a power stage circuit, and a multiphase signal control circuit as claimed in any one of claims 1 to 20; wherein,

the multiphase signal control circuit is used for generating a first phase signal and a second phase signal according to a feedback control signal fed back by the power stage circuit;

the power stage circuit is configured to generate an output voltage signal according to the first phase signal and the second phase signal.

32. A communication device, the device comprising: a processing chip, and a voltage conversion chip according to claim 31 for powering the processing chip.

33. A communication device, the device comprising: and processing the chip.