CN115935866B - Method for verifying time sequence constraint function of integrated circuit - Google Patents

Method for verifying time sequence constraint function of integrated circuit Download PDF

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CN115935866B
CN115935866B CN202211683354.1A CN202211683354A CN115935866B CN 115935866 B CN115935866 B CN 115935866B CN 202211683354 A CN202211683354 A CN 202211683354A CN 115935866 B CN115935866 B CN 115935866B
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Abstract

The application discloses a verification method of a time sequence constraint function of an integrated circuit, which relates to the field of integrated circuits and comprises the steps of obtaining a time sequence constraint file of a chip to be tested, analyzing constraint mark point information and time sequence constraint destination information; determining the file type of the original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchy structure information, constraint mark point information and time sequence constraint destination information to obtain a time sequence constraint verification file; and carrying out logic function simulation and regression test on the time sequence constraint verification file based on the random function in the test case, and verifying the constraint effect. According to the scheme, the sequential verification is advanced from the subsequent gate-level netlist to the RTL stage of the preamble, so that the sequential constraint problem that a rear-end EDA tool cannot detect can be checked, the simulation of the subsequent gate-level netlist with sequential reverse mark is canceled, meanwhile, the checking coverage rate of the test case is improved, and the sequential constraint verification speed, the detection precision and the detection efficiency of the chip are greatly improved.

Description

Method for verifying time sequence constraint function of integrated circuit
Technical Field
The embodiment of the application relates to the field of integrated circuits, in particular to a method for verifying a time sequence constraint function of an integrated circuit.
Background
In addition to the logic design implementation in the field of high-performance, low-power-consumption large-scale integrated circuit design (including FPGA/IP/SOC/AISC), a time-sequence constraint (constraint) is also required to ensure that the delay time of the final real circuit after the silicon wafer production meets the requirements. The purpose is to ensure that the logic is not faulty and that the target function is implemented. The timing information of most circuits is usually automatically identified and checked by the back-end EDA implementation tool, but whether the timing constraints are accurate or correct is not checked or verified by the EDA implementation tool, and usually only depends on manual checking by engineers, which has the following problems:
1. inspection relies on the knowledge and ability of the engineer's individual and cannot guarantee quality;
2. the checking result cannot be verified, and the correctness cannot be ensured;
3. often times and times of inspection are only a few times at key research and development nodes, possibly missing some changes.
In view of the above, the existing mainstream design is not concerned in the RTL stage, and further does not verify any timing constraints, mainly because:
1. no time delay behavior on the logic RTL, or micro-delays (delta_delay) that are not manually observable but are visible to the simulated EDA tool;
2. Timing constraints cannot be checked on RTL, and the simulated EDA tool only performs logic function checks and does not do timing checks. In fact the timing check is the back-end implementation of the EDA tool functionality.
In a typical industry project, these timing constraint checks typically implement a gate level netlist (netlist) at the back end EDA tool, and after the timing (timing) has substantially converged, a timing anti-tag (back-end) is added to the gate level netlist, and then a functional test is passed to verify whether the timing is accurate. However, this solution has several problems that lead to very low efficiency and even failure:
1. the simulation speed of the gate-level netlist is tens times or even hundreds times slower than that of RTL;
2. the simulation speed of the gate-level netlist after the time sequence reverse mark is added is tens of times or hundreds of times slower than that of the gate-level netlist without the time sequence;
3. the time sequence reverse mark of the gate-level netlist needs to be started when the time sequence of a circuit is basically clean, but the time is always very late in project and even approaches to the final slice time, because the time sequence simulation cannot be finished before the slice due to the 2 reasons (low speed), and verification is invalid;
4. the time sequence reverse mark function simulation on the gate-level netlist often does not run out of all test cases (only 1% -5% possibly), so that the completeness of time sequence constraint verification cannot be guaranteed, and verification failure is caused.
Disclosure of Invention
The embodiment of the application provides a method for verifying a time sequence constraint function of an integrated circuit, which comprises the following steps:
acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchy information and constraint mark point information in the time sequence constraint file, and extracting time sequence constraint destination information in the time sequence constraint file;
determining the file type of an original description file and a time sequence file modification tool thereof, modifying a target logic behavior of the original description file according to the circuit hierarchy structure information, the constraint mark point information and the time sequence constraint destination information to obtain a time sequence constraint logic device, and generating a time sequence constraint verification file with time sequence constraint delay information; the resulting sequential constraint logic device comprises:
converting time sequence constraint information into target delay simulation behavior information based on an uncombinable simulation logic statement behavinordic, and configuring the time sequence constraint logic according to the target delay simulation behavior information; the time sequence constraint logic at least comprises a delay buffer delay_buffer, a delay module delay_module and a behavir logic; inserting the configured time sequence constraint logic device between the starting point and/or the ending point of the constraint statement mark in the original description file, replacing delay information of the original circuit simulation, and not changing logic assignment transmission of the original circuit;
Performing logic function simulation and regression testing on the time sequence constraint verification file based on a random function in the test case, and verifying the constraint effect;
when the simulation or test result is wrong, modifying the time sequence constraint file or the time sequence constraint verification file according to the error item; and when the simulation and test results meet the requirements of the target logic behaviors, ending the test and executing the subsequent chip streaming procedure.
Specifically, the circuit hierarchy information, the constraint mark point information and the time sequence constraint destination information are automatically extracted or manually extracted and confirmed through a time sequence constraint analysis tool; the types of the time sequence constraint files at least comprise TCL, excel, YAML, JSON and HASH arrays; the original description file comprises an original RTL file and an original TB design file.
Specifically, the constraint mark point information is a signal start point and/or an end point of constraint implementation and marking, and at least comprises multi-period time sequence constraint multi-cycle path information in a synchronous circuit, false path time sequence constraint false path information in an asynchronous circuit, minimum delay constraint min_delay information and maximum delay constraint max_delay information in a synchronous or asynchronous circuit, clock jitter information in the synchronous and asynchronous circuits, clock offset clock skew information in the synchronous and asynchronous circuits, clock creation create clock information in the synchronous and asynchronous circuits and data alignment data_check information in the synchronous and asynchronous circuits;
The time sequence constraint destination information is the logic function behavior corresponding to the labeling signal.
Specifically, the generating the timing constraint verification file with timing constraint delay information includes:
inserting the configured time sequence constraint logic into an original RTL file, and modifying target logic behaviors in the original RTL file to generate the time sequence constraint verification file;
or;
inserting the configured time sequence constraint logic into an original TB design file to generate a TB verification file; binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through force and/or bind and/or instance statement of HDL to generate the time sequence constraint verification file;
or;
generating independent TB verification file packages based on all the time sequence constraint logic; binding the independent TB verification file package with the starting point and/or the end point marked by the constraint statement in the original RTL file through force and/or bind and/or instance statement of HDL, and generating the time sequence constraint verification file;
the time sequence constraint delay information at least comprises delay information of multi_cycle_path, false_path, min_delay, max_delay, clock_jitter, clock_skew, create_clock and data_check.
Specifically, configuring the timing constraint logic includes:
adding delay information to the timing constraint logic when the timing constraint information includes multi_cycle_path and the target delay emulation behavior information is multi_cycle_path between selected two target data; the delay information makes random selection within 0 and the time upper limit through a random function of the original description file, and generates delay corresponding to target duration from each bit between the data input data_in to the data output data_out of the time sequence constraint logic device according to different seed values of the random function;
when the timing constraint information includes a false_path and the target delay emulation behavior information is a false_path between two selected target data; adding delay information randomly selected from 0 and an upper time limit between the data_in and the data_out;
when the timing constraint information comprises max_delay and the target delay simulation behavior information is max_delay_val between two target data; adding delay information randomly selected from 0 and max_delay_val between data_in and data_out; wherein max_delay_val represents the delay upper limit duration;
When the time sequence constraint information comprises min_delay and the target delay simulation behavior information is min_delay_val between two target data; adding delay information randomly selected from min_delay_val and a time upper limit between the data_in and the data_out; wherein min_delay_val represents the delay lower limit duration; when the time sequence constraint delay information comprises min_delay and max_delay at the same time, adding delay information which is randomly selected from the min_delay and the max_delay between the data_in and the data_out;
when the timing constraint information includes clock_jitter, and the target delay emulation behavior information is jitter_val of target data; adding delay information randomly selected from between 0 and jitter_val between data_in and data_out; where jitter val represents the time duration of the upper limit of the clock jitter.
Specifically, when the time constraint information includes clock_skew, and the target delay simulation behavior information is skew_val of the target clock; adding the configured time sequence constraint logic device on a clock signal of a target clock, and adding delay information which is randomly selected between 0 and skew_val through a random function of the original description file between data_in and data_out of the time sequence constraint logic device; wherein, skew_val represents the clock deviation upper limit duration;
When the timing constraint information comprises create_clock and the target delay emulation behavior information is period_val of a new clock domain; adding the configured time sequence constraint logic device on a designated clock signal, and adding delay information which is randomly selected from 0 and period_val between data_in and data_out; wherein period_val represents the clock cycle duration;
when the timing constraint information includes data_check, and the target delay emulation behavior information is data_check_val between two target data signals; adding the configured time sequence constraint logic into the two target data signals respectively, and adding delay information randomly selected from 0 and data_check_val between data_in and data_out; wherein, data_check_val represents the data alignment upper limit duration.
Specifically, when the time constraint information includes a false_path, and the target delay emulation behavior information is a clock_jitter between at least two clock_domain clock domains or an async asynchronous relationship between at least two clock_group clock groups; then the timing constraint delay information is inserted as the delay information of the clock jitter at the set source corresponding to the clock domain or the clock_group.
Specifically, the logic function simulation and regression test are performed on the time sequence constraint verification file based on the random function in the test case, including:
based on random function enabling, performing logic function simulation and regression testing on the time sequence constraint verification file and the original TB design file which are added into the time sequence constraint logic device, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, performing logic function simulation and regression testing on the time sequence constraint verification file formed by binding an original RTL file and the TB verification file package, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, logic function simulation and regression testing are carried out on a time sequence constraint verification file formed by binding an independent TB verification file packet with an original TB design file and the original RTL file, and the effectiveness of delay information is determined according to the delay time of an output signal.
Specifically, when the delay time of the logic function simulation or regression testing process is not matched with the delay information, determining an internal logic error;
when the error item indicates that the inserted RTL file or the TB file is in error, the modified time sequence constraint verification file is modified again according to the original RTL file or the original TB design file, and the simulation test is carried out again;
When the error item indicates that the time sequence constraint delay information is in error, the time sequence constraint file of the chip to be tested is modified and re-executed.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
the time sequence constraint can be verified by functional simulation, and the consistency and the correctness of the design and the constraint can be ensured; the timing verification is advanced from the subsequent gate-level netlist to the RTL stage of the preamble, so that the timing verification speed and efficiency are greatly improved;
the timing constraint (false_path) which cannot be checked (ignored) even by the back-end EDA tool can be checked, so that the timing constraint checked by the EDA tool can be checked by the front-end logic function simulation. What is called "shift left" in the industry, the original follow-up task is greatly advanced (at least 3 months in advance, and in fact, 6 to 12 months in advance);
after the function verification method is adopted, the simulation of the sequential reverse mark of the subsequent gate-level netlist can be canceled, so that the chip test precision and efficiency can be accelerated, and the construction period can be shortened;
the occupied resources and occupied time of the simulation server and the gate-level server are greatly reduced (the gate-level belt time sequence simulation requires multiple times or even tens times of the CPU and the memory to be increased, and the occupied time of the server is between 1 month and 3 months); thus, the server can be released to other critical tasks;
The traditional gate-level netlist with time sequence anti-standard simulation is easy to select few test cases (perhaps only 1 to 5 percent of the test cases are selected) because of the simulation speed and the server resource requirement, but the method can be used in all (100 percent of the test cases are selected) functional tests, and the checking coverage rate of time sequence constraints is greatly improved by combining random functions of each simulation, and the total coverage rate of the test cases can be up to or close to 100 percent through accumulation of different time periods and test sets.
Drawings
FIG. 1 is a flow chart of an integrated circuit timing constraint function verification method;
FIG. 2 is an algorithm flow chart of an integrated circuit timing constraint function verification method;
FIG. 3 is a schematic diagram of the timing constraint logic before and after configuration of the multi_cycle_path;
FIG. 4 is a schematic diagram of signals output by the timing constraint logic after inserting the Multicycle_Path;
FIG. 5 is a schematic diagram of the timing constraint logic after configuration of the false_path;
FIG. 6 is a schematic diagram of the signals output by the sequential constraint logic after inserting the false_path;
FIG. 7 is a schematic diagram of the structure of the timing constraint logic after configuring max_delay;
FIG. 8 is a schematic diagram of the signal output by the timing constraint logic after insertion of max_delay;
FIG. 9 is a schematic diagram of the timing constraint logic after configuring min_delay;
FIG. 10 is a schematic diagram of the signal output by the sequential constraint logic after min_delay is inserted;
FIG. 11 is a schematic diagram of the timing constraint logic after configuring min_delay and max_delay;
FIG. 12 is a schematic diagram of the signals output by the timing constraint logic after min_delay and max_delay are inserted;
FIG. 13 is a schematic diagram of the configuration clock_jitter post-timing constraint logic;
FIG. 14 is a schematic diagram of the signal output by the sequential constraint logic after clock_jitter is inserted;
FIG. 15 is a schematic diagram of the sequential constraint logic after configuration of create_clock;
FIG. 16 is a schematic of the signal output by the sequential constraint logic after insertion of create_clock;
FIG. 17 is a schematic diagram of the structure of the sequential constraint logic after configuring data_check;
FIG. 18 is a schematic diagram of the signal output by the sequential constraint logic after insertion of a data_check;
FIG. 19 is a schematic diagram of RTL simulation behavior before and after inserting a multi_cycle_path timing constraint;
FIG. 20 is RTL simulation behavior before and after insertion of a flag_path timing constraint;
FIG. 21 is a schematic diagram of RTL simulation behavior before and after insertion of a max_delay timing constraint;
FIG. 22 is a schematic diagram of RTL simulation behavior before and after clock_jitter timing constraints are inserted;
FIG. 23 is a schematic diagram of RTL simulation behavior before and after insertion of the create_clock timing constraints;
FIG. 24 is a schematic diagram of RTL simulation behavior before and after inserting a data_check timing constraint.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Reference herein to "RTL" refers to "Register Transfer Level", i.e. "register transfer level".
References herein to "HDL" refer to "Hardware Description Language," i.e., "hardware description language," including Verilog, system Verilog, VHDL.
Reference herein to "TB" refers to "test bench", i.e. "test environment and System", specifically including RTL or HDL (including Verilog, system Verilog, VHDL) based test environment, test stimulus generation and input, test result collection and observation.
Fig. 1 is a flowchart of an integrated circuit timing constraint function verification method according to an embodiment of the present application, including the following steps:
step 101, acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchy information and constraint mark point information in the time sequence constraint file, and extracting time sequence constraint destination information in the time sequence constraint file.
The time sequence constraint file is text data for verification, and the type of the time sequence constraint file at least comprises TCL, excel, YAML, JSON, a HASH array and the like; the content can be automatically extracted or manually extracted through a time sequence constraint analysis tool, and the extracted information comprises circuit hierarchy structure information and constraint mark point information and time sequence constraint destination information. These two types of information are extracted automatically or manually and converted into RTL files or TB design files. The RTL file and the TB design file are hardware description files in the field of integrated circuits and are also files for performing logic verification in the scheme.
The constraint mark information is a signal starting point and/or an ending point of constraint implementation and marking, and at least comprises multi-period time sequence constraint multi-cycle path information in a synchronous circuit, false path time sequence constraint false path information in an asynchronous circuit, minimum delay constraint min_delay information and maximum delay constraint max_delay information in the synchronous or asynchronous circuit, clock jitter information in the synchronous and asynchronous circuits, clock deviation clock skew information in the synchronous and asynchronous circuits, clock creation clock information in the synchronous and asynchronous circuits and data alignment data check information in the synchronous and asynchronous circuits. The time sequence constraint purpose information is used for explaining the logic functions corresponding to the labeling signals, namely various delay types and delay times.
The scheme mainly advances the timing verification from the subsequent gate-level netlist to the RTL or TB stage of the preamble, and simultaneously verifies the consistency and correctness of the timing constraints and logic designs of the types. The later-described inserting or binding of timing constraint delay information, i.e., the insertion or binding of delay type times of the types described above, is used for simulation. These timing constraints are all intended to ensure that the delay of the circuit on the final die does not exceed design goals, which would otherwise lead to logic design mismatch and circuit failure. The algorithm flow chart of the verification method of the timing constraint function of the corresponding integrated circuit in fig. 2 can be specifically adopted.
Step 102, determining the file type of the original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchy information, constraint mark point information and time sequence constraint destination information to generate a time sequence constraint verification file with time sequence constraint delay information.
The original file types include RTL files and TB design files, the time sequence file modification tool is an editing tool for modifying the RTL files and TB design files, the main principle is to modify the target logic behavior of the original description files, the target logic behavior is specific to the specific logic function of specific constraint information, and the time sequence constraint delay information, that is, the multi_cycle_path, false_path, min_delay, max_delay, clock_jitter, clock_skew, create_clock and data_clock delay information, is inserted at the position where the corresponding constraint needs to be generated.
The scheme provides various generation timing constraint verification files, and an original RTL file and a TB design file are taken as examples for illustration respectively.
1. The generating the timing constraint verification file based on the original RTL file specifically comprises the following steps:
and A, converting the time sequence constraint information into target delay simulation behavior information based on an uncomplicated simulation logic statement behavior logic.
And B, configuring a time sequence constraint logic device based on the target delay simulation behavior information, inserting the configured time sequence constraint logic device into an original RTL file, modifying the target logic behavior in the time sequence constraint logic device, and generating a time sequence constraint verification file.
Before modifying the target logic behavior of the file, the time sequence constraint information needs to be converted according to the time sequence constraint information to be inserted, namely the time sequence constraint information is converted into target delay simulation behavior information according to the language form of the non-comprehensive simulation logic statement, and then the time sequence constraint logic is configured according to the target delay simulation behavior information. The timing constraint logic includes various forms, such as a delay buffer, delay module, or behavir logic.
2. Generating a timing constraint verification file based on the original TB design file may specifically include the steps of:
A, configuring a time sequence constraint logic device based on target delay simulation behavior information, inserting the configured time sequence constraint logic device into an original TB design file, and generating a TB verification file.
And B, binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through force and/or bind and/or instance statement of the HDL to generate a time sequence constraint verification file.
The method is different from the generation mode of modifying RTL, and the main principle is that a new TB verification file is regenerated on the basis of an original TB design file, time sequence constraint delay information is added and configured in the generation process, and then a TB verification file package and the original RTL file are bound (essentially, a binding relation is established between two files and not a synthetic file) through force and/or bind and/or instance sentences to serve as the time sequence constraint verification file.
Besides, the method also comprises a scheme for independently generating the TB design file, which comprises the following steps:
a, configuring a time sequence constraint logic device based on target delay simulation behavior information, and generating an independent TB verification file packet based on all time sequence constraint logic devices.
And B, binding the independent TB verification file package with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force and/or bind statement and/or instance of the HDL to generate a time sequence constraint verification file.
The method is that on the premise of not changing the original TB design file, the information to be inserted is independently generated into an independent TB verification file (package), and then the independent TB verification file (package) is forcedly bound with the original RTL file to generate.
The time sequence constraint logic at least comprises a delay buffer delay_buffer, a delay module delay_module and a behavir logic. And inserting a configured delay buffer or delay module between the starting point and/or the ending point of the constraint statement annotation to replace delay information of the original circuit simulation, and not changing logic assignment transmission of the original circuit.
Regardless of what timing constraint logic is employed, the configuration process may include the following:
multi_cycle_path: when the timing constraint information includes multi_cycle_path and the target delay emulation behavior information is multi_cycle_path between two target data selected, the delay information is added to the timing constraint logic. The delay information is randomly selected within 0 and the upper time limit through a $random function of the original description file, and a delay corresponding to a target duration is generated between each bit between the data input data_in and the data output data_out of the time sequence constraint logic according to different seed values of the $random function.
For example, in one possible implementation, the constraint is set multi_cycle_path 3-from xxx.yyy.zz.data_out-to aaa.bbb.ccc.data_in. The present invention inserts timing constraint logic between xxx, yyy, zzz, data_out and aaa. This delay behavior is randomly chosen within 0 and a time upper bound (16 clock cycles h or other values) by the $random function of RTL. The delay between each bit is determined according to the different seed values of the $ random function, but the maximum delay of all bits does not exceed the upper limit (16 clock cycles or other values), and the specific time is 0 to the number of clock cycles. Wherein aaa.bbb.ccc.data_in t and xxx.yyy.zzz.data_out represent the selected target data input and target data output, respectively, with intervening timing constraint logic therebetween.
Fig. 3 is a schematic diagram of the structure of the timing constraint logic before and after the multi_cycle is configured, and fig. 4 is a schematic diagram of the signals output after the multi_cycle is inserted. As can be seen from fig. 4, the delay of outputting multiple bits after configuration of each data_out is different, and no more than 2×period.
false_path: when the timing constraint information includes a false_path and the target delay emulation behavior information is a false_path between two selected target data; delay information randomly selected from between 0 and the upper time limit is added between data_in and data_out.
For example, in one possible implementation, the constraint is set false path from xxx. The invention inserts timing constraint logic between xxx, yyy, zz, data_out and aaa.bbb.ccc.data_in, this buffer adds signal delay, this delay behavior is randomly selected within 0 and the upper time limit (16 clock cycles or other values) by the $random function of RTL, and the delay between each bit from data_out to data_in is kept different by configuring the different seed values of the $random function, but the maximum delay of all bits does not exceed the upper time limit (16 clock cycles or other values).
Fig. 5 is a schematic diagram of the configuration of the timing constraint logic after the configuration of the false_path, and fig. 6 is a schematic diagram of the signal output from the timing constraint logic after the insertion of the false_path. As can be seen from the figure, the delay of outputting multiple bits after configuration is different for each data_out, and no more than 16×period ((1) represents maximum 16×period).
The upper limit of the delay time to 16 clock cycles is mainly to reduce the influence on the overall simulation time and to prevent the possibility that the simulation cannot be ended normally in some cases. In fact other numbers may be chosen as the case may be, but should not be less than 3.
It should be noted that, when the time constraint information includes a false_path and the target delay emulation behavior information is a clock_jitter between at least two clock_domain clock domains or an async relationship between at least two clock_group clock groups; then the timing constraint delay information is inserted as the delay information of the clock_jitter at the set source corresponding to domain or clock_group. For example, when the constraint is set false_path-from clock_domain a (or clock_group pa) -to clock_domain b (or clock_group pb), the timing constraint logic is not inserted in the path between domainA (groupA) and domainB (groupB) in this scheme, but is implemented by inserting jitter in the clock, see later.
max_delay: when the time sequence constraint information comprises max_delay and the target delay simulation behavior information is max_delay_val between two selected target data; adding delay information randomly selected from 0 and max_delay_val between data_in and data_out; wherein max_delay_val represents the delay upper limit duration;
for example, the constraint is set max_delay_path #max_delay_val (e.g., 3 ns) -from xxx.yyy.zz.data_out-to aaa.bbb.ccc.data_in. The present invention inserts a timing constraint logic between xxx.yyy.zzz.data_out and aaa.bbb.ccc.data_in, which adds a signal delay that is randomly selected within 0 and max_delay_val (3 ns) by the $random function of RTL, and maintains a different delay between each bit from data_out to data_in by configuring different seed values of the $random function, but ensures that the maximum delay of all bits is not greater than #max_delay_val.
Fig. 7 is a schematic diagram of the structure of the time sequence constraint logic after configuring max_delay, and fig. 8 is a schematic diagram of the signal output by the time sequence constraint logic after inserting max_delay. As can be seen from the figure, the delays of the data_out outputting a plurality of bits after configuration are different, and none of the data_out exceeds max_delay.
min_delay: when the time sequence constraint information comprises min_delay and the target delay simulation behavior information is min_delay_val between two selected target data; adding delay information randomly selected from min_delay_val and a time upper limit between the data_in and the data_out; where min_delay_val represents the delay lower limit duration.
For example, in one possible implementation, the constraint is set min_delay_path #min_delay_val (e.g., 0.3 ns) -from xxx.yyy.zz.data_out-to aaa.bbb.ccc.data_in. The present invention inserts a timing constraint logic between xxx.yyy.zzz.data_out and aaa.bbb.ccc.data_in, which adds a signal delay that is randomly selected within #min_delay_val (0.3 ns) and the upper time limit by the $ random function of RTL, and maintains the delay between each bit from data_out to data_in differently by configuring different seed values of the $ random function, but ensures that the minimum delay of all bits is not less than min_delay_val and the maximum delay is not exceeding the upper time limit.
Fig. 9 is a schematic diagram of a structure of the sequential constraint logic after configuring min_delay, and fig. 10 is a schematic diagram of signals output by the sequential constraint logic after inserting min_delay. As can be seen from the figure, the delays of the data_out outputting a plurality of bits after configuration are different and all are larger than min_delay.
From the above-described min_delay and max_delay, when the timing constraint information includes both min_delay and max_delay, delay information randomly selected from between min_delay and max_delay_val is added between data_in and data_out, instead of taking 16 cycles as an upper limit.
Fig. 11 is a schematic diagram of a structure of the sequential constraint logic after configuring min_delay and max_delay, and fig. 12 is a schematic diagram of signals output by the sequential constraint logic after inserting min_delay and max_delay. As can be seen from the figure, the delays of the data_out after configuration to output a plurality of bits are different, but the delays are all located between min_delay and max_delay ((1) represents the minimum delay and (2) represents the maximum delay).
clock_jitter: when the timing constraint information includes clock_jitter, and the target delay simulation behavior information is jitter_val of the target data output; adding delay information randomly selected from between 0 and jitter_val between data_in and data_out; where jitter val represents the time duration of the upper limit of the clock jitter.
For example, the constraint is set clock_jitter #jitter_val (e.g., 0.03 ns) xx.yy.zz.clk_out. The present invention adds a timing constraint logic to the xx.yy.zz.clk_out signal (target data out) of the RTL, which adds a signal delay that is randomly selected within 0 and jitter_val (0.03 ns) by the $ random function of the RTL.
Fig. 13 is a schematic diagram of a configuration of the clock_jitter post-timing constraint logic, and fig. 14 is a schematic diagram of signals output by the clock_jitter post-timing constraint logic. Clk_out and Clk_out_dly correspond to data_in and data_out, and as can be seen from the figure, there is a random delay between the phases of each clock, and there is a corresponding random delay ((1) representing the phase difference, and (2) representing the random delay corresponding to the data) between the data of each clock.
clock_skew: when the timing constraint information includes clock_skew and the target delay emulation behavior information is skew_val of the target clock; adding a configured time sequence constraint logic device on a clock signal of a target clock, and adding delay information which is randomly selected between 0 and skew_val through a $random function of an original description file between data_in and data_out of the time sequence constraint logic device; where skew_val represents the clock skew upper bound duration.
For example, constraint set_clock_view #clock_val (e.g., 0.5 ns) [ get_clock #clock_name ] the present invention adds a timing constraint logic (delay_buffer) to the #clock_name signal of the RTL, and the buffer adds a signal delay, which is randomly selected within 0 and the skew_val (0.5 ns) by the $random function of the RTL. The scheme defaults to performing delay verification on all clock_skew.
create_clock: when the timing constraint information comprises create_clock and the target delay emulation behavior information is create_clock period_val of the new clock domain; adding configured time sequence constraint logic on a designated clock signal, and adding delay information randomly selected from 0 and period_val between data_in and data_out; where period val represents the clock cycle duration.
If this clock constraint defines a new clock domain, the constraint is, for example, create_clock-add-name #new_clock-period #period_val (e.g., 2 ns) [ get_pin xx.yy.zz.clk_out ]. The present invention adds a timing constraint logic (delay_buffer) to the xx.yy.zz.clk_out signal (the designated clock signal) of the RTL, the buffer adds a signal delay that is randomly selected within 0 and period_val (2 ns) by the $ random function of the RTL. The scheme defaults to verifying all the create_clock.
Fig. 15 is a schematic diagram of a structure of the sequential constraint logic after the create_clock is configured, and fig. 16 is a schematic diagram of signals output by the sequential constraint logic after the create_clock is inserted. Clk_out and Clk_out_dly correspond to data_in and data_out, and as can be seen from the figure, there is a random delay between different clocks, and neither of them exceeds a period set.
data_check: when the timing constraint information includes data_check and the target delay emulation behavior information is data_check data_check_val between two target data; respectively adding configured time sequence constraint logic devices into two target data, and adding delay information randomly selected from 0 and data_check_val between data_in and data_out; wherein, data_check_val represents the data alignment upper limit duration.
For example, constraint is set_data_check#data_check_val (e.g., 1 ns) -from [ get_pin xx.yy.zz.data_out [ m ] ] -to [ get_pin xx.yy.zz.data_out [ n ] ]. The present invention adds a timing constraint logic to each of the xx.yy.zz.data_out m and xx.yy.zz.data_out n signals (the two target data signals) of the RTL, the buffer adds a signal delay, and the delay behavior is randomly selected within 0 and data_check_val (1 ns) by the $random function of the RTL.
Fig. 17 is a schematic diagram of a structure of the timing constraint logic after the data_check is configured, and fig. 18 is a schematic diagram of signals outputted by the timing constraint logic after the data_check is inserted. data_out and data_out_dly correspond to data_in and data_out, and it can be seen from the figure that the delay of the plurality of bits is not the same, but is not longer than the data alignment period.
It should be noted that the foregoing describes a possible configuration, and other flat-replacing means may be used to add the timing constraint delay information, which is not described herein.
And obtaining the time sequence constraint verification file inserted with the time sequence constraint delay information after the configuration is completed.
And step 103, performing logic function simulation and regression testing on the time sequence constraint verification file based on the random function in the test case, and verifying the constraint effect.
In the logic function simulation and regression test, the validity of delay information is determined according to the delay time of an output signal when the logic function simulation and regression test is carried out on the sequence constraint verification file through random function enabling.
Aiming at the form of generating a time sequence constraint verification file, the verification process is divided into the following cases:
1. based on random function enabling, logic function simulation and regression testing are carried out on the time sequence constraint verification file and the original TB design file which are added into the time sequence constraint logic device, and the effectiveness of delay information is determined according to the delay time of an output signal.
2. Based on random function enabling, logic function simulation and regression testing are carried out on a time sequence constraint verification file generated by binding the TB verification file and the original RTL file, and the effectiveness of delay information is determined according to the delay time of an output signal.
3. Based on random function enabling, logic function simulation and regression testing are carried out on a time sequence constraint verification file formed by binding an independent TB verification file packet with an original TB design file and the original RTL file, and the effectiveness of delay information is determined according to the delay time of an output signal.
Because RTL behavior at timing constraints simulates delays on real circuits, if logic design errors or timing constraint errors, there is a high probability that functional simulation errors will occur. Even though in most cases no logic function errors are caused, the timing constraint logic will not be the same in each function simulation or regression test as the delay time between different batches of logic function simulations and regression tests because of the random function. If the logic design or timing constraints are inaccurate, functional errors must be made in some delay situations so that whether logic errors or timing constraint errors can be checked.
104, when the simulation or test result is wrong, modifying the time sequence constraint verification file or the time sequence constraint verification file according to the error item; and when the simulation and test results meet the requirements of the target logic behaviors, ending the test and executing the subsequent chip streaming procedure.
When the delay time and delay information of the logic function simulation or regression test process result in inaccurate results due to the addition of the above delay information, an error that is a mismatch between the internal logic design and the timing constraint can be determined.
When the error item indicates that the RTL or TB design file is in error, the modified time sequence constraint verification file is modified again according to the original RTL file or the original TB design file, and the simulation test is conducted again.
When the error item indicates that the time sequence constraint delay information is in error, modifying the time sequence constraint file of the chip to be tested, and executing the steps again to perform simulation test until the conditions are met.
If the function simulation and regression test are not wrong at all, entering a subsequent implementation flow, and carrying out traditional design implementation and time sequence check.
The final simulation behavior is described below in terms of specific embodiments, with the results of all different implementations consistent with the behavior described below; and the following examples include only partial circuit behavior and do not cover all possibilities (because of the presence of random functions).
Multi_cycle: referring to FIG. 19, a schematic diagram of RTL simulation behavior before and after inserting a multi_cycle timing constraint is shown.
RTL simulation behavior without delay (upper part), (1) illustrates that the sampling control circuit has no delay; (2) the position indicates that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower part), (1) bit random delay; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation function errors.
flag_path: referring to FIG. 20, a schematic diagram of RTL simulation behavior before and after insertion of a flag_path timing constraint is shown.
RTL simulation behavior without delay (upper part), (1) illustrates that the bits have no delay; (2) the position indicates that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower part), (1) bit random delay; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation functional errors.
max_delay: referring to FIG. 21, a schematic diagram of RTL simulation behavior before and after insertion of a max_delay timing constraint is shown.
RTL simulation behavior without delay (upper part), (1) illustrates that the bits have no delay; (2) the position indicates that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower part), (1) bit random delay; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation functional errors.
clock_jitter: referring to FIG. 22, a schematic diagram of RTL simulation behavior before and after clock_jitter timing constraints are inserted is shown.
RTL simulation behavior without delay (upper part), no jitter constraint is represented at (1); (2) the data is correctly captured; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower part), (1) represents the insertion of clock_jitter timing constraints; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation functional errors.
create_clock: referring to FIG. 23, RTL simulation behavior before and after insertion of the create_clock timing constraints is shown.
RTL simulation behavior without delay (upper part), no time delay indicated at (1); (2) the data is correctly captured; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower part), (1) represents random delay between different clock and is smaller than clock_period; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation functional errors.
data_check: referring to FIG. 24, RTL simulation behavior before and after insertion of a data_check timing constraint is shown.
RTL simulation behavior without delay (upper part), (1) indicates no time delay between multiple bits; (2) the data is correctly captured; (3) the sampling control circuit at this point is wrong, but the data still shows correct. The RTL simulation behavior without delay does not suffer from simulation functional errors even if the circuit or timing constraints are wrong.
The RTL simulation behavior (lower part) with delay (1) shows that random delay exists among different clocks and is smaller than clock_period; (2) the position grabs the data correctly; (3) where the data is grabbed in error. It can be seen that the RTL simulation behavior after adding the timing constraint destination behavior, the circuit or timing constraint errors may have simulation functional errors.
In summary, the present application can achieve the following technical effects:
the time sequence constraint can be verified by functional simulation, and the consistency and the correctness of the design and the constraint can be ensured; the timing verification is advanced from the subsequent gate-level netlist to the RTL stage of the preamble, so that the timing verification speed and efficiency are greatly improved;
the timing constraint (false_path) which cannot be checked (ignored) even by the back-end EDA tool can be checked, so that the timing constraint checked by the EDA tool can be checked by the front-end logic function simulation. What is called "shift left" in the industry, the original follow-up task is greatly advanced (at least 3 months in advance, and in fact, 6 to 12 months in advance);
After the function verification method is adopted, the simulation of the sequential reverse mark of the subsequent gate-level netlist can be canceled, so that the chip test precision and efficiency can be accelerated, and the construction period can be shortened;
the occupied resources and occupied time of the simulation server and the gate-level server are greatly reduced (the gate-level belt time sequence simulation requires multiple times or even tens times of the CPU and the memory to be increased, and the occupied time of the server is between 1 month and 3 months); thus, the server can be released to other critical tasks;
the traditional gate-level netlist with time sequence anti-standard simulation is easy to select few test cases (perhaps only 1 to 5 percent of the test cases are selected) because of the simulation speed and the server resource requirement, but the method can be used in all (100 percent of the test cases are selected) functional tests, and the checking coverage rate of time sequence constraints is greatly improved by combining random functions of each simulation, and the total coverage rate of the test cases can be up to or close to 100 percent through accumulation of different time periods and test sets.
The foregoing describes preferred embodiments of the present application; it is to be understood that the application is not limited to the specific embodiments described above, wherein devices and structures not described in detail are to be understood as being implemented in a manner common in the art; any person skilled in the art will make many possible variations and modifications, or adaptations to equivalent embodiments without departing from the technical solution of the present application, which do not affect the essential content of the present application; therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.

Claims (9)

1. A method for verifying timing constraint functions of an integrated circuit, the method comprising:
acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchy information and constraint mark point information in the time sequence constraint file, and extracting time sequence constraint destination information in the time sequence constraint file;
determining the file type of an original description file and a time sequence file modification tool thereof, modifying a target logic behavior of the original description file according to the circuit hierarchy structure information, the constraint mark point information and the time sequence constraint destination information to obtain a time sequence constraint logic device, and generating a time sequence constraint verification file with time sequence constraint delay information; the resulting sequential constraint logic device comprises:
converting time sequence constraint information into target delay simulation behavior information based on an uncombinable simulation logic statement behavir logic, and configuring the time sequence constraint logic according to the target delay simulation behavior information; the time sequence constraint logic at least comprises a delay buffer delay_buffer, a delay module delay_module and a behavir logic; inserting the configured time sequence constraint logic device between the starting point and/or the ending point of the constraint statement mark in the original description file, replacing delay information of the original circuit simulation, and not changing logic assignment transmission of the original circuit;
Performing logic function simulation and regression testing on the time sequence constraint verification file based on a random function in the test case, and verifying the constraint effect;
when the simulation or test result is wrong, modifying the time sequence constraint file or the time sequence constraint verification file according to the error item; and when the simulation and test results meet the requirements of the target logic behaviors, ending the test and executing the subsequent chip streaming procedure.
2. The method of claim 1, wherein the circuit hierarchy information, the constraint marker point information, and the timing constraint destination information are automatically extracted and validated by a timing constraint analysis tool or manually; the types of the time sequence constraint files at least comprise TCL, excel, YAML, JSON and HASH arrays; the original description file comprises an original RTL file and an original TB design file.
3. The method according to claim 2, wherein the constraint mark point information is a signal start point and/or an end point of constraint implementation and marking, and at least comprises multi-cycle time constraint multi_cycle_path information in a synchronous circuit, false path time constraint false_path information in an asynchronous circuit, minimum delay constraint min_delay information and maximum delay constraint max_delay information in a synchronous or asynchronous circuit, clock jitter information in synchronous and asynchronous circuits, clock skew information in synchronous and asynchronous circuits, clock creation create clock information in synchronous and asynchronous circuits, and data alignment data_check information in synchronous and asynchronous circuits;
The time sequence constraint destination information is the logic function behavior corresponding to the labeling signal.
4. A method according to claim 3, wherein generating a timing constraint verification file having timing constraint delay information comprises:
inserting the configured time sequence constraint logic into an original RTL file, and modifying target logic behaviors in the original RTL file to generate the time sequence constraint verification file;
or;
inserting the configured time sequence constraint logic into an original TB design file to generate a TB verification file; binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through force and/or bind and/or instance statement of HDL to generate the time sequence constraint verification file;
or;
generating independent TB verification file packages based on all the time sequence constraint logic; binding the independent TB verification file package with the starting point and/or the end point marked by the constraint statement in the original RTL file through force and/or bind and/or instance statement of HDL, and generating the time sequence constraint verification file;
the time sequence constraint delay information at least comprises delay information of multi_cycle_path, false_path, min_delay, max_delay, clock_jitter, clock_skew, create_clock and data_check.
5. The method of claim 4, wherein configuring the timing constraint logic comprises:
adding delay information to the timing constraint logic when the timing constraint information includes multi_cycle_path and the target delay emulation behavior information is multi_cycle_path between selected two target data; the delay information makes random selection within 0 and the time upper limit through a random function of the original description file, and generates delay corresponding to target duration from each bit between the data input data_in to the data output data_out of the time sequence constraint logic device according to different seed values of the random function;
when the timing constraint information includes a false_path and the target delay emulation behavior information is a false_path between two selected target data; adding delay information randomly selected from 0 and an upper time limit between the data_in and the data_out;
when the timing constraint information comprises max_delay and the target delay simulation behavior information is max_delay_val between two target data; adding delay information randomly selected from 0 and max_delay_val between data_in and data_out; wherein max_delay_val represents the delay upper limit duration;
When the time sequence constraint information comprises min_delay and the target delay simulation behavior information is min_delay_val between two target data; adding delay information randomly selected from min_delay_val and a time upper limit between the data_in and the data_out; wherein min_delay_val represents the delay lower limit duration; when the time sequence constraint delay information comprises min_delay and max_delay at the same time, adding delay information which is randomly selected from the min_delay and the max_delay between the data_in and the data_out;
when the timing constraint information includes clock_jitter, and the target delay emulation behavior information is jitter_val of target data; adding delay information randomly selected from between 0 and jitter_val between data_in and data_out; where jitter val represents the time duration of the upper limit of the clock jitter.
6. The method of claim 4, wherein the timing constraint information comprises clock_skew, and the target delay emulation behavior information is a skew_val of a target clock; adding the configured time sequence constraint logic device on a clock signal of a target clock, and adding delay information which is randomly selected between 0 and skew_val through a random function of the original description file between data_in and data_out of the time sequence constraint logic device; wherein, skew_val represents the clock deviation upper limit duration;
When the timing constraint information comprises create_clock and the target delay emulation behavior information is period_val of a new clock domain; adding the configured time sequence constraint logic device on a designated clock signal, and adding delay information which is randomly selected from 0 and period_val between data_in and data_out; wherein period_val represents the clock cycle duration;
when the timing constraint information includes data_check, and the target delay emulation behavior information is data_check_val between two target data signals; adding the configured time sequence constraint logic into the two target data signals respectively, and adding delay information randomly selected from 0 and data_check_val between data_in and data_out; wherein, data_check_val represents the data alignment upper limit duration.
7. The method of claim 5, wherein the timing constraint information comprises false_path and the target delay emulation behavior information is when a clock_jitter between at least two clock_domain clock domains, or an async asynchronous relationship between at least two clock_group clock groups, is selected; then the timing constraint delay information is inserted as the delay information of the clock jitter at the set source corresponding to the clock domain or the clock_group.
8. The method of claim 4, wherein performing logic function simulation and regression testing on the timing constraint verification file based on the random function in the test case comprises:
based on random function enabling, performing logic function simulation and regression testing on the time sequence constraint verification file and the original TB design file which are added into the time sequence constraint logic device, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, performing logic function simulation and regression testing on the time sequence constraint verification file formed by binding an original RTL file and the TB verification file package, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, logic function simulation and regression testing are carried out on a time sequence constraint verification file formed by binding an independent TB verification file packet with an original TB design file and the original RTL file, and the effectiveness of delay information is determined according to the delay time of an output signal.
9. The method of claim 8, wherein an internal logic error is determined when the delay time of the logic function simulation or regression testing process does not match the delay information;
When the error item indicates that the inserted RTL file or the TB file is in error, the modified time sequence constraint verification file is modified again according to the original RTL file or the original TB design file, and the simulation test is carried out again;
when the error item indicates that the time sequence constraint delay information is in error, the time sequence constraint file of the chip to be tested is modified and re-executed.
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CN116822450A (en) * 2023-06-27 2023-09-29 上海奎芯集成电路设计有限公司 Method for manufacturing on-line delay in verifying training process
CN116776793B (en) * 2023-08-22 2023-11-03 成都翌创微电子有限公司 Multi-period path constraint verification method combining static time sequence analysis and pre-simulation
CN117313604B (en) * 2023-11-30 2024-02-06 沐曦科技(成都)有限公司 Timing exception constraint checking method, device, system and storage medium

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104699473A (en) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 Timing constraint file generation method and device and RTL (Register Transfer Level) simulation equipment
CN107167725A (en) * 2017-03-30 2017-09-15 北京时代民芯科技有限公司 A kind of quick low overhead Full automatic digital integrated circuit single-particle fault injection system
CN110750956A (en) * 2018-07-23 2020-02-04 扬智科技股份有限公司 Logic gate level verification method and verification system
CN112000173A (en) * 2020-08-20 2020-11-27 天津飞腾信息技术有限公司 Method and system for checking multi-bit signal timing violation across clock domains
CN112232006A (en) * 2020-10-26 2021-01-15 海光信息技术股份有限公司 Standard cell library verification method and device, electronic equipment and storage medium
CN113486613A (en) * 2021-06-29 2021-10-08 海光信息技术股份有限公司 Data link extraction method and device, electronic equipment and storage medium
CN113487726A (en) * 2021-07-12 2021-10-08 北京未来天远科技开发有限公司 Motion capture system and method
CN115455873A (en) * 2022-09-14 2022-12-09 深存科技(无锡)有限公司 HDL code generation method supporting embedded scripting language

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104699473A (en) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 Timing constraint file generation method and device and RTL (Register Transfer Level) simulation equipment
CN107167725A (en) * 2017-03-30 2017-09-15 北京时代民芯科技有限公司 A kind of quick low overhead Full automatic digital integrated circuit single-particle fault injection system
CN110750956A (en) * 2018-07-23 2020-02-04 扬智科技股份有限公司 Logic gate level verification method and verification system
CN112000173A (en) * 2020-08-20 2020-11-27 天津飞腾信息技术有限公司 Method and system for checking multi-bit signal timing violation across clock domains
CN112232006A (en) * 2020-10-26 2021-01-15 海光信息技术股份有限公司 Standard cell library verification method and device, electronic equipment and storage medium
CN113486613A (en) * 2021-06-29 2021-10-08 海光信息技术股份有限公司 Data link extraction method and device, electronic equipment and storage medium
CN113487726A (en) * 2021-07-12 2021-10-08 北京未来天远科技开发有限公司 Motion capture system and method
CN115455873A (en) * 2022-09-14 2022-12-09 深存科技(无锡)有限公司 HDL code generation method supporting embedded scripting language

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