CN112000173A - Method and system for checking multi-bit signal timing violation across clock domains - Google Patents
Method and system for checking multi-bit signal timing violation across clock domains Download PDFInfo
- Publication number
- CN112000173A CN112000173A CN202010843322.8A CN202010843322A CN112000173A CN 112000173 A CN112000173 A CN 112000173A CN 202010843322 A CN202010843322 A CN 202010843322A CN 112000173 A CN112000173 A CN 112000173A
- Authority
- CN
- China
- Prior art keywords
- clock
- checking
- clock domain
- domain
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a method and a system for checking the time sequence violation of a multi-bit signal across clock domains, wherein the method comprises the following steps: acquiring all time sequence checking end angles; and traversing in all the signing and checking corners, and executing the following processing every time one current signing and checking corner is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different clock groups are removed, and internal time sequence of a clock domain is not checked; establishing clock groups crossing clock domains, and setting different timing sequence check constraints on multi-bit control and data signals respectively; all clock-domain-crossing clock packets are subjected to setup and hold time violation checking of the control and data signals. And outputting a clock domain crossing signal timing checking result. The invention is used for ensuring the correct clock domain crossing signal transmission function in the process of checking the clock domain crossing signal timing sequence, does not expose a large number of false clock domain crossing signal timing sequence violation problems due to the over-constraint problem, and avoids repairing a large number of buffers inserted by the timing sequence violation.
Description
Technical Field
The invention belongs to a clock domain crossing signal timing analysis and inspection technology in the field of digital integrated circuit design, and particularly relates to a method and a system for inspecting clock domain crossing multi-bit signal timing violation.
Background
As is well known, a plurality of clock domains exist in an soc (system on chip), and a signal transmission circuit between two clock domains with different frequencies or an uncertain phase relationship is called a clock domain crossing circuit. Such as master and generator clocks, asynchronous clocks, I/O interfaces. Due to the fact that the arrival time of the signals transmitted across the clock domain has the characteristic of uncertainty, the sampling signals cannot be guaranteed to be kept stable before the rising edge or the falling edge of the target clock arrives, and therefore violation of the setup time and the holding time of the sampling register is caused. This instability (i.e., metastability) often causes unexpected errors and disturbances in the circuitry that render the system inoperable. The traditional method for checking the time sequence of the clock domain crossing circuit uniformly restricts a source clock period value with a fixed percentage as the maximum time delay according to the combination of different process end angles, different voltages and different temperatures, and takes zero time delay as the minimum time delay; and calculating whether the sampling of the cross-clock domain signal meets the maximum delay and the minimum delay constraint by using a static timing analysis tool. Because a fixed percentage of source clock period value constraints are set for timing inspection of different clock domain crossing circuits, inspection of certain clock domain crossing signals is inevitably too strict, and a large number of buffers are additionally inserted to reduce transmission delay of the clock domain crossing signals. Meanwhile, the static timing analysis checks the setup time and hold time violations under the constraints of maximum delay and minimum delay of the clock domain crossing signal paths, and the clock network delay deviation between the source clock and the destination clock is calculated, so that a large number of false violation paths appear. Meanwhile, the conventional cross-clock domain inspection method not only wastes chip area, but also increases chip power consumption.
In the process of checking the time of the clock domain crossing signal, how to ensure the correct transmission function of the clock domain crossing signal can be ensured, a large number of false clock domain crossing signal time sequence violation problems can not be exposed due to the over-constraint problem, and the problem that a large number of buffers inserted for repairing the time sequence violation are engineering problems which must be considered by a chip physical designer is avoided.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, a method and a system for checking the time sequence violation of a clock domain crossing multi-bit signal are provided, which are used for ensuring that the clock domain crossing signal transmission function is correct in the process of checking the time of the clock domain crossing signal, avoiding exposing a large number of false clock domain crossing signal time sequence violation problems due to over-constraint problems, and avoiding repairing a large number of buffers inserted in the time sequence violation.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method of checking for a timing violation of a multi-bit signal across a clock domain, comprising the steps of:
1) acquiring all time sequence checking end angles;
2) and traversing in all the signing and checking corners, and executing the following processing every time one current signing and checking corner is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
3) and outputting a clock domain crossing signal timing checking result.
Optionally, the step of calculating the average clock insertion delay of each clock domain named feature timing unit in step 2) includes:
2.1A) acquiring all real clocks aiming at the current signing and checking end angle, wherein each real clock corresponds to a clock domain;
2.2A) for each clock domain: firstly, capturing a clock input end of a corresponding named feature time sequence unit under each clock domain according to the characteristics of keywords in the naming of the logic structure time sequence unit of the clock domain crossing, and calculating to obtain the clock insertion delay of the corresponding named feature time sequence unit under each clock domain; then according to all under the clock domainnSumming the clock insertion delays of the corresponding named feature timing units to obtain a total clock insertion delay; and divides the total clock insertion delay bynObtaining the average clock insertion delay under the clock domain;
2.3A) setting clock source insertion delay for each real clock, wherein the set clock source insertion delay value is the negative average clock insertion delay under the clock domain.
Optionally, the step 2) of removing the asynchronous constraint between different time packets further includes setting a false path for each clock domain internal timing path.
Optionally, the step of setting different timing check constraints on the multi-bit control and data signals grouped across clock domains in step 2) includes:
2.1B) aiming at the current signing and checking end angle, obtaining a start clock and an end clock of the cross-clock domain signal by utilizing the naming characteristic of the characteristic cross-clock domain signal, and establishing a cross-clock domain clock group by the combination of the start clock and the end clock;
2.2B) setting one beat of source clock period value as maximum delay check constraint and zero delay as minimum delay check constraint for multi-bit control signals under each clock group; and setting a clock period value of two beats as a maximum delay check constraint and setting zero delay as a minimum delay check constraint for the multi-bit data signals of each clock group.
Optionally, the step of performing control and data signal setup and hold time violation checking on all clock packets crossing the clock domain in step 2) includes:
2.1C) acquiring all clock groups crossing the clock domain aiming at the current signing and checking end corner;
2.2C) traversing and selecting a current clock packet from all clock packet spanning the clock domains, calculating the establishment time margin and the retention time margin of a multi-bit control signal and a multi-bit data signal by considering the deviation on a process chip and the clock jitter aiming at the current clock packet spanning the clock domain, and calculating the sum of the establishment time margin and the retention time margin of the multi-bit control signal and the data signal under the current clock packet spanning the clock domains;
2.3C) judging whether the sum of the establishment time margin and the retention time margin is greater than or equal to 0, and if so, judging that the current clock domain crossing clock grouping time sequence inspection is passed; otherwise, judging that the current clock packet time sequence inspection crossing the clock domain does not pass, and reporting a specific violation path under the clock packet;
2.4C) judging whether all clock packets crossing the clock domain are traversed completely, and if not, skipping to execute the step 2.2C); otherwise, skipping to execute the step 3).
Optionally, the step of calculating the setup time margin and the hold time margin of the multi-bit control signal and the multi-bit data signal in step 2.2C) in consideration of the on-chip deviation of the process and the jitter of the clock comprises: calculating the time of the source end of the source clock reaching the clock input end of the starting register as the insertion delay of the sending clock; calculating the time from the start register to the clock input end to the data input end of the end register as the data path delay; calculating the time of the source end of the target clock reaching the clock input end of the destination register as the capture clock insertion delay; calculating a maximum delay constraint value of the multi-bit signal and adding a capture clock insertion delay, and subtracting a clock jitter value, a terminal register establishing time, a sending clock insertion delay and a data path delay to obtain an establishing time margin; and calculating the insertion delay of the sending clock and the delay of the data path, and subtracting the minimum delay constraint value of the multi-bit signal, the clock jitter value, the holding time of the end point register and the insertion delay of the capture clock to obtain a holding time margin.
In addition, the present invention also provides a system for checking a timing violation of a multi-bit signal across a clock domain, comprising:
an end angle acquisition program unit for acquiring all timing sequence signing end angles;
and the end angle traversing program unit is used for traversing in all the signing end angles, and executing the following processing every time one current signing end angle is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
and the result output program unit is used for outputting the clock domain crossing signal timing sequence checking result.
Furthermore, the present invention also provides a system for checking timing violations of clock domain crossing multi-bit signals, comprising a computer device programmed or configured to perform the steps of the method for checking timing violations of clock domain crossing multi-bit signals.
Furthermore, the present invention also provides a system for checking a timing violation of a clock domain crossing multi-bit signal, comprising a computer device having stored in a memory thereof a computer program programmed or configured to perform the method for checking a timing violation of a clock domain crossing multi-bit signal.
Furthermore, the present invention also provides a computer readable storage medium having stored therein a computer program programmed or configured to perform the method of checking a timing violation of a multi-bit signal across a clock domain.
Compared with the prior art, the invention has the following advantages: the invention respectively sets a source clock period value and a target clock period value of two beats as the maximum delay check constraint of the multi-bit control signal and the data signal for each clock-domain-crossing clock group, and uses zero delay as the minimum delay check constraint. And calculating a multi-bit control signal and data signal establishing time margin and a holding time margin under each clock group of the clock domain crossing aiming at the CMOS logic circuit and the interconnection line under different signing end angles, and judging whether the clock group of the clock domain crossing passes through the clock domain crossing time sequence inspection or not according to the sum of the establishing time margin and the holding time margin. The method greatly reduces a large amount of false clock domain crossing signal time sequence violations caused by inaccurate checking constraints and defects of a checking method, avoids the insertion of a large amount of buffer units, and simultaneously provides an excellent scheme for quick checking iteration of clock domain crossing signal time sequence analysis.
Drawings
In order that the manner in which the above recited and other aspects of the present invention are obtained can be readily understood, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings.
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Fig. 2 is a design circuit example of the embodiment of the present invention.
FIG. 3 is a schematic diagram of a basic flow of step 6) of the method according to the embodiment of the present invention.
Detailed Description
As shown in fig. 1, the method for checking a timing violation of a multi-bit signal across clock domains of the present embodiment includes the following steps:
1) acquiring all timing sequence checking end angles (signoff end angles);
2) and traversing in all the signing and checking corners, and executing the following processing every time one current signing and checking corner is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
3) and outputting a clock domain crossing signal timing checking result.
Step 1) cross-clock domain timing analysis is associated with chip manufacturing process and working conditions so as to truly reflect the actual working behavior of the cross-clock domain circuit. As known to semiconductor practitioners, the timing characteristics of CMOS circuits vary under different PVTs (Process, Voltage, Temperature), and the cross-clock domain signal timing inspection is not sufficient under only one PVT condition. Therefore, the purpose of listing all timing signoff corners in step 1) is to ensure that the timing requirements of the cross-clock domain signal timing analysis can be met under each process corner. When all the signing and checking end corners are obtained in the step 1), all the time sequence signing and checking end corners can be listed based on the foundry process and the chip working conditions.
Step 2) is used for calculating the average clock insertion delay of the corresponding naming characteristic time sequence unit in each clock domain according to the naming characteristics of the time sequence unit of the cross-clock domain logic structure aiming at each signing and checking end corner, and setting the clock source insertion delay for each clock; the step of calculating the average clock insertion delay of each clock domain named feature timing unit in the step 2) comprises the following steps:
2.1A) acquiring all real clocks aiming at the current signing and checking end angle, wherein each real clock corresponds to a clock domain;
2.2A) for each clock domain: firstly, the clock input end of the corresponding named feature time sequence unit under each clock domain is captured according to the key character in the naming of the logic structure time sequence unit of the clock domain crossing, the clock insertion delay of the corresponding named feature time sequence unit under each clock domain is calculated and recorded asclock_latency(ii) a Then according to all under the clock domainnOf corresponding named feature timing unitsclock_latencyThe summation yields the total clock insertion delay, notedtotal_clock_ latency(ii) a And will betotal_clock_latencyIs divided bynGet the average clock insertion delay under this clock domain, denotedaverage_clock_latency(ii) a The functional expression of the above calculation process is:
2.3A) setting a clock source insertion delay for each real clock, wherein the set clock source insertion delay value is negative in the clock domainaverage_clock_latency。
In this embodiment, the step 2) of removing the asynchronous constraint between different time packets further includes setting a false path for the internal timing path of each clock domain.
Fig. 2 is a logic structure diagram of a fifo body of a cross-clock domain, which is used for converting signals of the cross-clock domain, and a fifo data body is built by using registers. In the figure, the structure of the key reg _ memory is the start of the clock domain crossing multi-bit data signal (data _ out), and the registers with the keys gray _ wptr and gray _ rptr are the start of the clock domain crossing multi-bit pointer signal. It can also be seen from fig. 2 that the pointer signal is synchronized by the two stages of registers and then the reproduction signal is generated, so that the time timing check constraints are established across the clock domains of the multi-bit pointer signal and the multi-bit data signal, respectively, one beat of the source clock cycle and two beats of the destination clock cycle. In this embodiment, the step of setting different timing inspection constraints for the multi-bit control and data signals under the clock domain crossing clock grouping in step 2) includes:
2.1B) aiming at the current signing and checking end angle, obtaining a start clock and an end clock of the cross-clock domain signal by utilizing the naming characteristic of the characteristic cross-clock domain signal, and establishing a cross-clock domain clock group by the combination of the start clock and the end clock;
2.2B) setting one beat of source clock period value as maximum delay check constraint and zero delay as minimum delay check constraint for multi-bit control signals under each clock group; and setting a clock period value of two beats as a maximum delay check constraint and setting zero delay as a minimum delay check constraint for the multi-bit data signals of each clock group.
In step 2), performing control and data signal setup and hold time violation checking on all clock domain crossing clock groups is used to calculate, for each core-end corner, a setup time margin and a hold time margin (slack) of a multi-bit control signal and a data signal in each clock domain crossing clock group, respectively. For each clock packet across the clock domain, if the sum of the setup time margin and the hold time margin of the multi-bit control signal and the data signal under the packet is greater than or equal to zero, the packet timing check is passed; otherwise, the packet timing check fails, and then a specific violation path is reported. As shown in fig. 3, the step of performing control and setup and hold time violation checking on all clock packets across clock domains in step 2) of this embodiment includes:
2.1C) acquiring all clock groups crossing the clock domain aiming at the current signing and checking end corner;
2.2C) traversing and selecting a current clock-domain-crossing clock group from all clock-domain-crossing clock groups, calculating the establishment time margin and the holding time margin of a multi-bit control signal and a multi-bit data signal by considering the on-chip deviation (OCV) and the clock jitter (jitter) of the current clock-domain-crossing clock group, and calculating the sum of the establishment time margin and the holding time margin of the multi-bit control signal and the data signal under the current clock-domain-crossing clock group;
2.3C) judging whether the sum of the establishment time margin and the retention time margin is greater than or equal to 0, and if so, judging that the current clock domain crossing clock grouping time sequence inspection is passed; otherwise, judging that the current clock packet time sequence inspection crossing the clock domain does not pass, and reporting a specific violation path under the clock packet;
2.4C) judging whether all clock packets crossing the clock domain are traversed completely, and if not, skipping to execute the step 2.2C); otherwise, skipping to execute the step 3).
In this embodiment, the step 2.2C) of calculating the setup time margin and the hold time margin of the multi-bit control signal and the multi-bit data signal in consideration of the on-chip deviation of the process and the jitter of the clock includes: calculating the time of the source end of the source clock reaching the clock input end of the starting register as the insertion delay of the sending clock; calculating the time from the start register to the clock input end to the data input end of the end register as the data path delay; calculating the time of the source end of the target clock reaching the clock input end of the destination register as the capture clock insertion delay; calculating a maximum delay constraint value of the multi-bit signal and adding a capture clock insertion delay, and subtracting a clock jitter value, a terminal register establishing time, a sending clock insertion delay and a data path delay to obtain an establishing time margin; and calculating the insertion delay of the sending clock and the delay of the data path, and subtracting the minimum delay constraint value of the multi-bit signal, the clock jitter value, the holding time of the end point register and the insertion delay of the capture clock to obtain a holding time margin.
In summary, the method for checking timing violations of clock domain crossing multi-bit signals of the present embodiment has the following advantages:
1. in the embodiment, the clock domain crossing timing sequence inspection is only performed on the multi-bit control signal and the multi-bit data signal, and a single signal does not have the clock domain crossing timing sequence inspection requirement, so that the timing sequence inspection of the clock domain crossing signal is accelerated.
2. In the embodiment, the clock deviation of the clock packet where the clock domain crossing multi-bit signal is located is removed in the process of analyzing the time sequence of the clock domain crossing signal. It is ensured that the multi-bit signal setup and hold time check only takes into account the relative deviation of the clocks, i.e. the clock insertion delay before the multi-bit register branch point is not calculated.
3. In this embodiment, different setup time sequence check constraint values are respectively set for the multi-bit control signal and the data signal according to the implementation manner of the clock domain crossing circuit structure, so that pessimistic time sequence analysis caused by setting a uniform check constraint for the signal by the conventional clock domain crossing time sequence check is avoided.
4. In the embodiment, on-chip deviation and clock jitter of a chip manufacturing process are considered, timing analysis is carried out according to a timing signoff specification recommended by foundry, and the influence of reserving a certain timing margin to replace the former is avoided, so that the accuracy of the clock domain crossing signal timing analysis is ensured.
5. The embodiment judges whether the clock domain crossing multi-bit signal time sequence check passes or not by calculating the sum of the setup time margin and the hold time margin of the multi-bit control signal and the multi-bit data signal, replaces the effect which can be achieved by adjusting the sampling window of the multi-bit signal before, and simultaneously ensures that the multi-bit data signal arrives earlier than the effective control signal.
In addition, the present embodiment further provides a system for checking a timing violation of a multi-bit signal across clock domains, including:
an end angle acquisition program unit for acquiring all timing sequence signing end angles;
and the end angle traversing program unit is used for traversing in all the signing end angles, and executing the following processing every time one current signing end angle is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
and the result output program unit is used for outputting the clock domain crossing signal timing sequence checking result.
Furthermore, the present invention also provides a system for checking a timing violation of a clock domain crossing multi-bit signal, comprising a computer device programmed or configured to perform the steps of the aforementioned method for checking a timing violation of a clock domain crossing multi-bit signal.
Furthermore, the present invention also provides a system for checking a timing violation of a clock domain crossing multi-bit signal, comprising a computer device having stored in a memory thereof a computer program programmed or configured to perform the aforementioned method for checking a timing violation of a clock domain crossing multi-bit signal.
Furthermore, the present invention also provides a computer readable storage medium having stored therein a computer program programmed or configured to perform the aforementioned method of checking a timing violation of a multi-bit signal across a clock domain.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A method for checking for a timing violation of a multi-bit signal across a clock domain, comprising the steps of:
1) acquiring all time sequence checking end angles;
2) and traversing in all the signing and checking corners, and executing the following processing every time one current signing and checking corner is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
3) and outputting a clock domain crossing signal timing checking result.
2. The method of checking timing violations of a multi-bit signal across clock domains as recited in claim 1, wherein the step of calculating an average clock insertion delay for each clock domain named feature timing unit in step 2) comprises:
2.1A) acquiring all real clocks aiming at the current signing and checking end angle, wherein each real clock corresponds to a clock domain;
2.2A) for each clock domain: firstly, capturing a clock input end of a corresponding named feature time sequence unit under each clock domain according to the characteristics of keywords in the naming of the logic structure time sequence unit of the clock domain crossing, and calculating to obtain the clock insertion delay of the corresponding named feature time sequence unit under each clock domain; then according to all under the clock domainnSumming the clock insertion delays of the respective named feature timing units to obtain a total clock insertion delayDelay; and divides the total clock insertion delay bynObtaining the average clock insertion delay under the clock domain;
2.3A) setting clock source insertion delay for each real clock, wherein the set clock source insertion delay value is the negative average clock insertion delay under the clock domain.
3. The method of claim 1, wherein removing asynchronous constraints between different time packets in step 2) further comprises setting a false path for each clock domain internal timing path.
4. The method of checking timing violations of multi-bit signals across clock domains as claimed in claim 1, wherein the step of setting different timing checking constraints for the multi-bit control and data signals under clock-domain clock grouping in step 2) comprises:
2.1B) aiming at the current signing and checking end angle, obtaining a start clock and an end clock of the cross-clock domain signal by utilizing the naming characteristic of the characteristic cross-clock domain signal, and establishing a cross-clock domain clock group by the combination of the start clock and the end clock;
2.2B) setting one beat of source clock period value as maximum delay check constraint and zero delay as minimum delay check constraint for multi-bit control signals under each clock group; and setting a clock period value of two beats as a maximum delay check constraint and setting zero delay as a minimum delay check constraint for the multi-bit data signals of each clock group.
5. The method of claim 1, wherein the step of performing control and setup and hold time violation checking on all clock-domain crossing clock packets in step 2) comprises:
2.1C) acquiring all clock groups crossing the clock domain aiming at the current signing and checking end corner;
2.2C) traversing and selecting a current clock packet from all clock packet spanning the clock domains, calculating the establishment time margin and the retention time margin of a multi-bit control signal and a multi-bit data signal by considering the deviation on a process chip and the clock jitter aiming at the current clock packet spanning the clock domain, and calculating the sum of the establishment time margin and the retention time margin of the multi-bit control signal and the data signal under the current clock packet spanning the clock domains;
2.3C) judging whether the sum of the establishment time margin and the retention time margin is greater than or equal to 0, and if so, judging that the current clock domain crossing clock grouping time sequence inspection is passed; otherwise, judging that the current clock packet time sequence inspection crossing the clock domain does not pass, and reporting a specific violation path under the clock packet;
2.4C) judging whether all clock packets crossing the clock domain are traversed completely, and if not, skipping to execute the step 2.2C); otherwise, skipping to execute the step 3).
6. The method for checking timing violation of multi-bit signals across clock domains according to claim 5, wherein the step of calculating setup and hold time margins of the multi-bit control signal and the multi-bit data signal in step 2.2C) taking into account on-chip variations, clock jitter comprises: calculating the time of the source end of the source clock reaching the clock input end of the starting register as the insertion delay of the sending clock; calculating the time from the start register to the clock input end to the data input end of the end register as the data path delay; calculating the time of the source end of the target clock reaching the clock input end of the destination register as the capture clock insertion delay; calculating a maximum delay constraint value of the multi-bit signal and adding a capture clock insertion delay, and subtracting a clock jitter value, a terminal register establishing time, a sending clock insertion delay and a data path delay to obtain an establishing time margin; and calculating the insertion delay of the sending clock and the delay of the data path, and subtracting the minimum delay constraint value of the multi-bit signal, the clock jitter value, the holding time of the end point register and the insertion delay of the capture clock to obtain a holding time margin.
7. A system for checking timing violations of a multi-bit signal across a clock domain, comprising:
an end angle acquisition program unit for acquiring all timing sequence signing end angles;
and the end angle traversing program unit is used for traversing in all the signing end angles, and executing the following processing every time one current signing end angle is traversed: calculating the average clock insertion delay of each clock domain named feature time sequence unit; asynchronous constraints among different time packets are removed, and the internal time sequence of a clock domain is not checked; setting different timing inspection constraints on multi-bit control and data signals under clock domain crossing clock grouping; carrying out control and data signal establishment and holding time violation inspection on all clock groups crossing the clock domain;
and the result output program unit is used for outputting the clock domain crossing signal timing sequence checking result.
8. A system for checking timing violations of a cross-clock domain multi-bit signal, comprising a computer device, wherein the computer device is programmed or configured to perform the steps of the method for checking timing violations of a cross-clock domain multi-bit signal of any of claims 1-6.
9. A system for checking timing violations of clock domain crossing multi-bit signals, comprising a computer device, wherein a computer program programmed or configured to perform the method of checking timing violations of clock domain crossing multi-bit signals of any of claims 1-6 is stored in a memory of the computer device.
10. A computer-readable storage medium having stored thereon a computer program programmed or configured to perform the method of checking a timing violation of a multi-bit signal across a clock domain of any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010843322.8A CN112000173B (en) | 2020-08-20 | 2020-08-20 | Method and system for checking multi-bit signal timing violation across clock domains |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010843322.8A CN112000173B (en) | 2020-08-20 | 2020-08-20 | Method and system for checking multi-bit signal timing violation across clock domains |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112000173A true CN112000173A (en) | 2020-11-27 |
| CN112000173B CN112000173B (en) | 2022-03-29 |
Family
ID=73472243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010843322.8A Active CN112000173B (en) | 2020-08-20 | 2020-08-20 | Method and system for checking multi-bit signal timing violation across clock domains |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112000173B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580283A (en) * | 2020-12-23 | 2021-03-30 | 海光信息技术股份有限公司 | Control method and device of cross-clock-domain model checker and electronic equipment |
| CN112783065A (en) * | 2021-01-08 | 2021-05-11 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
| CN113191112A (en) * | 2021-03-25 | 2021-07-30 | 西安紫光国芯半导体有限公司 | Clock tree planning method of chip and chip |
| CN113297819A (en) * | 2021-06-22 | 2021-08-24 | 海光信息技术股份有限公司 | Asynchronous clock timing sequence checking method and device, electronic equipment and storage medium |
| CN114519318A (en) * | 2022-02-15 | 2022-05-20 | 海光信息技术股份有限公司 | NOC design method, NOC design device, related devices and equipment |
| CN115935866A (en) * | 2022-12-27 | 2023-04-07 | 深存科技(无锡)有限公司 | Verification method for integrated circuit time sequence constraint function |
| CN115983171A (en) * | 2023-03-17 | 2023-04-18 | 摩尔线程智能科技(北京)有限责任公司 | Method and simulation platform for post-simulation of system on chip |
| CN117436402A (en) * | 2023-11-01 | 2024-01-23 | 上海合芯数字科技有限公司 | Cross-voltage-domain time sequence path analysis method, device, medium and terminal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN106407489A (en) * | 2015-07-31 | 2017-02-15 | 展讯通信（上海）有限公司 | Timing constraint checking method |
| CN110007713A (en) * | 2019-04-16 | 2019-07-12 | 中国人民解放军国防科技大学 | Time sequence checking method and system for dynamically adjusting checking parameters of clock domain crossing signals |
| CN112241615A (en) * | 2020-10-09 | 2021-01-19 | 广芯微电子（广州）股份有限公司 | Method and system for detecting data balance time sequence and electronic equipment |
-
2020
- 2020-08-20 CN CN202010843322.8A patent/CN112000173B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN106407489A (en) * | 2015-07-31 | 2017-02-15 | 展讯通信（上海）有限公司 | Timing constraint checking method |
| CN110007713A (en) * | 2019-04-16 | 2019-07-12 | 中国人民解放军国防科技大学 | Time sequence checking method and system for dynamically adjusting checking parameters of clock domain crossing signals |
| CN112241615A (en) * | 2020-10-09 | 2021-01-19 | 广芯微电子（广州）股份有限公司 | Method and system for detecting data balance time sequence and electronic equipment |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580283B (en) * | 2020-12-23 | 2022-04-29 | 海光信息技术股份有限公司 | Control method and device of cross-clock-domain model checker and electronic equipment |
| CN112580283A (en) * | 2020-12-23 | 2021-03-30 | 海光信息技术股份有限公司 | Control method and device of cross-clock-domain model checker and electronic equipment |
| CN112783065A (en) * | 2021-01-08 | 2021-05-11 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
| CN112783065B (en) * | 2021-01-08 | 2022-01-28 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
| CN113191112A (en) * | 2021-03-25 | 2021-07-30 | 西安紫光国芯半导体有限公司 | Clock tree planning method of chip and chip |
| CN113297819B (en) * | 2021-06-22 | 2023-07-07 | 海光信息技术股份有限公司 | Timing sequence checking method and device of asynchronous clock, electronic equipment and storage medium |
| CN113297819A (en) * | 2021-06-22 | 2021-08-24 | 海光信息技术股份有限公司 | Asynchronous clock timing sequence checking method and device, electronic equipment and storage medium |
| CN114519318A (en) * | 2022-02-15 | 2022-05-20 | 海光信息技术股份有限公司 | NOC design method, NOC design device, related devices and equipment |
| CN114519318B (en) * | 2022-02-15 | 2024-04-09 | 海光信息技术股份有限公司 | NOC design method, device, related device and equipment |
| CN115935866A (en) * | 2022-12-27 | 2023-04-07 | 深存科技(无锡)有限公司 | Verification method for integrated circuit time sequence constraint function |
| CN115935866B (en) * | 2022-12-27 | 2023-12-08 | 深存科技(无锡)有限公司 | Method for verifying time sequence constraint function of integrated circuit |
| CN115983171A (en) * | 2023-03-17 | 2023-04-18 | 摩尔线程智能科技(北京)有限责任公司 | Method and simulation platform for post-simulation of system on chip |
| CN117436402A (en) * | 2023-11-01 | 2024-01-23 | 上海合芯数字科技有限公司 | Cross-voltage-domain time sequence path analysis method, device, medium and terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112000173B (en) | 2022-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112000173B (en) | Method and system for checking multi-bit signal timing violation across clock domains | |
| US9547732B2 (en) | Static checking of asynchronous clock domain crossings | |
| WO2017016178A1 (en) | Interface signal remapping method based on fpga | |
| US10999050B1 (en) | Methods and apparatus for data synchronization in systems having multiple clock and reset domains | |
| JPH0329438A (en) | Digital data transfer circuit | |
| CN114997087B (en) | Clock tree optimization method, optimization device and related equipment | |
| US20090271747A1 (en) | Logic circuit designing device, logic circuit designing method and logic circuit designing program for asynchronous logic circuit | |
| US9449127B1 (en) | System for verifying timing constraints of IC design | |
| US7735032B2 (en) | Early HSS Rx data sampling | |
| Kapschitz et al. | Formal verification of synchronizers | |
| KR102129649B1 (en) | Automatic clock tree synthesis exceptions generation | |
| Garg | Common path pessimism removal: An industry perspective: Special session: Common path pessimism removal | |
| WO2022037638A1 (en) | Integrated circuit reset method and integrated circuit | |
| US20080069277A1 (en) | Method and apparatus for modeling signal delays in a metastability protection circuit | |
| CN115455880A (en) | Time sequence path screening method and equipment | |
| US7840925B1 (en) | Source specific timing checks on synchronous elements using a static timing analysis engine | |
| US7982502B2 (en) | Asynchronous circuit representation of synchronous circuit with asynchronous inputs | |
| WO2022021091A1 (en) | Clock tree architecture, and clock signal transmission method and device | |
| Huemer et al. | Timing domain crossing using Muller pipelines | |
| Poornima et al. | Functional verification of clock domain crossing in register transfer level | |
| US20070258300A1 (en) | Functional verification of synchronized signals using random delays | |
| US8959398B2 (en) | Multiple clock domain debug capability | |
| Pandit et al. | Clock Domain Crossing—Design, Verification and Sign-Off | |
| JP2000011031A (en) | Device and method for verifying logical circuit in semiconductor integrated circuit | |
| Curzon et al. | Improving hardware designs whilst simplifying their proof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant after: Feiteng Information Technology Co.,Ltd. Address before: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant before: TIANJIN FEITENG INFORMATION TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |