CN115932739A

CN115932739A - General Signal Processing System for Marine Radar

Info

Publication number: CN115932739A
Application number: CN202211692722.9A
Authority: CN
Inventors: 高琦; 王登峰; 王梦; 翁博; 黄艺; 刘婧芳; 刘嘉琦; 何建龙; 罗悦; 张沂洁
Original assignee: Shaanxi Changling Electronic Technology Co ltd
Current assignee: Shaanxi Changling Electronic Technology Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-04-07

Abstract

The invention discloses a general signal processing system for a marine radar, which mainly solves the problems of various board cards, complex structure and low reliability of the conventional general processing platform. It mainly comprises a signal processing board and a comprehensive bottom board. The signal processing board includes: the device comprises an FPGA module, a DSP module, 3 ADC chips, 2 DAC chips, a DDS chip, a debugging port and a VPX interface; this synthesize bottom plate includes: 2-slot VPX socket, power supply socket, change-over switch, communication socket, time sequence control socket and optical module. The modules and the circuits respectively complete the functions of power supply, processing and switching of the two signal processing boards, intermediate frequency echo acquisition, target identification and sum-difference processing. The invention enhances the reliability and the universality of the system, reduces the maintenance difficulty of the system, and can be used for a primary radar system and a secondary radar system for a ship.

Description

General signal processing system for marine radar

Technical Field

The invention belongs to the technical field of radars, and particularly relates to a general signal processing system for a marine radar, which can be used for target detection and positioning.

Background

Radar is a traditional radio navigation device that uses electromagnetic waves to find objects and determine their position, velocity and other characteristics, and functions in positioning ships offshore, guiding ships to enter and exit ports, navigating narrow channels, and avoiding collisions, and can also be used to guide aircraft to land safely or to land on ships under complex weather conditions. The method is divided into a primary radar and a secondary radar according to different modes of receiving target echoes after the radar transmits electric waves. The primary radar receives the target transmitting echo, and the secondary radar receives the radiated electric wave forwarded by the transponder on the target. The marine radar has become a necessary device for ensuring the safety of ship navigation.

Patent document CN105974365A discloses a general radar signal processing platform, which is composed of a communication board, a timing board, an interface board I, an interface board ii, a processing board, a signal source board, and a chassis to realize integrated management of signal processing and monitoring, but the general processing platform has various board cards, a complex structure, and low reliability.

Along with the continuous development of integrated circuits, the modern marine radar system has high requirements on the reliability of the system, and the types and the number of board cards are expected to be reduced as much as possible while the functions of different radar signal processing systems are completed.

Disclosure of Invention

The invention aims to provide a general signal processing system for a marine radar, which aims to solve the problems of various board cards, complex structure and low reliability of the traditional general processing platform, improve the working performance of the radar and the integration level of the radar system, perfect the self-checking function and facilitate maintenance.

In order to achieve the above object, the general signal processing system of the present invention comprises a signal processing board and a comprehensive bottom board, and is characterized in that:

the comprehensive bottom plate comprises a 2-slot VPX socket, a power supply socket, a change-over switch, a communication socket, a time sequence control socket and an optical module;

the device comprises two signal processing boards, a debugging interface and a VPX interface, wherein each signal processing board is provided with a lockable and quick plug-pull structure and comprises an FPGA module, a DSP module, an ADC chip, a DAC chip, a DDS chip, the debugging interface and the VPX interface, and the DSP module, the ADC chip, the DAC chip and the DDS chip are all connected with the FPGA module; each can be locked and quickly plugged

The two signal processing boards are respectively installed on a 2-slot VPX socket of the comprehensive bottom plate, the two signal processing boards are respectively supplied with power through switch switching, serial port communication between the two signal processing boards and an upper computer is realized through the communication socket, time sequence control of the upper computer on the two signal processing boards is realized through the time sequence control socket, and optical fiber communication between the two signal processing boards and the upper computer is realized through the optical module.

Furthermore, the FPGA module comprises an FPGA chip and peripheral DDR3 memories thereof, a configuration starting Flash, an SPIFlash, a serial port interface, LVDS and LVTTL discrete interfaces and clock sources, wherein the number of the DDR3 memories is four, and the DDR3 memories are used for expanding the external storage space of the FPGA chip; the configuration starts Flash for solidifying the program code of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified, and the SPIFlash is used for the communication between the FPGA chip and an external SPI device.

Furthermore, the DSP module comprises a DSP chip and a peripheral DDR3 memory thereof, a configuration starting Flash, an SPI Flash, an Ethernet interface, a serial port interface and a clock source; the DDR3 memories are four and used for expanding the external storage space of the FPGA chip; the configuration starts SPIFlash which is used for solidifying the program codes of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified; the SPIFlash is used for the communication between the DSP chip and an external SPI device.

Furthermore, the number of the ADC chips is 3, and the ADC chips are used for receiving commands of the FPGA module to complete echo sampling; the number of the DAC chips is 2, and the DAC chips are used for receiving signals of the FPGA module after selecting DDS, pulse pressure and MTD and directly converting the signals into analog signals to be output; the DDS chip is used for receiving parameters such as frequency control words, phase control codes and phase control addresses of the FPGA module and generating a required intermediate frequency waveform; the debugging port is used for debugging and testing the DSP module and the FPGA module; and the VPX interface is used for connecting the comprehensive bottom plate, supplying power for the DSP module and the FPGA module and communicating with the outside.

Furthermore, an SRIO interface of the DSP chip in the DSP module is directly interconnected with an MGT pipe orifice of the FPGA chip in the FPGA module; the EMIF interface is directly interconnected with 1.8VBank of an FPGA chip in the FPGA module; the 16 bidirectional GPIO pins are directly interconnected with the pipe orifices of the FPGA chip in the FPGA module;

furthermore, an LVDS interface in the ADC chip is directly interconnected with an LVDS interface of the FPGA chip so as to output a differential LVDS signal to the FPGA module after the AD chip finishes echo sampling;

furthermore, an LVDS interface and an SPI interface in the DAC chip are directly interconnected with an LVDS interface and a pipe orifice of the FPGA chip respectively;

further, an SPI interface in the DDS chip is directly interconnected with a pipe orifice of the FPGA chip.

Compared with the prior art, the invention has the following advantages:

first, the invention designs the signal processing board and the comprehensive bottom board, and installs two signal processing boards with the same function on the comprehensive bottom board, realizes the power supply and processing switching of the two signal processing boards by selecting, and realizes the information interaction with the external upper computer through the comprehensive bottom board after the switching work, thereby avoiding the condition that the radar system stops working after one signal processing board is damaged, and improving the reliability of the general signal processing system.

Secondly, the VPX interface which adopts a locking and fast plugging structure is arranged on the signal processing board, so that the fastening performance can be ensured, the fast tattoo replacement requirement can be realized, and the maintenance is convenient.

Thirdly, the invention can complete intermediate frequency echo collection, target identification and sum-difference processing by adopting a radar signal processing system based on FPGA and DSP, thereby having small volume, high integration level and strong universality and being suitable for a primary radar system and a secondary radar system.

Drawings

FIG. 1 is a schematic diagram of the overall structure of a general signal processing system according to the present invention;

FIG. 2 is a block diagram of a signal processing board according to the present invention;

FIG. 3 is a block diagram of an integrated backplane structure according to the present invention;

FIG. 4 is a block diagram of an FPGA module of the present invention;

FIG. 5 is a block diagram of the DSP module structure of the present invention;

FIG. 6 is a functional block diagram of an FPGA chip according to the present invention;

FIG. 7 is a functional block diagram of a DSP chip according to the present invention.

Detailed Description

The following detailed description of the embodiments of the invention refers to the accompanying drawings.

Referring to fig. 1, the marine general signal processing system in this example includes a first signal processing board 1, a second signal processing board 2 and an integrated bottom board 3, the two signal processing boards have the same hardware design principle and implementation function and are both installed on the integrated bottom board 3, and power supply and processing switching of the two signal processing boards can be implemented through switch selection on the integrated bottom board, that is, only one signal processing board normally works when the general signal processing system normally works, and the other signal processing board is in a state where a hot backup does not work or is only powered on, and external information interaction can be implemented through the integrated bottom board 3.

Referring to fig. 2, the size of the signal processing board is not greater than 200mm × 300mm, and the signal processing board includes an FPGA module, a DSP module, 3 ADC chips, 2 DAC chips, a DDS chip, a debug port, and a VPX interface, and the DSP module, the ADC chip, the DAC chip, and the DDS chip are all connected to the FPGA module; the DSP module and the FPGA module are respectively connected with a debugging port and a VPX interface; the DSP chip in the DSP module is connected with the FPGA chip of the FPGA module in a board mode through the SRIO, the EMIF and the GPIO; the DSP module is used for analyzing the calibration coefficient and the working parameters sent by the upper computer through the comprehensive bottom plate, sending the calibration coefficient and the working parameters to the FPGA module after processing, receiving the data processed by the FPGA module, completing moving target display, moving target detection, distance dimension CFAR, point trace condensation and target parameter calculation, and finally reporting the data to the terminal. The FPGA module is used for analyzing the calibration coefficient and the working parameter sent by the DSP module, then performing orthogonal digital down conversion, correction value loading, doppler compensation, pulse compression and data integration processing on echo sampling data of a radar emission detection signal, and then transmitting the processed data to the DSP module; the 3 ADC chips are respectively connected with the FPGA chip in the FPGA module and used for receiving a command of the FPGA module to complete echo sampling; the 2 DAC chips are respectively connected with the FPGA chip in the FPGA module and used for receiving signals of the FPGA module after selecting DDS, pulse pressure and MTD according to commands and directly converting the signals into analog signals to be output; the DDS chip is connected with the FPGA chip in the FPGA module and is used for receiving parameters of frequency control words, phase control codes and phase control addresses of the FPGA module and generating a required intermediate frequency waveform; the debugging port is respectively connected with a DSP chip in the DSP module and an FPGA chip in the FPGA module and is used for debugging and testing the DSP chip and the FPGA chip; the VPX interface is respectively connected with a DSP chip in the DSP module and an FPGA chip in the FPGA module, the VPX interface comprises 4 connectors including P0, P3, P4 and P6, and the P0 connector defines module power supply, slot position numbers and the like; the P3 connector defines Ethernet and single-ended LVTTL signals; the P4 connector defines a differential line and a single-ended LVTTL signal; the P6 connector defines a serial port RS422 and a single-ended LVTTL signal; p1, P2 and P5 are empty.

Referring to fig. 3, the integrated backplane 3 includes 2 slots VPX sockets, a power supply socket, a switch, a communication socket, a timing control socket, and an optical module; each VPX socket comprises 4 signal ports including J0, J3, J4 and J6, wherein the J0 signal port is connected with a power supply socket and a change-over switch, and a power supply is provided for the signal processing board through the power supply socket and the change-over switch; j3 and J6 are connected with a communication socket, J3 is an Ethernet signal port, J6 is a serial signal port, and the communication between the signal processing board and the upper computer is realized through the communication socket; the J4 signal port is connected with a time sequence control socket, and the time sequence control of the upper computer on the signal processing board is realized through the time sequence control socket; j6 is also connected with an optical module, and optical fiber communication between the signal processing board and an upper computer is realized through the optical module; j1, J2 and J5 are empty, and the P0, P3, P4 and P6 connectors in the VPX interface can correspond to the J0, J3, J4 and J6 signal ports inserted in the VPX socket.

Referring to fig. 4, the FPGA module includes an FPGA chip and a peripheral DDR3 memory thereof, a configuration start Flash, an SPIFlash, a serial port interface, LVDS and lvTTL discrete interfaces, and a clock source, where 4 DDR3 memories are used to expand an external storage space of the FPGA chip; the configuration starts Flash, and is used for solidifying the program code of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified; the SPIFlash is used for the communication between the FPGA chip and external SPI equipment; and the clock source is used for providing a clock for the FPGA chip.

Referring to fig. 5, the DSP module includes a DSP chip and a peripheral DDR3 memory thereof, a configuration startup Flash, an SPI Flash, an ethernet interface, a serial interface, and a clock source; the DDR3 memories are four and used for expanding the external storage space of the FPGA chip; the configuration starts SPIFlash which is used for solidifying the program codes of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified; the SPIFlash is used for the communication between the DSP chip and an external SPI device; and the clock source is used for providing a clock for the DSP chip.

Referring to fig. 6, the functional modules of the FPGA chip include a parameter generation sub-module, a working state monitoring sub-module, a timing control sub-module, a DDS control sub-module, an AGC sub-module, an amplitude and phase correction sub-module, an orthogonal digital down-conversion sub-module, a correction value loading sub-module, a doppler compensation sub-module, a pulse compression sub-module, and a data integration sub-module; the function of each submodule is as follows:

the parameter generation submodule is used for analyzing binding parameters, calibration coefficients and working parameters issued by the DSP module through EMIF, and generating control parameters required by the time sequence control submodule, the DDS control submodule, the AGC submodule, the amplitude-phase correction submodule, the orthogonal digital down-conversion submodule, the correction value loading submodule, the Doppler compensation submodule and the pulse compression submodule according to the parameters;

the working state monitoring submodule is used for monitoring the working state and communication state information of the key node and uploading the working state and communication state information to the DSP module through the EMIF;

the time sequence control submodule is used for generating the time sequence required by the system according to the control parameters issued by the parameter generation submodule;

the DDS control submodule is used for generating frequency and phase control codes required by the DDS chip according to the control parameters issued by the parameter generation submodule;

the AGC submodule is used for calculating the current average power through digital detection according to the control parameters issued by the parameter generation submodule and the data issued by the orthogonal digital down-conversion submodule, and comparing the current average power with the required RGC upper and lower limit values to generate the required AGC control code;

the amplitude-phase correction submodule is used for calculating the signal frequency domain intensity of a sum-difference channel by FFT (fast Fourier transform) on the data sampled by the ADC (analog-to-digital converter) chip according to the control parameters issued by the parameter generation submodule, calculating a sum-difference channel correction coefficient and uploading the sum-difference channel correction coefficient to the DSP module;

the orthogonal digital down-conversion submodule is used for down-converting the data sampled by the ADC chip to a baseband according to the control parameter issued by the parameter generation submodule, filtering a high-frequency signal by using a filter and then extracting the high-frequency signal to generate an in-phase signal and an orthogonal signal with low data rate;

the correction value loading submodule is used for carrying out amplitude-phase correction on the sum-difference channel through a correction formula according to the control parameters sent by the parameter generating submodule and the parameters and data sent by the orthogonal digital down-conversion module;

the Doppler compensation submodule is used for generating corresponding nco according to the control parameter issued by the parameter generation submodule, and obtaining a desired signal after the parameter and the data issued by the correction value loading module are subjected to complex field frequency mixing;

the pulse compression submodule is used for converting the time domain signals into frequency domains through FFT (fast Fourier transform) according to the control parameters issued by the parameter generation submodule and the parameters and data issued by the Doppler compensation submodule, selecting pulse compression coefficient domain frequency domain signals corresponding to the ROM according to the waveform, multiplying the pulse compression coefficient domain frequency domain signals, and performing inverse Fourier transform (IFFT) to complete matched filtering of the signals;

and the data integration submodule is used for integrating and packaging the three paths of sum and difference signals transmitted by the pulse compression module and transmitting the integrated and packaged sum and difference signals to the DSP module through the SRIO.

Referring to fig. 7, the functional modules of the DSP chip include a data parsing sub-module, a data reporting sub-module, a parameter parsing and calculating sub-module, a parameter issuing sub-module, a moving target displaying sub-module, a moving target processing sub-module, a distance dimension CFAR sub-module, a trace aggregation sub-module, and a parameter calculating sub-module; the function of each submodule is as follows:

the data analysis submodule is used for analyzing the correction value and the working state information reported by the FPGA module through the EMIF and sending the correction value and the working state information to the data reporting submodule;

the data reporting submodule is used for reporting the data sent by the parameter resolving submodule and the information sent by the data analyzing submodule to the terminal through the Ethernet;

the parameter analyzing and calculating submodule is used for analyzing the calibration coefficient and the working parameter sent by the upper computer and calculating the binding distance and the offset speed information as the control parameters of the FPGA;

the parameter issuing sub-module is used for issuing the control parameters issued by the parameter analyzing and calculating sub-module to the FPGA module through EMIF;

the moving target display submodule is used for three-time delay cancellation to form zero-frequency suppression;

the moving target processing submodule is used for rearranging data according to slow time, performing Fourier transform FFT accumulation of N points to form suppression of designated frequency, and performing meteorological clutter suppression by using a filter bank in a remote area;

the distance dimension CFAR submodule is used for filtering noise and clutter;

the trace point condensation submodule is used for distinguishing and merging trace points, namely filtering false trace points, distinguishing trace point data of different targets, and merging the trace point data belonging to the same target;

and the parameter calculation submodule is used for estimating the frequency shift and the time delay of the target, calculating the speed and the distance of the target and calculating the target angle through the sum-difference amplitude.

The working process of the invention is as follows:

the method comprises the following steps: the DSP module receives calibration coefficients and working parameter information sent by an upper computer

Firstly, a power supply change-over switch of the comprehensive bottom plate is used for electrifying a target signal processing plate, an upper computer sends a calibration coefficient and working parameters to a DSP module, the DSP module analyzes the calibration coefficient and the working parameters sent by the upper computer, the binding distance, the offset speed and other information are calculated into FPGA control parameters such as waveforms, frequency control words and the like, and the DSP module sends the calculated and converted parameters to the FPGA module through EMIF.

Step two: judging the working mode according to the working parameters, and entering the corresponding working process

The FPGA module analyzes binding parameters, calibration coefficients and working parameters issued by the DSP module through EMIF, generates required frequency control words, filter coefficients, time sequence control parameters, doppler frequency deviation, DDS time delay and DDS frequency deviation according to the parameters and issues the frequency control words, the filter coefficients, the time sequence control parameters, the Doppler frequency deviation, the DDS time delay and the DDS frequency deviation to each function module of the FPGA module. The FPGA module judges according to the working parameters and sequentially enters different working modes:

and (3) a normal working mode: the DDS control module generates a required intermediate frequency waveform according to the parameters issued by the FPGA module and transmits a detection signal; the ADC chip finishes echo sampling; the FPGA module carries out quadrature digital down-conversion processing to the data after the echo sampling, and the DAC chip receives the direct analog signal output that turns into of the signal after FPGA module's command selection DDS, pulse pressure, MTD, carries out corrected value loading module and AGC module after quadrature digital down-conversion processing, wherein corrected value loading module: storing a current frequency point correction coefficient issued by the DSP, and performing amplitude-phase correction on the sum-difference channel according to a correction formula; an AGC module: the current average power is calculated by digital detection and compared with the required RGC upper and lower limit values to generate the required AGC control code. After passing through the correction value loading module, sequentially performing a Doppler compensation module, a pulse compression module and a data integration module; and the data integration module integrates and packs the data and sends the data to the DSP module through the SRIO. The DSP module performs moving target display, moving target detection, constant false alarm detection, trace point agglomeration and target parameter calculation on the data after data integration step by step;

amplitude and phase correction working mode: and closing the emission detection signal, calculating the signal frequency domain intensity of the sum-difference channel by the amplitude-phase correction module through FFT (fast Fourier transform), calculating the correction coefficient of the sum-difference channel, uploading the correction coefficient to the DSP module, and reporting the correction value to the upper computer by the DSP module through the Ethernet.

Simulating a self-checking working mode: in the process of powering on and starting the board card, the processor initializes each interface, runs a function self-checking program, collects a self-checking test result and reports the self-checking test result through a serial port or an Ethernet. And generating a time sequence required by the system according to the working mode and the time sequence control parameter, generating a detection signal by the information processing board after delaying, and resolving according to a normal working mode.

Standby working mode: the FPGA mode generates a standby time sequence according to the working mode and the time sequence control parameter.

Step three: and reporting the measured target data, the corrected value and the working state information to an upper computer through the Ethernet.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. The utility model provides a general signal processing system of marine radar, includes signal processing board and synthesizes bottom plate, its characterized in that:

the number of the signal processing boards is two, each signal processing board is provided with a VPX interface, each signal processing board comprises an FPGA module, a DSP module, an ADC chip, a DAC chip, a DDS chip, a debugging port and a VPX interface, and the DSP module, the ADC chip, the DAC chip and the DDS chip are all connected with the FPGA module; the DSP module and the FPGA module are respectively connected with a debugging port and a VPX interface;

2. The system of claim 1, wherein the FPGA module in the signal processing board includes a DDR3 memory on the FPGA chip and its periphery, a configuration start Flash, an SPIFlash, a serial port interface, LVDS and LVTTL discrete interfaces, and a clock source, the number of the DDR3 memory is four, and the DDR3 memory is used for expanding the external storage space of the FPGA chip; the configuration starts Flash for solidifying the program code of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified, and the SPIFlash is used for the communication between the FPGA chip and an external SPI device.

3. The system of claim 1, wherein the DSP module in the signal processing board comprises a DSP chip and its peripheral DDR3 memory, a configuration start Flash, an SPIFlash, an Ethernet interface, a serial interface, and a clock source; the DDR3 memories are 4 and used for expanding the external storage space of the FPGA chip; the configuration starts SPIFlash which is used for solidifying the program codes of the FPGA chip and ensuring the normal work of the FPGA chip after being electrified; the SPIFlash is used for the communication between the DSP chip and an external SPI device.

4. The system of claim 1, wherein:

the number of the ADC chips is 3, and the ADC chips are used for receiving commands of the FPGA module to complete echo sampling;

the number of the DAC chips is 2, and the DAC chips are used for receiving signals of the FPGA module after selecting DDS, pulse pressure and MTD and directly converting the signals into analog signals to be output;

the DDS chip is used for receiving parameters such as frequency control words, phase control codes and phase control addresses of the FPGA module and generating a required intermediate frequency waveform;

the debugging port is used for debugging and testing the DSP module and the FPGA module;

and the VPX interface is used for connecting the comprehensive bottom plate, supplying power for the DSP module and the FPGA module and communicating with the outside.

5. The system of claim 1, wherein: the DSP module, the ADC chip, the DAC chip and the DDS chip are respectively connected with the FPGA module in the following relation:

the SRIO interface, the EMIF interface and the GPIO interface of the DSP chip in the DSP module are respectively interconnected with the corresponding interfaces of the FPGA chip in the FPGA module;

an LVDS interface and an SPI interface in the DAC chip are directly interconnected with an LVDS interface and a pipe orifice of an FPGA chip in the FPGA module respectively;

and an SPI interface in the DDS chip is directly interconnected with a pipe orifice of the FPGA chip in the FPGA module.

6. The system of claim 2, wherein: the FPGA chip comprises:

the parameter generation submodule is used for analyzing binding parameters, calibration coefficients and working parameters sent by the DSP module through EMIF and generating control parameters required by a time sequence control submodule, a DDS control submodule, an AGC submodule, an amplitude-phase correction submodule, an orthogonal digital down-conversion submodule, a correction value loading submodule, a Doppler compensation submodule and a pulse compression submodule according to the parameters;

the Doppler compensation submodule is used for generating corresponding nco according to the control parameters issued by the parameter generation submodule, and acquiring a desired signal after the parameters and the data issued by the correction value loading module are subjected to complex field frequency mixing;

the pulse compression submodule is used for converting the time domain signals into frequency domains through FFT according to the control parameters issued by the parameter generation submodule and the parameters and data issued by the Doppler compensation submodule, selecting pulse compression coefficient domain frequency domain signals corresponding to the ROM according to waveforms for multiplication, and performing inverse Fourier transform (IFFT) to complete matched filtering of the signals;

7. The system of claim 3, wherein: the DSP chip includes:

the moving target processing submodule is used for rearranging data according to slow time, performing Fourier transform FFT accumulation of N points to form suppression of designated frequency, and performing meteorological clutter suppression in a remote area by using a filter bank;

the distance dimension CFAR submodule is used for filtering noise and clutter;

the trace point condensation submodule is used for carrying out trace point distinguishing and merging processing, namely filtering false trace points, distinguishing trace point data of different targets and merging the trace point data belonging to the same target;

8. The system of claim 1, wherein: the VPX interface on the signal processing board adopts a lockable and quick plug structure, thereby being convenient for maintenance and reducing the maintenance intensity.