CN115915756A - Preparation method of semiconductor structure, semiconductor structure and semiconductor memory - Google Patents
Preparation method of semiconductor structure, semiconductor structure and semiconductor memory Download PDFInfo
- Publication number
- CN115915756A CN115915756A CN202211477231.2A CN202211477231A CN115915756A CN 115915756 A CN115915756 A CN 115915756A CN 202211477231 A CN202211477231 A CN 202211477231A CN 115915756 A CN115915756 A CN 115915756A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- layer
- forming
- isolation
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the disclosure provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor memory, wherein the method comprises the following steps: providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure; forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure; and carrying out heat treatment on the capacitor supporting structure and the conducting layer, and forming a capacitor isolation structure on the surface of the capacitor supporting structure, wherein the capacitor isolation structure is used for insulating and isolating at least one capacitor column. Like this, through heat treatment at the surface formation electric capacity isolation structure of electric capacity bearing structure, block the conducting layer and to the connection of electric capacity post, realize the insulation isolation to electric capacity post, this scheme not only process is simple, and the cost is lower moreover.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure, and a semiconductor memory.
Background
With the development of semiconductor technology, in order to further improve the integration level of a semiconductor Memory and increase the Memory performance, a Three Dimensional (3D) semiconductor Memory is proposed, wherein the 3D structure expands the structure of the semiconductor Memory upwards, which is a great help for the development of Dynamic Random Access Memory (DRAM) and other memories. In the DRAM, a capacitor is a part for storing data in a semiconductor memory, and in the process of manufacturing a 3D DRAM, when a capacitor bottom electrode is formed, the capacitor bottom electrode connects all capacitors on a bit line together due to process influence, and at this time, it is necessary to separate the connected capacitors.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor memory.
In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure;
forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure;
and carrying out heat treatment on the capacitance supporting structure and the conductive layer, and forming a capacitance isolation structure on the surface of the capacitance supporting structure, wherein the capacitance isolation structure is used for insulating and isolating the at least one capacitance column.
In some embodiments, the thermally treating the capacitive support structure and the conductive layer comprises:
forming an isolation protection structure between the conductive layers;
taking the isolation protection structure as protection, and annealing the capacitor supporting structure and the conductive layer to obtain the capacitor isolation structure;
and removing the isolation protection structure.
In some embodiments, the annealing temperature of the annealing treatment is 600 to 1000 ℃.
In some embodiments, the material of the capacitive support structure includes a first dielectric, the material of the conductive layer includes a metal material, and the material of the capacitive isolation structure includes a second dielectric, wherein the second dielectric is decomposed from the first dielectric, and the second dielectric is an insulating substance.
In some embodiments, the material of the capacitive support structure comprises a silicon carbon nitrogen oxide compound, the material of the conductive layer comprises molybdenum, and the material of the capacitive isolation structure comprises a silicon carbon nitrogen compound.
In some embodiments, in the silicon oxycarbonitride, the atomic ratio of silicon, carbon, oxygen, and nitrogen is: 1 (1.5-1.8) 0.05; in the silicon carbon nitrogen compound, the atomic ratio of silicon to carbon to nitrogen is as follows: 1 (1.5-1.8) and 0.4.
In some embodiments, the providing a substrate comprises:
providing an initial substrate; the initial substrate comprises a transistor area and a capacitor area, and the transistor area and the capacitor area are sequentially arranged along a first direction;
forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region;
and carrying out metal silicification treatment on the at least one initial capacitor column to obtain the at least one capacitor column.
In some embodiments, the providing an initial substrate comprises:
providing a substrate layer;
forming a stack structure over the substrate layer;
forming an oxide layer over the stacked structure;
and forming a dielectric layer above the oxide layer.
In some embodiments, the stacked structure comprises at least one stacked layer comprising a sacrificial layer and an active layer;
the forming a stack structure over the substrate layer, comprising:
forming the sacrificial layer over the substrate layer, forming the active layer over the sacrificial layer;
repeating the steps of forming the sacrificial layer and the active layer until the stacked structure is formed.
In some embodiments, the forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region includes:
performing a first patterning process on the initial substrate, forming at least one isolation trench extending along the first direction in the initial substrate, and dividing the active layer in the transistor area into at least one active pillar and dividing the active layer in the capacitor area into at least one initial capacitor pillar by the at least one isolation trench;
forming an oxide structure in the at least one isolation trench;
performing second patterning on the initial substrate and the oxidation structure, forming at least one electrode groove in the transistor area, and forming at least one supporting groove in the capacitor area;
carrying out doping treatment on the active column to form a source electrode and a drain electrode of the transistor structure;
and forming an electrode isolation structure in the electrode groove and forming the capacitance support structure in the support groove.
In some embodiments, the forming an electrode isolation structure in the electrode trench and a capacitive support structure in the support trench includes:
forming a trench filling structure in the electrode trench and the support trench; the groove filling structure positioned in the electrode groove forms the electrode isolation structure, and the groove filling structure positioned in the support groove forms the capacitance support structure.
In some embodiments, after forming the capacitive support structure in the support trench, the method further comprises:
removing the oxidation structure and the dielectric layer above the top surface plane of the oxidation layer;
removing the sacrificial layer and the oxide layer within the capacitive region to expose the initial capacitive pillars not covered by the capacitive support structures.
In some embodiments, when the doping process is performed on the active pillars, the doping process includes: and (4) gas-phase doping.
In a second aspect, embodiments of the present disclosure provide a semiconductor structure, including:
the capacitor comprises a substrate, at least one capacitor post and at least one capacitor supporting structure, wherein the substrate is provided with the at least one capacitor post, and the capacitor post penetrates through the at least one capacitor supporting structure;
the capacitor comprises a conductive layer formed on the surface of the capacitor column and a capacitor isolation structure formed on the surface of the capacitor support structure, wherein the capacitor isolation structure is used for insulating and isolating the at least one capacitor column.
In a third aspect, the present disclosure provides a semiconductor memory device including the semiconductor structure as set forth in the second aspect.
The embodiment of the disclosure provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor memory, wherein the method comprises the following steps: providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure; forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure; and carrying out heat treatment on the capacitor supporting structure and the conductive layer, and forming a capacitor isolation structure on the surface of the capacitor supporting structure, wherein the capacitor isolation structure is used for insulating and isolating at least one capacitor column. Like this, through heat treatment at the surface formation electric capacity isolation structure of electric capacity bearing structure, block the conducting layer and to the connection of electric capacity post, realize the insulation isolation to the electric capacity post to can reduce the electric capacity electric leakage, be favorable to proposing the performance of semiconductor construction, this scheme not only the process is realized easily, and the cost is lower moreover.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 2 is a schematic partial structural view of a substrate according to an embodiment of the present disclosure;
fig. 3A to 16 are schematic views of structures obtained in a process of fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 17 is a schematic structural diagram of a semiconductor memory according to an embodiment of the disclosure.
The correspondence of reference numerals is as follows:
201: a capacitor column;
202: a capacitive support structure;
101: a substrate layer;
102: a stacked structure;
1021: a sacrificial layer;
1022: an active layer;
103: an oxide layer;
104: a dielectric layer;
105: a first photoresist layer;
106: isolating the trench;
107: an oxidized structure;
108: a second photoresist layer;
109: an electrode trench;
110: a support trench;
111: a trench filling structure;
203: a conductive layer;
204: an isolation protection structure;
205: a capacitive isolation structure;
170: a semiconductor memory device.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and are not limiting of the disclosure. It should be noted that, for the convenience of description, only the parts relevant to the related disclosure are shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to be limiting of the disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
It is noted that the terms "first \ second \ third" and "first \ second \ third" in the embodiments of the present disclosure are used for distinguishing similar objects only and do not denote a particular order or sequence of objects, and it is to be understood that "first \ second \ third" and "first \ second \ third" may be interchanged under certain circumstances or sequences of events to enable embodiments of the present disclosure described herein to be practiced in other than the order shown or described herein.
In depositing the Bottom Electrode (BE) of the capacitor of the 3D DRAM, it connects all the capacitors in the entire Bit Line (BL) together due to the Atomic Layer Deposition (ALD) process, and it is required to separate the connected capacitors.
The current solution is to add a sacrificial layer in the side recesses of the BE material, which is different from the frame material. However, this solution is complicated in process and requires an additional mask, resulting in increased cost and is not suitable for process fabrication.
Based on this, the embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, and the basic idea of the method is: providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure; forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure; and carrying out heat treatment on the capacitor supporting structure and the conducting layer, and forming a capacitor isolation structure on the surface of the capacitor supporting structure, wherein the capacitor isolation structure is used for insulating and isolating at least one capacitor column. Like this, the electric capacity bearing structure who will connect the electric capacity post through the mode of thermal treatment handles for electric capacity isolating construction, blocks the connection of conducting layer to the electric capacity post, realizes the insulation isolation to the electric capacity post, can reduce electric capacity electric leakage, compares in the mode of additionally increasing the sacrificial layer moreover, and this scheme not only the simple easy realization of process, and is with low costs moreover, is applicable to the batch manufacturing in the actual production.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In an embodiment of the present disclosure, referring to fig. 1, a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown. As shown in fig. 1, the method may include:
s1001: providing a substrate, wherein at least one capacitor post is formed in the substrate, and the at least one capacitor post penetrates through the at least one capacitor support structure.
It should be noted that the method provided by the embodiments of the present disclosure is used for preparing a semiconductor structure, and mainly relates to a capacitor portion in a 3D DRAM. Firstly, a substrate is provided, and the substrate comprises at least one capacitor column and at least one capacitor support structure, wherein the capacitor support structure is penetrated by the capacitor column. The at least one capacitor column can be arranged in the substrate in a spatial array mode, so that a 3D semiconductor structure can be formed, the integration level of the semiconductor structure is increased, and the storage performance is improved.
Exemplarily, fig. 2 illustrates a schematic partial structure diagram of a substrate provided by an embodiment of the present disclosure, and in fig. 2, taking two capacitance support structures 202 and a plurality of capacitance pillars 201 as an example, the capacitance support structures 202 support two ends of each capacitance pillar 201.
The formation process of the substrate will be described first with reference to the drawings.
In some embodiments, providing a substrate may include:
providing an initial substrate; the initial substrate comprises a transistor area and a capacitor area, and the transistor area and the capacitor area are arranged at intervals along a first direction;
forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region;
and carrying out metal silicification on at least one initial capacitor column to obtain at least one capacitor column.
The preparation method of the substrate may be: firstly, providing an initial substrate, dividing the initial substrate into a transistor area and a capacitor area, then processing the initial substrate, forming at least one transistor structure in the transistor area, forming at least one initial capacitor column in the capacitor area, and then carrying out metal silicification on the initial capacitor column to obtain the required capacitor column.
Wherein providing an initial substrate may comprise:
providing a substrate layer 101;
forming a stack structure 102 over a substrate layer;
forming an oxide layer 103 over the stacked structure;
a dielectric layer 104 is formed over the oxide layer.
Fig. 3A is a schematic top view of the substrate layer 101, and fig. 3B corresponds to different cross sections in fig. 3A. In the following fig. 4A to 10B, in the two figures with the same number, a represents a schematic top view of the obtained structure, and B represents different cross sections corresponding to a, which will not be described again.
It should be further noted that the substrate layer 101 may be a silicon substrate or other suitable substrate materials such as silicon, germanium, silicon germanium compound, etc., such as a doped or undoped monocrystalline silicon substrate, a polycrystalline silicon substrate, etc., which is taken as an example.
As shown in fig. 3A, the substrate layer 101 may be divided into a bit line region, a transistor region, and a capacitor region sequentially arranged in a first direction. The width of the bit line region along the second direction may be greater than the transistor region and the capacitor region for forming a step-shaped bit line.
Fig. 4A and 4B are schematic views of the resulting structure after formation of dielectric layer 104. As shown in fig. 4B, a stacked structure 102 is formed over the substrate layer 101, an oxide layer 103 is formed over the stacked structure 102, and a dielectric layer 104 is formed over the oxide layer 103.
The stacked structure 102 includes at least one stacked layer, and as shown in fig. 4B, a sacrificial layer 1021 and an active layer 1022 form the stacked layer. Accordingly, forming the stack structure 102 over the substrate layer 101 may include:
forming a sacrificial layer 1021 above the substrate layer 101, and forming an active layer 1022 above the sacrificial layer 1021;
the steps of forming the sacrificial layer 1021 and the active layer 1022 are repeated until the stacked structure 102 is formed.
Here, the number of stacked layers is not particularly limited, and only two stacked layers are illustrated in the drawings.
It should be noted that, before the first sacrificial layer 1021 is formed, the substrate layer 101 may be pre-cleaned to remove oxides or other impurities that may be formed on the surface of the substrate layer 101. Then, a sacrificial layer 1021 is formed, and an active layer 1022 is formed, and the process is repeated. For example, the above-mentioned steps are repeated twice, so as to obtain a stacked structure 102 comprising two stacked layers as shown in fig. 4B; the thickness of the sacrificial layer 1021 may be 60 nanometers (nm), and the thickness of the active layer 1022 may be 30nm. Then, bevel etching can be performed from top to bottom to remove the excessive sacrificial layer at the edge and the back, and the cleaning process is performed.
An oxide layer 103 is then formed over the stacked structure 102, and a dielectric layer 104 is formed over the oxide layer 103.
Wherein, the material of the sacrificial layer 1021 may include silicon germanium (SiGe) compound, etc.; the material of the active layer 1022 may be the same as the substrate layer 101, such as silicon; the material of the oxide layer 103 may include silicon oxide (SiO), tetraethoxysilane (Teos), and the like; the material of the dielectric layer 104 may include silicon nitride (SiN), etc., and each layer may be formed by deposition.
At this time, an initial substrate is obtained, i.e., fig. 4A and 4B show a schematic view of the structure of the initial substrate. It is also desirable to further form the transistor structures and capacitor pillars in the initial substrate. In some embodiments, forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region comprises:
performing a first patterning process on an initial substrate, forming at least one isolation trench 106 extending along a first direction in the initial substrate, and the at least one isolation trench 106 dividing the active layer 1022 in the transistor region into at least one active pillar and the active layer 1022 in the capacitor region into at least one initial capacitor pillar;
forming an oxide structure 107 in the at least one isolation trench 106;
performing a second patterning process on the initial substrate and the oxide structure 107 to form at least one electrode trench 109 in the transistor region and at least one support trench 110 in the capacitor region;
carrying out doping treatment on the active column to form a source electrode and a drain electrode of the transistor structure;
electrode isolation structures are formed in the electrode trenches 109 and capacitive support structures are formed in the support trenches 110.
The first patterning process may be performed on the initial substrate by: a first photoresist layer 105 is first formed over the initial substrate. Fig. 5A and 5B are schematic views of the resulting structure after the first photoresist layer 105 is formed. As shown in fig. 5A, the first photoresist layer 105 may be divided into two portions, wherein the first portion is located in the bit line region, extends along the second direction and covers the bit line region; the second portion is located in the transistor region and the capacitor region, extends in the first direction, and includes a plurality of portions arranged at intervals in the second direction. If only the second portions in the transistor region and the capacitor region are concerned, it can be seen that the first photoresist layer 105 has a pattern extending in the first direction, which exposes regions that need to be subsequently removed to form the isolation trenches 106.
Wherein, as shown in fig. 5A, in the second direction, a width (1) of a region exposed by the first photoresist layer 105 may be 140nm, that is, a width of the isolation trench 106 may be 140nm, and a width (2) of the first photoresist layer 105 patterning the isolation trench 106 may be 60nm; in the first direction, the width (3) of the first photoresist layer 105 over the transistor region and the capacitor region may be 660nm, and the width (4) of the first photoresist layer 105 over the bit line region may be 80nm. In addition, the drawings illustrating the embodiments of the present disclosure are for convenience of describing the implementation process of the present disclosure, and are not necessarily drawn strictly to scale, and the numerical values illustrated herein are also only exemplary and are not particularly limited.
Then, the first photoresist layer 105 is used as a mask to remove the part of the initial substrate not covered by the first photoresist layer 105, so as to obtain at least one isolation trench 106. Fig. 6A and 6B are schematic views of the resulting structure after forming the isolation trench 106. As shown in fig. 6B, the isolation trench 106 may be formed by etching, and as shown in fig. 6B, the etching depth of the isolation trench 106 is deeper than that of the lowermost sacrificial layer 1021, and the substrate layer 101 is also etched and removed by a certain depth along the etching direction.
As shown in fig. 6A and 6B, the isolation trench 106 separates the stacked structure 102 in the transistor region and the capacitor region, and the separated active layer 1022 in the transistor region is referred to as an active pillar, and the separated active layer 1022 in the capacitor region is referred to as an initial capacitor pillar.
After the isolation trench 106 is formed, the first photoresist layer 105 is removed. The first photoresist layer 105 may be removed by etching and/or using nitrogen (N) 2 ) Hydrogen (H) 2 ) Etc., and cleaning, etc., with a cleaning agent to completely remove the photoresist.
Next, an oxide structure 107 is formed in the isolation trench 106, and fig. 7A and 7B are schematic views of the structure obtained after the oxide structure 107 is formed. As shown in fig. 7A and 7B, the oxide structure 107 is completely formed within the isolation trench 106. The oxide structure 107 and the oxide layer 103 may be made of the same material, such as silicon oxide or tetraethoxysilane, and the manner of forming the oxide structure 107 may be deposition. It is understood that since the oxide structure 107 and the oxide layer 103 are made of the same material, there is no distinct distinction between the two, and the boundaries between the two are distinguished in the drawings only for the convenience of separate description.
After the oxide structure 107 is formed, a Chemical Mechanical Polishing (CMP) process may be performed, and the stop layer of the CMP is the dielectric layer 104, and a detergent is used to clean the dielectric layer 104 to remove residual impurities, so that the top surfaces of the oxide structure 107 and the dielectric layer 104 are flush.
A second patterning process is performed on the structure shown in fig. 7A and 7B to form the electrode trench 109 and the support trench 110. The second patterning process may be performed by: a second photoresist layer 108 is first formed over the dielectric layer 104 and the oxide structure 107, and fig. 8A and 8B are schematic views of the resulting structure after the second photoresist layer 108 is formed.
As shown in fig. 8A and 8B, the second photoresist layer 108 may be divided into three portions, a first portion located above the bit line region, extending in the second direction and completely covering the bit line region. A second part of the bit line transistor region, including a plurality of sub-patterns arranged at intervals along the second direction, wherein the width of the sub-pattern along the second direction is larger than that of the dielectric layer 104 below the sub-pattern, that is, along the second direction, the sub-pattern not only covers the dielectric layer 104, but also covers part of the oxide structure 107, so that when patterning is performed, the part of the oxide structure 107 below the sub-pattern is remained; meanwhile, the dielectric layer 104 and the oxide structure 107 at both sides of the sub-pattern are not covered along the first direction, so that the active region under the uncovered region is exposed for forming the source and the drain of the transistor structure during patterning. The third portion is located above the capacitor region, the third portion extends along the second direction, and exposes the region for forming the support trench 110, the support trench position shown in fig. 8A is located on two sides of the capacitor region along the first direction, and in addition, the support trenches may be in other numbers and located at other positions, wherein, a plurality of support trenches may be arranged at intervals along the first direction.
Then, pattern transfer is performed using the second photoresist layer 108 as a mask, resulting in the structure shown in fig. 9A and 9B. As shown in fig. 9A and 9B, in the bit line region, the second photoresist layer 108 completely covers the dielectric layer 104 in the bit line region, and the structure of the bit line region is unchanged; in the transistor area, the dielectric layer 104, the oxide layer 103, the oxide structure 107, and the sacrificial layer 1021, which are not located under the second portion of the second photoresist layer 108, are removed, and the substrate layer 101 is also removed to a certain depth, but the active layer 1022 (i.e., active pillar) is remained, so that the electrode trench 109 is formed in the transistor area; in the capacitor region, the dielectric layer 104, the oxide layer 103 and the sacrificial layer 1021, which are not located under the third portion of the second photoresist layer 108, are removed, and the substrate layer 101 is also removed to a certain depth, but the active layer 1022 (i.e., the initial capacitor pillar) remains, and the support trench 110 is obtained in the capacitor region. The manner of forming the electrode trench 109 and the support trench 110 by performing the pattern transfer may be etching.
The second photoresist layer 108 is then removed, wherein the second photoresist layer 108 is formed and removed in substantially the same manner as the first photoresist layer 105.
Further, as shown in fig. 9A and 9B, the active layer 1022 (active pillar) in the transistor region is doped to form Source/Drain (S/D) of the transistor structure, respectively, and the unexposed active region forms a channel of the transistor structure. When doping treatment is performed on the active pillar, the doping treatment may include: gas phase doping is carried out, so that the doped impurities are uniformly distributed, and the process is simple.
The doping type of the doping process may be N-type or P-type, and is not limited herein. Based on this structure, a Gate-All-Around (GAA) structure can be obtained when a Gate of the transistor structure is formed later, and details thereof are not repeated.
Finally, an electrode isolation structure is formed in the electrode trench 109 and a capacitive support structure is formed in the support trench 110.
In some embodiments, forming the electrode isolation structure in the electrode trench 109 and forming the capacitor support structure in the support trench 110 includes:
forming a trench filling structure 111 in the electrode trench and the support trench; the trench filling structure 111 located in the electrode trench 109 forms an electrode isolation structure, and the trench filling structure 111 located in the support trench 110 forms a capacitance support structure.
It should be noted that the electrode isolation structure and the capacitive support structure may be formed simultaneously from the same material. At this time, the trench filling structure 111 may be simultaneously formed in the trench (including the electrode trench 109 located in the transistor region and the support trench 110 located in the capacitor region) obtained after the second patterning process, resulting in the structure shown in fig. 10A and 10B, and the trench filling structure 111 completely fills the trench as shown in fig. 10A and 10B. The trench filling structure 111 formed in the transistor region electrode trench 109 is referred to as an electrode isolation structure, and the trench filling structure 111 formed in the capacitor region support trench 110 is referred to as a capacitor support structure.
The trench filling structure 111 may be formed by deposition.
In some embodiments, after forming the capacitive support structure in the support trench 110, the method further comprises:
removing the oxidation structure 107 and the dielectric layer 104 above the top plane of the oxidation layer 103;
the sacrificial layer 1021 and the oxide layer 103 in the capacitor region are removed to expose the initial capacitor pillars not covered by the capacitor support structure.
It should be noted that, as shown in fig. 10A and 10B, after the trench filling structure 111 is formed, a CMP process may be performed to remove both the oxide structure 107 and the dielectric layer 104 above the top plane of the oxide layer 103 by using the oxide layer 103 as a CMP stop layer.
Further, the sacrificial layer 1021 and the oxide layer 103 in the capacitor region are both removed, so that the active layer 1022 (initial capacitor pillar) of the capacitor region, which is not covered by the capacitor support structure, is exposed, and the sacrificial layer 1021 and the oxide layer 103 may be removed by etching.
It should be noted that the subsequent processes are only directed to the capacitor region, and therefore, the subsequent steps only show the cross section in the ff' direction. Fig. 11 is a schematic diagram of the resulting structure after exposing the initial capacitor pillar.
Before forming the conductive layer, a metal silicide process (silicide) is first performed on the initial capacitor pillar (i.e., the active layer 1022 in fig. 11), so as to obtain the capacitor pillar 201. Fig. 12 is a schematic view of a structure obtained after forming the capacitor column 201. As shown in fig. 12, when the initial capacitor pillar is subjected to the metal silicide process, the initial capacitor pillar not covered by the capacitor support structure 202 is subjected to the metal silicide process, so that the exposed initial capacitor pillar is subjected to the metal silicide process, thereby obtaining the capacitor pillar 201.
The silicidation may be performed by reacting a metal material with the initial capacitor pillar, and the silicidation may be performed by using a metal material such as titanium, cobalt, or nickel. Therefore, the initial capacitor column is subjected to metal silicification by using a metal material, so that the conductivity of the capacitor is increased, and the storage performance is improved.
Thus, the substrate required by the embodiment of the disclosure is obtained.
S102: and forming a conductive layer on the surfaces of the capacitor posts and the capacitor support structure.
Fig. 13 is a schematic view of a structure obtained after the conductive layer 203 is formed. As shown in fig. 13, the conductive layer 203 covers the surface of the capacitor post 201 and the surface of the capacitor support structure 202. The material of the conductive layer 203 may include a metal material such as molybdenum or tungsten, or a conductive material such as titanium nitride, and in the embodiment of the present disclosure, the material of the conductive layer 203 is selected to be a metal material. The conductive layer 203 may be formed by deposition.
S103: and carrying out heat treatment on the capacitor supporting structure and the conductive layer, and forming a capacitor isolation structure on the surface of the capacitor supporting structure, wherein the capacitor isolation structure is used for insulating and isolating at least one capacitor column.
It should be noted that, the conductive layer 203 serves as a bottom electrode of the capacitor, as shown in fig. 13, the conductive layer 203 connects the capacitor pillars 201 together, and in the embodiment of the disclosure, the conductive layer 203 and the capacitor supporting structure 202 may be subjected to a heat treatment at a certain temperature, so as to form an insulated capacitor isolation structure 205 on the surface of the capacitor supporting structure 202, and meanwhile, the conductive layer 203 on the surface of the capacitor supporting structure 202 may be removed during the heat treatment, so as to insulate and isolate the capacitor pillars 201.
Thus, through heat treatment, the structure for connecting the capacitor columns 201 is changed from the conductive layer 203 with conductivity to the insulating capacitor isolation structure 205, so that the capacitor columns 201 can be isolated from each other, electric leakage is avoided, and the improvement of storage performance and reliability is facilitated.
In addition, when the scheme of the embodiment is used for isolating the capacitor column, a complex process is not needed, the embodiment is easy, the cost is reduced, and the method is suitable for a large-scale production process in actual manufacturing.
In some embodiments, thermally treating capacitive support structure 202 and conductive layer 203 may include:
forming an isolation protection structure 204 between the conductive layers 203;
taking the isolation protection structure 204 as protection, and annealing the capacitor support structure 202 and the conductive layer 203 to obtain a capacitor isolation structure 205;
the isolation protection structure 204 is removed.
Fig. 14 is a schematic structural view of the isolation protection structure 204. The isolation protection structure 204 can prevent oxidation effect caused by oxygen in the environment during high temperature reaction during subsequent heat treatment, thereby playing a role in packaging protection. The isolation protection structure 204 may be made of the same material as the oxide layer 103, such as silicon oxide, and the isolation protection structure 204 may be formed by deposition.
It should be further noted that the heat treatment may be an annealing treatment, the material of the capacitor support structure may include a first dielectric, the material of the conductive layer includes a metal material, and the material of the capacitor isolation structure may include a second dielectric, where the second dielectric is obtained by decomposing the first dielectric, and the second dielectric is an insulating substance. The first dielectric is generally an unstable dielectric (unstable dielectric), and the second dielectric is generally a stable insulating material (dielectric).
During the annealing process, the isolation protection structure 204 is used as a protection, and the chemical reaction is as follows: a + B → C + D, wherein: the reaction condition may be High temperature annealing (High temperature annealing), a denotes the capacitor support structure 202, which is usually made of unstable dielectric material, B denotes the conductive layer 203, which is usually made of metal material, C denotes other substances generated by the reaction, and D denotes the new product generated and remained by the reaction, i.e. the capacitor isolation structure 205, which is usually made of insulating dielectric material and is relatively stable.
It should be noted that, because the capacitor support structure is usually a medium with unstable properties, the capacitor support structure may be decomposed at a high temperature to obtain a stable insulating medium (capacitor isolation structure), that is, the capacitor isolation structure may be obtained by decomposing the capacitor support structure under a certain condition, and the capacitor isolation structure has more stable chemical properties compared to the capacitor support structure.
For example, the material of the capacitor support structure is an oxygen-containing compound, the material of the conductive layer is a metal, and at a high temperature, the oxygen-containing compound is decomposed to obtain oxygen and a stable insulating medium, wherein the oxygen and the metal of the conductive layer are subjected to a chemical combination reaction to generate an oxide, and the generated oxide is gasified at the high temperature, so that the stable insulating medium is finally left to serve as a capacitor isolation structure.
Fig. 15 is a schematic structural diagram of the capacitor isolation structure 205, as shown in fig. 15, a layer of capacitor isolation structure 205 is formed on the surface of the capacitor support structure 202, at this time, the capacitor pillars 201 are connected together through the capacitor isolation structure 205, and the capacitor isolation structure 205 can insulate and isolate the capacitor pillars 201 to prevent leakage between the capacitor pillars 201.
In one specific example, the material of capacitive support structure 202 comprises a silicon carbon nitrogen oxide compound, the material of conductive layer 203 comprises molybdenum, and the material of capacitive isolation structure 205 comprises a silicon carbon nitrogen compound.
In this particular example, the chemical reaction that occurs is of the formula:
wherein the annealing temperature of the annealing treatment can be 600-1000 ℃, here taking 800 ℃ as an example, the reactant silicon-carbon-oxygen-nitrogen compound (SiC) x O y N z ) And molybdenum (Mo) are both solids(s), and the reaction product, silicon carbonitride (SiC), is produced x N z ) Is solid, and the reaction product is molybdenum dioxide (MoO) 2 ) Is gas (g).
The reaction process can be divided into the following two reaction processes:
in the process of forming the capacitive isolation structure, like the reaction formula (1) and the reaction formula (2), siC x O y N z First, decomposition occurs at a high temperature (e.g., 800 ℃ C.) to produce SiC x N z And oxygen (O) 2 ) Oxygen and molybdenum react to form molybdenum dioxide, and the molybdenum dioxide is gasified at high temperature, and only SiC is finally reserved x N z And the capacitor isolation structure is used for insulating and isolating the capacitor column.
Wherein, in the silicon-carbon-oxygen-nitrogen compound, the atomic ratio of silicon, carbon, oxygen and nitrogen can be as follows: 1 (1.5-1.8) 0.05; in the silicon carbonitride compound, the atomic ratio of silicon, carbon and nitrogen may be: 1 (1.5-1.8) and 0.4.
After the formation of the capacitive isolation structure 205, the isolation protection structure 204 is removed, resulting in the semiconductor structure shown in fig. 16.
It should be noted that, as shown in fig. 16, the remained conductive layer 203 at this time may serve as a capacitor bottom electrode, after that, a capacitor dielectric layer may be formed on the surface of the capacitor bottom electrode, a capacitor Top electrode (Top Electrodes, TE) may be formed on the surface of the capacitor dielectric layer, and a capacitor filling structure may be filled in the gap of the capacitor Top electrode. The capacitor dielectric layer, the capacitor top electrode and the capacitor filling structure may be formed by deposition, the capacitor dielectric layer may be made of a High dielectric constant (High k) material such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, hafnium silicon oxide, hafnium oxynitride, or the like, the capacitor top electrode may be made of the same material as the conductive layer 203, and the capacitor filling structure may be made of polysilicon.
It should be further noted that the deposition process involved in the embodiments of the present disclosure may include: physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), ALD, and the like, the etching process may include dry etching, wet etching, and the like, and is selected specifically according to the characteristics of the material and the process conditions, which is not limited specifically.
Briefly, the disclosed embodiments provide a method for cutting a bottom electrode in a 3D DRAM by self-reaction, which relates to the manufacturing of integrated circuit chips, and is applied to the manufacturing of logic chip products, and the method is easy to implement and low in cost by selecting a suitable material system and using a self-aligned chemical reaction process instead of selective ALD to realize the cutting-off (Cut off) of a bottom electrode of a capacitor. For example, siC is selected x O y N z As the material of the capacitor supporting structure, oxygen is concentrated during the reaction processThe degree is increased to the maximum value due to SiC x O y N z The structure is unstable, oxygen can be decomposed to react with a metal electrode (namely, a conductive layer on the surface of the capacitor support structure) to generate metal oxide, and the metal oxide can be gasified at high temperature, so that a lower insulating medium is reserved, and the capacitor column is insulated and isolated.
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the steps of providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure; forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure; and carrying out heat treatment on the capacitor supporting structure and the conducting layer, and forming a capacitor isolation structure on the surface of the capacitor supporting structure, wherein the capacitor isolation structure is used for insulating and isolating at least one capacitor column. Like this, through thermal treatment at the surface formation electric capacity isolation structure of electric capacity bearing structure, block the conducting layer to the connection of electric capacity post, realize the insulation isolation to the electric capacity post, reduce electric capacity electric leakage, be favorable to promoting semiconductor structure's storage performance, this scheme not only the process is realized easily, and is with low costs moreover.
In another embodiment of the present disclosure, a semiconductor structure is provided, and the structure thereof can refer to fig. 16. As shown in fig. 16, the semiconductor structure may include:
a substrate, wherein at least one capacitor pillar 201 is formed in the substrate, and the capacitor pillar 201 penetrates through at least one capacitor support structure 202;
a conductive layer 203 formed on the surface of the capacitor pillar 201 and a capacitor isolation structure 205 formed on the surface of the capacitor support structure 202, wherein the capacitor isolation structure 205 is used for isolating at least one capacitor pillar 201.
In some embodiments, the material of the capacitive support structure comprises a first dielectric, the material of the conductive layer comprises a metal material, and the material of the capacitive isolation structure comprises a second dielectric, wherein the second dielectric is obtained by decomposing the first dielectric, and the second dielectric is an insulating substance.
In some embodiments, the material of the capacitive support structure comprises a silicon carbon nitrogen oxide compound, the material of the conductive layer comprises molybdenum, and the material of the capacitive isolation structure comprises a silicon carbon nitrogen compound.
In some embodiments, in the silicon oxycarbonitride, the atomic ratio of silicon, carbon, oxygen, and nitrogen is: 1, (1.5-1.8) 0.05; in the silicon carbonitride compound, the atomic ratio of silicon, carbon and nitrogen is: 1 (1.5-1.8) and 0.4.
It should be noted that the semiconductor structure provided by the embodiments of the present disclosure can be prepared by the preparation method provided by the foregoing embodiments, and details which are not disclosed in the embodiments of the present disclosure can be understood by referring to the description of the foregoing embodiments.
The embodiment of the disclosure provides a semiconductor structure, which comprises a substrate, at least one capacitor column formed in the substrate, and at least one capacitor support structure penetrated by the capacitor column; the capacitor isolation structure is used for insulating and isolating at least one capacitor column. Like this, the connection of conducting layer to the electric capacity post can be blocked to the electric capacity isolation structure, realizes the insulation isolation to the electric capacity post to can reduce the electric leakage of electric capacity, promote semiconductor structure's performance.
In still another embodiment of the present disclosure, referring to fig. 17, a schematic structural diagram of a semiconductor memory 170 provided in an embodiment of the present disclosure is shown. As shown in fig. 17, the semiconductor memory 170 includes the semiconductor structure according to any one of the previous embodiments.
In some embodiments, the semiconductor memory 170 may be a 3D DRAM.
In the embodiment of the present disclosure, for the DRAM, not only the memory specifications such as Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, etc., but also the memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., may be met, which is not limited herein.
Since the semiconductor structure includes the semiconductor structure described in the foregoing embodiment, capacitance leakage can be reduced, and performance of the semiconductor memory 170 can be improved.
The above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.
It should be noted that, in the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.
The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.
Features disclosed in several of the product embodiments provided in this disclosure may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (15)
1. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein at least one capacitor column is formed in the substrate and penetrates through at least one capacitor supporting structure;
forming a conductive layer on the surfaces of the capacitor column and the capacitor support structure;
and carrying out heat treatment on the capacitance supporting structure and the conductive layer, and forming a capacitance isolation structure on the surface of the capacitance supporting structure, wherein the capacitance isolation structure is used for insulating and isolating the at least one capacitance column.
2. The method of claim 1, wherein thermally treating the capacitive support structure and the conductive layer comprises:
forming an isolation protection structure between the conductive layers;
taking the isolation protection structure as protection, and annealing the capacitor supporting structure and the conductive layer to obtain the capacitor isolation structure;
and removing the isolation protection structure.
3. The method according to claim 2, wherein the annealing temperature of the annealing treatment is 600 to 1000 ℃.
4. The method of claim 1, wherein the material of the capacitive support structure comprises a first dielectric, the material of the conductive layer comprises a metallic material, and the material of the capacitive isolation structure comprises a second dielectric, wherein the second dielectric is decomposed from the first dielectric, and the second dielectric is an insulating material.
5. The method of claim 4, wherein the material of the capacitive support structure comprises a silicon oxycarbonitride, the material of the conductive layer comprises molybdenum, and the material of the capacitive isolation structure comprises a silicon carbonitride.
6. The method according to claim 5, wherein in the silicon oxycarbonitride, the atomic ratio of silicon, carbon, oxygen, and nitrogen is: 1 (1.5-1.8) 0.05; in the silicon carbon nitrogen compound, the atomic ratio of silicon to carbon to nitrogen is as follows: 1, (1.5-1.8) and 0.4.
7. The method of claim 1, wherein the providing a substrate comprises:
providing an initial substrate; the initial substrate comprises a transistor area and a capacitor area, and the transistor area and the capacitor area are sequentially arranged along a first direction;
forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region;
and carrying out metal silicification on the at least one initial capacitor column to obtain the at least one capacitor column.
8. The method of claim 7, wherein the providing an initial substrate comprises:
providing a substrate layer;
forming a stack structure over the substrate layer;
forming an oxide layer over the stacked structure;
and forming a dielectric layer above the oxide layer.
9. The method of claim 8, wherein the stacked structure comprises at least one stacked layer comprising a sacrificial layer and an active layer;
the forming a stack structure over the substrate layer, comprising:
forming the sacrificial layer over the substrate layer, forming the active layer over the sacrificial layer;
repeating the steps of forming the sacrificial layer and the active layer until the stacked structure is formed.
10. The method of claim 9, wherein forming at least one transistor structure in the transistor region and at least one initial capacitor pillar in the capacitor region comprises:
performing a first patterning process on the initial substrate, forming at least one isolation trench extending along the first direction in the initial substrate, and dividing the active layer in the transistor area into at least one active pillar and dividing the active layer in the capacitor area into at least one initial capacitor pillar by the at least one isolation trench;
forming an oxide structure in the at least one isolation trench;
performing second patterning on the initial substrate and the oxidation structure, forming at least one electrode groove in the transistor area, and forming at least one supporting groove in the capacitor area;
doping the active column to form a source electrode and a drain electrode of the transistor structure;
forming an electrode isolation structure in the electrode trench, and forming the capacitance support structure in the support trench.
11. The method of claim 10, wherein forming an electrode isolation structure in the electrode trench and a capacitive support structure in the support trench comprises:
forming a trench filling structure in the electrode trench and the support trench; the groove filling structure positioned in the electrode groove forms the electrode isolation structure, and the groove filling structure positioned in the support groove forms the capacitance support structure.
12. The method of claim 10, after forming the capacitive support structure in the support trench, further comprising:
removing the oxidation structure and the dielectric layer above the top surface plane of the oxidation layer;
removing the sacrificial layer and the oxide layer in the capacitance region to expose the initial capacitance pillar not covered by the capacitance support structure.
13. The method of claim 10, wherein, when the doping process is performed on the active pillar, the doping process comprises: and (4) gas-phase doping.
14. A semiconductor structure prepared according to the method of any one of claims 1 to 13, the semiconductor structure comprising:
the capacitor comprises a substrate, at least one capacitor column and at least one capacitor support structure, wherein the substrate is provided with the at least one capacitor column;
the capacitor comprises a conductive layer formed on the surface of the capacitor column and a capacitor isolation structure formed on the surface of the capacitor support structure, wherein the capacitor isolation structure is used for insulating and isolating the at least one capacitor column.
15. A semiconductor memory characterized in that it comprises the semiconductor structure of claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211477231.2A CN115915756A (en) | 2022-11-23 | 2022-11-23 | Preparation method of semiconductor structure, semiconductor structure and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211477231.2A CN115915756A (en) | 2022-11-23 | 2022-11-23 | Preparation method of semiconductor structure, semiconductor structure and semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115915756A true CN115915756A (en) | 2023-04-04 |
Family
ID=86480189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211477231.2A Pending CN115915756A (en) | 2022-11-23 | 2022-11-23 | Preparation method of semiconductor structure, semiconductor structure and semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115915756A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116322043A (en) * | 2023-05-17 | 2023-06-23 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
-
2022
- 2022-11-23 CN CN202211477231.2A patent/CN115915756A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116322043A (en) * | 2023-05-17 | 2023-06-23 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116322043B (en) * | 2023-05-17 | 2023-10-13 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10204913B2 (en) | Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof | |
| CN108028256B (en) | Robust nucleation layer for enhanced fluorine protection and stress reduction in 3D NAND word lines | |
| US7425740B2 (en) | Method and structure for a 1T-RAM bit cell and macro | |
| KR100984469B1 (en) | Silicided recessed silicon | |
| TWI458068B (en) | Vertical channel transistor array and manufacturing method thereof | |
| US7170125B2 (en) | Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium | |
| JP5147183B2 (en) | Capacitor having nanotube and method of manufacturing the same | |
| US7691743B2 (en) | Semiconductor device having a capacitance element and method of manufacturing the same | |
| WO2021133427A1 (en) | Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same | |
| KR100763745B1 (en) | A method of producing a semiconductor integrated circuit device | |
| JP2012151435A (en) | Method for manufacturing semiconductor device | |
| CN115915756A (en) | Preparation method of semiconductor structure, semiconductor structure and semiconductor memory | |
| US6423593B1 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
| JP2007073905A (en) | Semiconductor device and method for manufacturing same | |
| CN110391247B (en) | Semiconductor element and manufacturing method thereof | |
| JP4600836B2 (en) | Manufacturing method of semiconductor memory device | |
| KR100606256B1 (en) | Semiconductor integrated circuit device and the method of manufacturing the same | |
| US11659711B2 (en) | Three-dimensional memory device including discrete charge storage elements and methods of forming the same | |
| US20230011180A1 (en) | Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory | |
| CN116471840A (en) | Preparation method of semiconductor structure and semiconductor structure | |
| CN111799259A (en) | Integrated assembly including two different types of silicon nitride and method of forming an integrated assembly | |
| US20220036927A1 (en) | Integrated Assemblies Having Void Regions Between Digit Lines and Conductive Structures, and Methods of Forming Integrated Assemblies | |
| JP2000260957A (en) | Manufacture of semiconductor device | |
| JPS6315749B2 (en) | ||
| KR101040150B1 (en) | Semiconductor device and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |