CN116471840A

CN116471840A - Preparation method of semiconductor structure and semiconductor structure

Info

Publication number: CN116471840A
Application number: CN202310450436.XA
Authority: CN
Inventors: 黄猛
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-23
Filing date: 2023-04-23
Publication date: 2023-07-21

Abstract

The embodiment provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a stacked structure, wherein the stacked structure comprises a substrate and at least one layer of stacked layers formed on the substrate; the stacked layer includes a sacrificial layer and an active layer formed on the sacrificial layer; forming a first trench extending along a first direction in the stacked structure; the first trench divides the active layer into active pillars; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction; forming a source drain groove in the stacking structure, wherein the source drain groove exposes the first source drain region and the second source drain region; performing first in-situ selective epitaxial growth treatment on the first source drain region and the second source drain region to form a first doped region and a second doped region; forming a channel trench in the stacked structure, wherein the channel trench exposes a part of the channel region; and performing a second in-situ selective epitaxial growth treatment on the channel region exposed by the channel trench to form a channel layer. The embodiment can improve the doping uniformity of the transistor.

Description

Preparation method of semiconductor structure and semiconductor structure

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same.

Background

DRAM (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as a computer, and is constituted by a plurality of memory cells each typically including a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor, and the voltage on the word line can control the transistor to be turned on and off, so that the data information stored in the capacitor can be read or written through the bit line.

With the continuous miniaturization of memory structures such as DRAM, the structure of the semiconductor memory is spatially expanded upwards by using a three-dimensional (Three Dimensional, 3D) structure, which is greatly helpful for the development of memories such as dynamic random access memories.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

providing a stacked structure comprising a substrate and at least one stacked layer formed on the substrate; the stack layer includes a sacrificial layer and an active layer formed on the sacrificial layer;

forming a first trench extending in a first direction within the stacked structure; the first trench divides the active layer into active pillars; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction;

Forming a source-drain groove in the stacking structure, wherein the source-drain groove exposes the first source-drain area and the second source-drain area;

performing first in-situ selective epitaxial growth on the first source drain region and the second source drain region to form a first doped region and a second doped region;

forming a channel trench in the stacked structure, wherein the channel trench exposes a part of the channel region;

and performing a second in-situ selective epitaxial growth process on the channel region exposed by the channel trench to form a channel layer.

In some embodiments, along the first direction, the stacked structure includes a bit line region, a transistor region, and a capacitance region, and after providing the stacked structure, the method further includes:

forming a first oxide layer on the stacked structure;

forming a first isolation layer on the first oxide layer;

correspondingly, forming a first trench extending along a first direction in the stacked structure, including:

forming the first trench extending in the first direction in the first isolation layer, the first oxide layer and the stacked structure in the transistor region and the bit line region;

the active layer in the transistor region is divided into the active pillars by the first trenches, and the active layer in the capacitor region is divided into the capacitor pillars by the first trenches.

In some embodiments, forming a source-drain trench within the stacked structure includes:

forming a second oxide layer in the first groove; the top surface of the second oxide layer is flush with the top surface of the first isolation layer;

forming a source drain mask layer above the top surface plane of the first isolation layer; wherein the source-drain mask layer completely covers the first isolation layer and the second oxide layer above the bit line region and the capacitor region, and has a source-drain pattern extending in a second direction above the transistor region;

pattern transfer is carried out by taking the source-drain mask layer as a mask, and the first isolation layer, the sacrificial layer and the second oxide layer below the area exposed by the source-drain pattern are removed to form the source-drain groove;

the source drain grooves comprise a first source drain groove and a second source drain groove, the first source drain groove exposes the first source drain area, and the second source drain groove exposes the second source drain area.

In some embodiments, after exposing the first source drain region and the second source drain region, the method further comprises:

thinning the first source drain region and the second source drain region;

Correspondingly, performing a first in-situ selective epitaxial growth process on the first source drain region and the second source drain region, including:

and performing first in-situ selective epitaxial growth treatment on the thinned first source drain region and the thinned second source drain region to form the first doped region and the second doped region.

In some embodiments, after forming the first doped region and the second doped region, the method further comprises:

forming a second isolation layer in the source drain groove;

removing the remaining sacrificial layer, the first oxide layer and the second oxide layer to form a second groove;

forming a third oxide layer in the second trench and above the second isolation layer;

forming a word line isolation structure in the third oxide layer; and the active columns and the word line isolation structures are arranged at intervals along the second direction.

In some embodiments, forming a word line isolation structure within the third oxide layer includes:

forming an isolation mask layer on the third oxide layer; wherein the isolation mask layer completely covers the third oxide layer over the bit line region and the capacitor region, the isolation mask layer having an isolation pattern extending in a first direction over the transistor region, the isolation pattern exposing a portion of the third oxide layer between adjacent active pillars;

Pattern transfer is carried out by taking the isolation mask layer as a mask, and the third oxide layer below the area exposed by the isolation pattern is removed to form an isolation trench; wherein the isolation trench does not expose the active pillars;

and forming the word line isolation structure in the isolation trench.

In some embodiments, forming a channel trench within the stacked structure includes:

removing the third oxide layer adjacent to the word line isolation structure along a third direction to form an initial channel trench, wherein the initial channel trench exposes two sides of the channel region along the second direction;

thinning the exposed channel region to form the channel groove;

correspondingly, performing a second in-situ selective epitaxial growth process on the channel region exposed by the channel trench to form a channel layer, including:

and performing second in-situ selective epitaxial growth treatment on the channel region after the thinning treatment to form the channel layer, wherein the channel layer is not formed in the initial channel groove.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure comprising:

a stacked structure comprising a substrate and at least one stacked layer formed on the substrate; wherein the stacked layer comprises:

An active pillar extending along a first direction; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction;

the first doped region is formed on the surface of the first source drain region and the second doped region is formed on the surface of the second source drain region;

a channel layer formed on the surface of the channel region; and the channel layer is formed on both side surfaces of the channel region in the second direction.

In some embodiments, the stacked structure includes a bit line region, a transistor region, and a capacitance region along a first direction, the active pillar being located in the transistor region; the semiconductor structure further includes:

the capacitor column is connected with the active column and is positioned in the capacitor region;

the cross-sectional dimensions of the first source drain region, the channel region and the second source drain region are smaller than the cross-sectional dimensions of the capacitor column along the second direction;

the first doped region completely surrounds the first source drain region, and the second doped region completely surrounds the second source drain region. In some embodiments, the semiconductor structure further comprises a word line isolation structure and a word line structure formed in the transistor region, wherein:

the word line isolation structures and the word line structures are arranged at intervals along the second direction, and one of the word line structures is connected with a set of channel layers arranged along the third direction.

The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a stacked structure, wherein the stacked structure comprises a substrate and at least one layer of stacked layers formed on the substrate; the stacked layer includes a sacrificial layer and an active layer formed on the sacrificial layer; forming a first trench extending along a first direction in the stacked structure; the first trench divides the active layer into active pillars; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction; forming a source drain groove in the stacking structure, wherein the source drain groove exposes the first source drain region and the second source drain region; performing first in-situ selective epitaxial growth treatment on the first source drain region and the second source drain region to form a first doped region and a second doped region; forming a channel trench in the stacked structure, wherein the channel trench exposes a part of the channel region; and performing a second in-situ selective epitaxial growth treatment on the channel region exposed by the channel trench to form a channel layer. Thus, the source electrode and the drain electrode (the first doping region and the second doping region) of the transistor are formed through the first in-situ selective epitaxial growth process, and the channel of the transistor is formed through the second in-situ selective epitaxial growth process, so that the channel of the transistor and the doping uniformity of the source electrode and the drain electrode can be improved, and the complex doping problem of the 3D DRAM is solved.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

FIGS. 2 through 29 are schematic diagrams of structures obtained during the fabrication of semiconductor structures using the methods provided by embodiments of the present disclosure;

fig. 30 is a schematic diagram of a composition structure of a semiconductor memory according to an embodiment of the present disclosure.

The reference numerals are as follows:

a substrate (201); a sacrificial layer (202); an active layer (203); stacking layers (204); a first oxide layer (205); a first isolation layer (206); a first trench (207); a bit line sacrificial layer (208); an active column (209); a first source drain region (2091); a second source drain region (2092); a channel region (2093); a capacitor column (210); a second oxide layer (211); a source drain mask layer (212); a first spin-on hard mask layer (2121); a first anti-reflection layer (2122); a first photoresist layer (213); a source drain trench (214); a first source drain trench (2141); a second source drain trench (2142); a first doped region (2151); a second doped region (2152); a second isolation layer (216); a second trench (217); a third oxide layer (218); an isolation mask layer (219); a second spin-on hard mask layer (2191); a second anti-reflection layer (2192); a second photoresist layer (220); an isolation trench (221); word line isolation structures (222); a second mask layer (223); an initial channel trench (224); a channel trench (225); a channel layer (226); a fourth oxide layer (227); a conductive layer (228); a first conductive layer (2281); a second conductive layer (2282); a third separator (229); a capacitance trench (230); a capacitive structure (231); a first capacitance layer (2311); a dielectric layer (2312); a second capacitance layer (2313); a capacitance filling structure (232); metal silicide pillars (233); a bit line (234); a semiconductor memory (30).

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the related disclosure and not limiting thereof. It should be further noted that, for convenience of description, only the portions related to the disclosure are shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

In a transistor, the distribution of the electrodes is typically: the left and right sides of the Metal Gate are Source and Drain (D), respectively. In the stacked structure of 3D DRAM, doping is an important factor in meeting the device characterization requirements, and during the process, 3D Doping (3D Doping) of the stacked semiconductor structure is required to form a transistor. The channel of the Junction transistor (transistor type is Junction, junction Tr) requires uniform P-type doping, and BLC (bit line contact structure, which may be a source or an electrode connected to the source, indicating a region where the transistor contacts the bit line) and NC (capacitance contact structure, which may be a drain or an electrode connected to the drain, indicating a region where the transistor contacts the capacitance) require high doping to reduce the contact Resistance (RS). However, conventional implantation schemes are difficult to meet the requirements of 3D DRAM for the following reasons: (1) a high aspect ratio structure; (2) surface damage; (3) the doping uniformity of the channel is poor. Thus, a new doping scheme is needed for forming 3D DRAM.

Based on this, the embodiment of the disclosure provides a method for preparing a semiconductor structure, which includes: providing a stacked structure, wherein the stacked structure comprises a substrate and at least one layer of stacked layers formed on the substrate; the stacked layer includes a sacrificial layer and an active layer formed on the sacrificial layer; forming a first trench extending along a first direction in the stacked structure; the first trench divides the active layer into active pillars; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction; forming a source drain groove in the stacking structure, wherein the source drain groove exposes the first source drain region and the second source drain region; performing first in-situ selective epitaxial growth treatment on the first source drain region and the second source drain region to form a first doped region and a second doped region; forming a channel trench in the stacked structure, wherein the channel trench exposes a part of the channel region; and performing a second in-situ selective epitaxial growth treatment on the channel region exposed by the channel trench to form a channel layer. Thus, the source electrode and the drain electrode (the first doping region and the second doping region) of the transistor are formed through the first in-situ selective epitaxial growth process, and the channel of the transistor is formed through the second in-situ selective epitaxial growth process, so that the channel of the transistor and the doping uniformity of the source electrode and the drain electrode can be improved, and the complex doping problem of the 3D DRAM is solved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 1, a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown. As shown in fig. 1, the method includes:

s101: providing a stacked structure, wherein the stacked structure comprises a substrate and at least one layer of stacked layers formed on the substrate; the stacked layer includes a sacrificial layer and an active layer formed on the sacrificial layer.

It should be noted that, the method provided by the embodiment of the present disclosure is applied to preparing a semiconductor structure, which may be a 3D semiconductor structure, and is mainly applied to a semiconductor memory such as a DRAM (particularly a 3D DRAM).

Wherein, providing a stacked structure may include:

providing a substrate 201;

forming a sacrificial layer 202 on a substrate 201, and forming an active layer 203 on the sacrificial layer 202 to obtain a stacked layer 204;

the formation of a plurality of stacked layers 204 is continued to obtain at least one stacked layer 204.

It should be noted that fig. 2 is a schematic diagram of a structure obtained after forming a stacked structure according to an embodiment of the disclosure. As shown in fig. 2, the upper right corner is a schematic diagram of a top view of the currently obtained structure, and the rest are schematic diagrams of sections aa ', bb ', cc ', dd ' and ee ' in top view, respectively, all of which have the same correspondence, and will not be specifically described.

The substrate 201 may be a silicon (Si) substrate or other suitable substrate materials such as silicon, germanium (Ge), silicon germanium compound, etc., for example, a doped or undoped monocrystalline silicon substrate, a polycrystalline silicon substrate, etc., which is not specifically limited in this embodiment, and a silicon substrate is taken as an example.

A sacrificial layer 202 is formed over a substrate 201. The sacrificial layer 202 may be formed over the substrate 201 by deposition or epitaxy, and the material of the sacrificial layer 202 may be silicon germanium (SiGe) or the like which is easy to be etched.

An active layer 203 is formed over the sacrificial layer 202. Wherein the active layer 203 may be formed over the sacrificial layer 202 by deposition or epitaxy or the like. The material of the active layer 203 may be silicon or the like as a material of the active region, which generally has the same material as the substrate 201, and thus, in the drawings, the active layer 203 and the substrate 201 are illustrated as the same filling. As shown in fig. 2, the sacrificial layer 202 and the active layer 203 thereabove constitute a stacked layer 204.

It should also be noted that the embodiments of the present disclosure are mainly used for preparing 3D semiconductor structures, and thus, the multi-layer stack layer 204 may be continuously formed, thereby forming a 3D stacked structure. In this embodiment, N stacked layers 204 may be formed, N being an integer greater than or equal to 1. As an example, referring to fig. 2, a 3-layer stack 204 is shown.

In this way, by forming the multi-layered stack layer 204, a 3D semiconductor structure is prepared, so that the memory density can be increased, which is advantageous for downsizing of the semiconductor memory.

S102: forming a first trench extending along a first direction in the stacked structure; the first trench divides the active layer into active pillars; the active column comprises a first source drain region, a channel region and a second source drain region along a first direction.

It should be noted that, in the embodiment of the present disclosure, for convenience of description, the stacked structure may be divided into a bit line region, a transistor region (or referred to as a word line region, a channel region) and a capacitor region, which are sequentially arranged along the first direction, as shown in fig. 2. The Bit Line region is used for forming a Bit Line (BL) later, the transistor region is used for forming a transistor and a Word Line (WL) later, and the Capacitor region is used for forming a Capacitor (CAP) later.

Among them, the first trench 207 is mainly formed in the transistor region and the capacitor region, that is, the first trench 207 penetrates the transistor region and the capacitor region but is not formed in the bit line region.

It should be further noted that, before forming the first trench 207, or after providing the stacked structure, the method may further include:

Forming a first oxide layer 205 on the stacked structure;

forming a first isolation layer 206 on the first oxide layer 205;

fig. 3 is a schematic view of the structure obtained after forming the first isolation layer 206, in which the first oxide layer 205 may be formed over the last active layer 203 by deposition, and the material of the first oxide layer 205 may be silicon oxide (SiO) or the like; the first isolation layer 206 may be formed over the first oxide layer 205 by deposition, and a material of the first isolation layer 206 may be silicon nitride (SiN) or the like.

Forming the first trench 207 extending in the first direction in the stacked structure on the basis of the structure shown in fig. 3 may include:

forming a first trench 207 extending in a first direction in the first isolation layer 206, the first oxide layer 205 and the stacked structure in the transistor region and the bit line region;

the active layer 203 in the transistor region is divided into active pillars 209 by the first trench 207, and the active layer 203 in the capacitor region is divided into capacitor pillars 210 by the first trench 207.

Note that, as described above, in this embodiment, the first oxide layer 205 and the first isolation layer 206 may also be formed above the stacked structure, and then, when the first trench 207 is formed, the first trench 207 is formed within the first isolation layer 206, the first oxide layer 205 and the stacked structure. And the first trench 207 is not formed in the bit line region but in the transistor region and the capacitor region.

Fig. 4 is a schematic diagram of the structure obtained after the first trench 207 is formed. As shown in fig. 4, after the first trench 207 is formed, for the active layer 203, a portion located in the bit line region remains as it is, which may be referred to as a bit line sacrificial layer 208, and a portion located in the transistor region and the capacitor region is divided into pillars by the first trench 207 (the material of the active layer 203 may be silicon, and thus the resulting pillars may be referred to as silicon pillars). On the basis of fig. 4, taking one active layer 203 in the cross section shown in ff', fig. 5 is a schematic structural diagram of one active layer 203 provided in an embodiment of the disclosure. As shown in fig. 5, the silicon pillars located in the transistor region are denoted as active pillars 209, and the silicon pillars located in the capacitor region are denoted as capacitor pillars 210, and further, in the first direction, the active pillars 209 include a first source drain region 2091, a channel region 2093, and a second source drain region 2092. That is, for one silicon column, along a first direction, it comprises in order: a first source drain region 2091, a channel region 2093, a second source drain region 2092, and a capacitor pillar 210.

Thus, in fig. 4 and subsequent figures, the active layer 203 shown in the aa 'cross-section is the bit line sacrificial layer 208, the active layer 203 shown in the cc' cross-section is the channel region 2093, the active layer 203 shown in the dd 'cross-section is the second source drain region 2092, and the active layer 203 shown in the ee' cross-section is the capacitor pillar 210. It is understood that the active layer 203 in the gg' cross section corresponds to the first source drain region 2091, which is not shown in the drawings.

In a specific implementation, the manner of forming the first trench may be:

forming a first mask layer on the first isolation layer; wherein the first mask layer completely covers the first isolation layer above the bit line region, and has a first pattern extending along a first direction above the transistor region and the capacitor region;

and performing pattern transfer by taking the first mask layer as a mask, and removing the first isolation layer exposed by the first pattern, the first oxide layer below the first isolation layer, at least one layer of stacked layer and part of the substrate to form a first groove.

It should be noted that the first mask layer may have an "interdigital" structure, and in the bit line region, the first mask layer completely covers the first isolation layer above the bit line region, and in the transistor region and the capacitor region, the first mask layer extends along the first direction and is arranged at intervals to form the first pattern.

The first mask layer may be a single-layer mask or a multi-layer composite mask, and the material of the first mask layer may be Photoresist (PR) and/or Spin On Hard mask (SOH) and/or silicon oxynitride (SION, which may be used as an anti-reflection layer), etc., which are not limited herein, and the first mask layer may be formed by deposition.

The first mask layer is used as a mask, the first pattern is transferred to the first isolation layer, the first oxide layer and the stacked structure, and the first mask layer is removed, so that the structure shown in fig. 4 can be obtained. The pattern transfer may be performed by: the first isolation layer, the first oxide layer and the at least one stacked layer under the region exposed by the first pattern are removed by an etching process, and the underlying substrate is removed to a certain depth.

S103: and forming a source-drain groove in the stacking structure, wherein the source-drain groove exposes the first source-drain area and the second source-drain area.

S104: and performing first in-situ selective epitaxial growth treatment on the first source drain region and the second source drain region to form a first doped region and a second doped region.

Step S103 and step S104 are steps of forming a source and a drain of the transistor.

Wherein forming the source-drain trench 214 in the stacked structure includes:

forming a second oxide layer 211 in the first trench 207; the top surface of the second oxide layer 211 is flush with the top surface of the first isolation layer 206;

forming a source drain mask layer 212 above the top surface plane of the first isolation layer 206; wherein the source drain mask layer 212 completely covers the first isolation layer 206 and the second oxide layer 211 over the bit line region and the capacitor region, the source drain mask layer 212 having a source drain pattern extending in the second direction over the transistor region;

Pattern transfer is carried out by taking the source-drain mask layer 212 as a mask, and the first isolation layer 206, the sacrificial layer 202 and the second oxide layer 211 below the area exposed by the source-drain pattern are removed to form a source-drain groove 214;

the source-drain trenches 214 include a first source-drain trench 2141 and a second source-drain trench 2142, wherein the first source-drain trench 2141 exposes the first source-drain region 2091, and the second source-drain trench 2142 exposes the second source-drain region 2092.

Fig. 6 is a schematic diagram of the structure obtained after the second oxide layer 211 is formed. The second oxide layer 211 may have the same material as the first oxide layer 205, for example, silicon oxide, so in the drawings, the second oxide layer 211 and the first oxide layer 205 are shown in the same filling pattern, and in the following drawings, the boundaries of the two are not shown. The second oxide layer 211 may be formed by deposition.

As shown in fig. 6, the second oxide layer 211 completely fills the first trench 207, and its top surface is flush with the top surface of the first isolation layer 206. In the depositing of the second oxide layer 211, the top surface of the second oxide layer 211 may be higher than the top surface of the first isolation layer 206 due to practical process limitations, and at this time, chemical mechanical polishing (Chemical Mechanical Polish, CMP) may be performed on the second oxide layer 211, and the first isolation layer 206 is used as a polishing stop layer, so that the top surface of the second oxide layer 211 is level with the top surface of the first isolation layer 206.

Processing continues on the basis of the resulting structure of fig. 6 to obtain source drain trenches 214.

Fig. 7 is a schematic diagram of a structure obtained after forming the first photoresist layer 213, and as shown in fig. 7, the source drain mask layer 212 includes a first spin-on hard mask layer 2121 and a first anti-reflection layer 2122. The source-drain mask layer 212 may be formed by: a first spin-on hard mask layer 2121 is deposited over the top surface plane of the first isolation layer 206 and a first anti-reflective layer 2122 is deposited over the first spin-on hard mask layer 2121; the material of the first spin-on hard mask layer 2121 may be SOH, the material of the first anti-reflection layer 2122 may be sia, and the first anti-reflection layer 2122 may improve the reliability of the process, reduce the load effect of lithography, and improve the adverse effect of different material reflectivities on the process effect.

A first photoresist layer 213 is formed on the first anti-reflection layer 2122. As shown in fig. 7, the first photoresist layer 213 completely covers the first anti-reflection layer 2122 over the bit line region and the capacitor region, and the first photoresist layer 213 has a source drain pattern extending in the second direction over the transistor region, and an exposed region of the source drain pattern is a region corresponding to the first source drain region 2091 and the second source drain region 2092. The material of the first photoresist layer 213 is PR, which may be deposited. It will be appreciated that the gg 'interface has the same cross-section as the dd' interface.

In this embodiment, the first direction, the second direction, and the third direction are intersecting each other, and the first direction, the second direction, and the third direction are not located on the same plane. For example: the first direction and the second direction intersect and are positioned on the same plane, the plane is recorded as a first plane, the third direction intersects with the first plane, the first plane can be positioned by the first direction and the second direction, and the third direction intersects with the plane where the first direction and the second direction are positioned. Specifically, the first plane may be a horizontal plane, the first direction and the second direction are not parallel, the first direction and the second direction intersect with each other at a certain angle, and the third direction is a direction which is not parallel to the first plane and has a certain included angle with the first plane. In the present embodiment, the three-dimensional rectangular coordinate system is described as being formed by two perpendicular directions of the first direction, the second direction, and the third direction, but the semiconductor structure is not limited thereto.

In pattern transfer, the first spin-on hard mask layer 2121 and the first anti-reflection layer 2122 under the exposed region of the source/drain pattern are removed first, and the first photoresist layer 213 is removed to transfer the source/drain pattern to the source/drain mask layer 212, and further, the first isolation layer 206, the sacrificial layer 202 and the second oxide layer 211 under the exposed region are removed with the source/drain mask layer 212 as a mask, and the source/drain mask layer 212 is removed, so that the source/drain trench 214 is formed in the stacked structure, resulting in the structure shown in fig. 8. The first spin-on hard mask layer 2121, the first anti-reflection layer 2122, the first photoresist layer 213, the first isolation layer 206, the sacrificial layer 202, and the second oxide layer 211 may be etched.

As shown in fig. 8, the source drain trench 214 may include a first source drain trench 2141 and a second source drain trench 2142. The active layer 203 exposed by the first source-drain trench 2141 is a first source-drain region 2091, and the active layer 203 exposed by the second source-drain trench 2142 is a second source-drain region 2092.

In some embodiments, after exposing the first source drain region 2091 and the second source drain region 2092, the method may further comprise:

the first source drain region 2091 and the second source drain region 2092 are subjected to thinning treatment.

Fig. 9 is a schematic diagram of a structure obtained by thinning the first source drain region 2091 and the second source drain region 2092. As shown in fig. 9, the first source drain region 2091 and the second source drain region 2092 are thinned, so that the first source drain region 2091 and the second source drain region 2092 have smaller dimensions than those of fig. 8, and the active pillars 209 at the corresponding positions are thinned, so that the source and the drain are formed at the positions subsequently. The first source drain region 2091 and the second source drain region 2092 may be thinned by etching, such as lateral etching or isotropic etching.

It will be appreciated that in this embodiment, the first source drain region 2091 and the second source drain region 2092 are columnar, and the thinning treatment of the first source drain region 2091 and the second source drain region 2092 may be to etch and remove the first source drain region 2091 and the second source drain region 2092 by one week, so that the size thereof becomes smaller. In addition, for the active layer 203 adjacent to the first oxide layer 205, the source drain trench 214 does not completely expose the side surface thereof, and thus, a portion in contact with the first oxide layer 205 is not thinned during the thinning process, and this portion of the active layer 203 may serve as a redundant structure (dummy) in the semiconductor structure.

In some embodiments, a first in-situ selective epitaxial growth process is performed on the first source drain region 2091 and the second source drain region 2092, comprising:

a first in-situ selective epitaxial growth process is performed on the thinned first source drain region 2091 and second source drain region 2092 to form a first doped region 2151 and a second doped region 2152.

It should be noted that fig. 10 is a schematic diagram of the structure obtained after the first doped region 2151 and the second doped region 2152 are formed. As shown in fig. 10, after the first in-situ selective epitaxial growth process, the first doped region 2151 supplements the region of the first source drain region 2091 removed by the thinning process, and the second doped region 2152 supplements the region of the second source drain region 2092 removed by the thinning process.

In the semiconductor memory, the drain of the transistor is typically connected to a capacitor, and the source of the transistor is typically connected to a bit line. Thus, in embodiments of the present disclosure, the first doped region 2151 may function as a source for the transistor and the second doped region 2152 may function as a drain for the transistor.

Here, in performing the first in situ selective epitaxial growth, the grown first and second doped regions 2151 and 2152 may be n-type doped silicon or p-type doped silicon, particularly in combination with transistor types. This embodiment takes n-doped silicon as an example.

In this way, when the source and the drain of the transistor are formed, the in-situ growth and the epitaxial growth are combined to selectively grow the first source drain region 2091 and the second source drain region 2092 of the silicon pillar, on the one hand, the in-situ growth can ensure that the interface between the first doped region 2151 and the first source drain region 2091 and between the second doped region 2152 and the second source drain region 2092 is stable and pollution-free, and the electrical stability of the structure is improved; on the other hand, the epitaxial growth ensures that the impurity concentration can be conveniently controlled, the thicknesses of the first doped region 2151 and the second doped region 2152 obtained by the growth can be precisely controlled, selective growth can be realized, and the obtained structure has good integrity and high growth speed. Finally, the doping uniformity of the source electrode and the drain electrode of the transistor can be improved, and the complex doping problem of the 3D DRAM is solved.

S105: a channel trench is formed in the stacked structure, the channel trench exposing a portion of the channel region.

S106: and performing a second in-situ selective epitaxial growth treatment on the channel region exposed by the channel trench to form a channel layer.

Step S105 and step S106 are steps for forming a channel of the transistor.

In some embodiments, after forming the first doped region 2151 and the second doped region 2152, the method may further include:

forming a second isolation layer 216 in the source drain trench 214;

removing the remaining sacrificial layer 202, the first oxide layer 205 and the second oxide layer 211 to form a second trench 217;

forming a third oxide layer 218 within the second trench 217 and over the second isolation layer 216;

forming a word line isolation structure 222 within the third oxide layer 218; wherein, along the second direction, the active pillars 209 and the word line isolation structures 222 are spaced apart.

Note that fig. 11 is a schematic view of the structure obtained after the second isolation layer 216 is formed. As shown in fig. 11, the second isolation layer 216 completely fills the source drain trench 214. The second isolation layer 216 may be formed by depositing, and the second isolation layer 216 and the first isolation layer 206 may be made of the same material, for example, silicon nitride, so that in the drawings, the two are shown in the same filling pattern, and the following drawings do not show the boundary between the first isolation layer 206 and the second isolation layer 216, and meanwhile, in the schematic diagram of the bb' interface, the second isolation layer 216 is not particularly labeled.

Fig. 12 is a schematic view of the resulting structure after forming the second trench 217. As shown in fig. 12, the remaining sacrificial layer 202, the first oxide layer 205, and the second oxide layer 211 are all removed, forming a second trench 217. Here, the sacrificial layer 202, the first oxide layer 205, and the second oxide layer 211 may be removed by etching, for example, isotropic etching.

Fig. 13 is a schematic diagram of the resulting structure after formation of the third oxide layer 218. As shown in fig. 13, the third oxide layer 218 completely fills the second trench 217 and is also formed above the top surface plane of the first isolation layer 206. The third oxide layer 218 may be formed by depositing, and the material of the third oxide layer 218 may be silicon oxide, that is, the third oxide layer 218, the first oxide layer 205, and the second oxide layer 211 have the same material, so the three are shown in the same filling pattern in the drawings.

The third oxide layer 218 is then processed to form a word line isolation structure 222 within the third oxide layer 218. In some embodiments, forming the word line isolation structure 222 within the third oxide layer 218 includes:

forming an isolation mask layer 219 on the third oxide layer 218; wherein the isolation mask layer 219 completely covers the third oxide layer 218 over the bit line region and the capacitor region, and the isolation mask layer 219 has an isolation pattern extending in the first direction over the transistor region, the isolation pattern exposing a portion of the third oxide layer 218 between adjacent active pillars 209;

pattern transfer is performed by taking the isolation mask layer 219 as a mask, and the third oxide layer 218 below the region exposed by the isolation pattern is removed to form an isolation trench 221; wherein the isolation trench 221 does not expose the active pillar 209;

A word line isolation structure 222 is formed within the isolation trench 221.

Note that the isolation mask layer 219 is formed in a similar manner to the source drain mask layer 212. Fig. 14 is a schematic view of the structure obtained after forming the second photoresist layer 220 on the basis of fig. 13, and as shown in fig. 14, the isolation mask layer 219 includes a second spin-on hard mask layer 2191 and a second anti-reflection layer 2192. The manner of forming the initial isolation mask layer 219 may be: depositing a second spin-on hard mask layer 2191 over the third oxide layer 218, and depositing a second anti-reflective layer 2192 over the second spin-on hard mask layer 2191; the second spin-on hard mask layer 2191 may have the same material as the first spin-on hard mask layer 2121, and the second anti-reflection layer 2192 may have the same material as the first anti-reflection layer 2122.

A second photoresist layer 220 is formed over the second anti-reflective layer 2192. As shown in fig. 14, the second photoresist layer 220 completely covers the second anti-reflection layer 2192 over the bit line region and the capacitor region, and the second photoresist layer 220 has an isolation pattern extending along the first direction over the transistor region. The second photoresist layer 220 is formed by depositing PR.

As shown in fig. 14, in the second direction, a distance between adjacent active pillars 209 (i.e., adjacent first source drain regions 2091 or adjacent second source drain regions 2092) is D1, a width of a region exposed by the second photoresist layer 220 is D2, where D2 is smaller than D1, and extends in the third direction, i.e., a region corresponding to D1 includes a region corresponding to D2.

The second photoresist layer 220 is used as a mask to remove the second spin-on hard mask layer 2191 and the second anti-reflective layer 2192 under the exposed area of the second photoresist layer 220, and the second photoresist layer 220 is removed to transfer the isolation pattern to the isolation mask layer 219. The second photoresist layer 220, the second anti-reflection layer 2192 and the second spin-on hard mask layer 2191 may be removed by etching.

The third oxide layer 218 below the exposed region is removed using the isolation mask layer 219 as a mask, and the isolation mask layer 219 is removed, thereby forming an isolation trench 221, resulting in the structure shown in fig. 15. The third oxide layer 218 and the isolation mask layer 219 may be removed by etching. As shown in fig. 15, the isolation trench does not expose the active layer 203 (i.e., does not expose the active pillars 209).

A word line isolation structure 222 is formed within the isolation trench 221 resulting in the structure shown in fig. 16. The word line isolation structure 222 may be formed by deposition, and the material of the word line isolation structure 222 may be the same as that of the first isolation layer 206 and the second isolation layer 216, for example, both are insulating materials such as silicon nitride, so that insulating isolation of the device can be achieved, where the word line isolation structure 222 mainly implements insulating isolation of subsequently formed word lines, so that good insulating performance of the semiconductor structure is ensured, and leakage is avoided.

In some embodiments, forming the channel trench 225 within the stacked structure may include:

removing the third oxide layer 218 adjacent to the word line isolation structure 222 along the third direction to form an initial channel trench 224, the initial channel trench 224 exposing both sides of the channel region 2093 along the second direction;

the exposed channel region 2093 is thinned to form a channel trench 225.

Wherein the removing of the third oxide layer 218 adjacent to the word line isolation structure 222 along the third direction forms an initial channel trench 224, which may include:

forming a second mask layer 223 on the top surface plane of the third oxide layer 218; and the second mask layer 223 exposes a region above the transistor region;

the third oxide layer 218 is removed in the third direction by pattern transfer using the second mask layer 223 as a mask, forming an initial channel trench 224.

Note that the second mask layer 223 is formed in a similar manner to the manner of forming the source/drain mask layer 212 described above, and the formation thereof will not be described in detail here. Fig. 17 is a schematic view of the structure obtained after forming the second mask layer 223 on the basis of fig. 16.

Pattern transfer is performed using the second mask layer 223 as a mask, the third oxide layer 218 under the exposed area of the second mask layer 223 is removed, and the second mask layer 223 is removed, so that an initial trench 224 is formed, and the structure shown in fig. 18 is obtained. The third oxide layer 218 and the second mask layer 223 may be removed by etching.

As shown in fig. 18, the bit line region and the capacitor region still maintain the same structure as in fig. 17, the third oxide layer 218 over the first isolation layer 206 is removed in the transistor region, and at the same time, since the etching selectivity of silicon nitride (word line isolation structure 222 and first isolation layer 206) and silicon oxide (third oxide layer 218) is different, after the third oxide layer 218 over the first isolation layer 206 is removed, etching is continued downward in the third direction, so that the third oxide layer 218 between the side surface of the word line isolation structure 222 and the side surface plane of the active column 209 can be removed, resulting in the initial channel trench 224.

At this time, the initial channel trench 224 exposes the surfaces of the channel region 2093 on both sides in the second direction, as shown by the dashed oval in the cc' interface schematic diagram in fig. 18. That is, in this embodiment, the channel region 2093 may have a square column shape including four sides, two sides in the second direction and two sides in the third direction, respectively, the two sides in the second direction being shown by the dashed oval in the cc' interface schematic diagram in fig. 18, being exposed by the initial channel trench 224, and the two sides in the third direction being covered by the third oxide layer 218.

As shown in fig. 18, the initial channel trench 224 exposes the word line isolation structure 222 and the active pillar 209 (specifically, the channel region 2093). The channel region 2093 exposed by the initial channel trench 224 is subjected to a thinning process. Here, when the channel region 2093 is thinned, a portion of the channel region 2093 exposed by the initial channel trench 224 may be removed by means of lateral etching, thereby forming a recess as a portion where a channel of a transistor is formed later, and the resulting structure is shown in fig. 19. The channel trench 225 includes an initial channel trench 224 and a recess (shown as a dashed oval in the cc' interface schematic of fig. 19) obtained by thinning the active pillar 209.

In some embodiments, a second in situ selective epitaxial growth process is performed on the channel region 2093 exposed by the channel trench 225 to form the channel layer 226, including:

a second in-situ selective epitaxial growth process is performed on the thinned channel region 2093 to form a channel layer 226, and the channel layer 226 is not formed within the initial channel trench 224.

Fig. 20 is a schematic diagram of the structure obtained after the channel layer 226 is formed. As shown in fig. 20, a channel layer 226 is formed in the aforementioned recess while also being formed on the surface of the substrate 201 exposed by the channel trench 225. That is, after the second in-situ selective epitaxial growth process, the channel layer 226 supplements the region of the channel region 2093 that was removed by the thinning process. The channel layer 226 serves as a channel of the transistor.

Here, the grown channel layer 226 may be n-type doped silicon or p-type doped silicon, particularly in combination with transistor types, when performing the second in situ selective epitaxial growth. This embodiment takes p-type doped silicon as an example.

It can be seen that, in this embodiment, there are two thinning processes, taking the shape of the active pillar 209 as a pillar body including four sides as an example, the first thinning process is performed for the first source drain region 2091 and the second source drain region 2092, and is performed for all four sides of the pillar body; the second thinning process is performed for the channel region 2093, and thinning is performed only for the two opposite sides of the pillar in the second direction.

For doping types, specifically, the first in-situ selective epitaxial growth treatment is to in-situ selective epitaxial growth of n-type doped silicon; the second in-situ selective epitaxial growth process is to in-situ selectively epitaxially grow p-type doped silicon. Thereby yielding n-doped source and drain, and p-doped channel.

Or the first in-situ selective epitaxial growth treatment is in-situ selective epitaxial growth of p-type doped silicon; the second in-situ selective epitaxial growth treatment is to in-situ selective epitaxial grow n-type doped silicon. Thereby obtaining p-doped source and drain, and an n-doped channel.

In this way, when the channel of the transistor is formed, the interface stability can be improved by combining the in-situ growth and epitaxial growth modes, the process mode is easy to realize, the doping uniformity of the channel of the transistor can be improved finally, and the problem of complex doping of the 3DDRAM is solved.

Thus, the source, drain and channel of the transistor in the semiconductor structure are all prepared.

Next, structures such as a gate, a word line, and a capacitor are further formed.

In some embodiments, after forming the channel layer 226, the method may further include:

Forming a fourth oxide layer 227 on the surfaces of the third oxide layer 218 and the channel layer 226 in the initial channel trench 224;

forming a conductive layer 228 within the remaining initial channel trench 224 and on the surface of the third oxide layer 218;

a capacitor structure 231 is formed in the capacitor region.

Fig. 21 is a schematic diagram of the structure obtained after the fourth oxide layer 227 is formed. As shown in fig. 21, a fourth oxide layer 227 is formed on the surface of the initial channel trench 224 at the remaining position excluding the surface of the word line isolation structure 222, specifically, the surface of the first isolation layer 206 and the channel layer 226 exposed by the initial channel trench 224. The fourth oxide layer 227 may be formed by deposition, and the material of the fourth oxide layer may be the same as that of the first/second/third oxide layers described above, for example, silicon oxide, so that in the drawings, these four are shown in the same filling pattern.

The fourth oxide layer 227 may be used as a gate oxide layer of a transistor.

Further, the conductive layer 228 may include a first conductive layer 2281 and a second conductive layer 2282, and in some embodiments, forming the conductive layer 228 within the remaining initial channel trench 224 and on the surface of the third oxide layer 218 includes:

Forming a first conductive layer 2281 on the fourth oxide layer 227, the word line isolation structure 222 and the top surface of the first isolation layer 206;

forming a second conductive layer 2282 on the surface of the first conductive layer 2281;

wherein the first conductive layer 2281 and the second conductive layer 2282 constitute the conductive layer 228.

Fig. 22 is a schematic diagram of the structure obtained after the first conductive layer 2281 is formed. As shown in fig. 22, a first conductive layer 2281 is formed on the surface of the resulting structure of fig. 21. Fig. 23 is a schematic view of the resulting structure after forming the second conductive layer 2282, as shown in fig. 23, the second conductive layer 2282 is formed on the surface of the first conductive layer 2281 and completely fills the initial channel trench 224, and the top surface of the second conductive layer 2282 is flush.

It should be further noted that the first conductive layer 2281 and the second conductive layer 2282 may be formed by deposition, the material of the first conductive layer 2281 and the second conductive layer 2282 may be a conductive material, for example, the first conductive layer 2281 may be titanium nitride (TiN), and the second conductive layer 2282 may be tungsten (W). The conductive layer 228 may serve as a word line for the semiconductor structure, and may also serve as a metal gate for the transistor.

In some embodiments, forming the capacitor structure 231 in the capacitor region may include:

Forming a third isolation layer 229 over the conductive layer 228;

removing the third oxide layer 218 in the capacitor region, exposing the capacitor pillar 210;

forming a first capacitor layer 2311, a dielectric layer 2312 and a second capacitor layer 2313 on the surface of the capacitor pillar 210; wherein the first capacitance layer 2311, the dielectric layer 2312 and the second capacitance layer 2313 form a capacitance structure 231;

a capacitor filling structure 232 is formed in the gap of the second capacitor layer 2313.

Note that, before the third isolation layer 229 is formed, the conductive layer 228 may be polished, so that the conductive layer 228 connected together is separated into a plurality of word lines. Here, the structure shown in fig. 23 is subjected to CMP processing using the top surface plane of the third oxide layer 218 as a polishing stop layer, resulting in the structure shown in fig. 24.

As shown in fig. 24, the first conductive layer 2281 and the second conductive layer 2282 remain between two adjacent word line isolation structures 222 as one word line. It can be seen that the word lines formed in the embodiments of the present disclosure are vertical word line structures, and the cross section of the word lines is inverted "U", one word line being connected to one column of channel layers 226.

Then, a third isolation layer 229 is formed above the top surface of the remaining conductive layer 228, and the third isolation layer 229 is used as a protection layer, so that the third isolation layer 229 and the first isolation layer 206 above the capacitor region, and the third oxide layer 218 in the capacitor region are removed, thereby obtaining the structure shown in fig. 25. As shown in fig. 25, the third isolation layer 229 is formed above the third oxide layer 218, the conductive layer 228, and the word line isolation structure 222. The third isolation layer 229 may be formed by depositing, and the material of the third isolation layer 229 may be the same as that of the first isolation layer 206 and the second isolation layer 216, for example, silicon nitride, so that the three are shown with the same filling in the drawings, and the following drawings do not show the boundaries of the three.

Here, the second isolation layer 216 serves as a protection layer covering the bit line region and the region above the transistor region and exposing the region above the capacitor region, and the third isolation layer 229, the first isolation layer 206 and the third oxide layer 218 of the capacitor region are subjected to etching treatment, thereby forming a capacitor trench 230 in the capacitor region, resulting in the structure shown in fig. 25.

As shown in fig. 25, in the capacitor region, the capacitor trench 230 exposes the capacitor post 210.

A capacitor structure 231 is formed on the surface of the capacitor pillar 210, resulting in the structure shown in fig. 26, wherein the capacitor pillar 210 and the capacitor structure 231 on the surface thereof constitute a capacitor. As shown in fig. 26, the capacitor structure 231 may include: the first capacitor layer 2311 formed on the surface of the capacitor pillar 210, the dielectric layer 2312 formed on the surface of the first capacitor layer 2311, and the second capacitor layer 2313 formed on the surface of the dielectric layer 2312, wherein the first capacitor layer 2311, the dielectric layer 2312, and the second capacitor layer 2313 may be formed by deposition, the materials of the first capacitor layer 2311 and the second capacitor layer 2313 may be conductive materials such as titanium nitride (which may be the same as the first conductive layer 2281, and thus the three are shown in the same filling pattern), and the material of the dielectric layer 2312 may be a High dielectric coefficient (High K) material.

A capacitor fill structure 232 is then formed resulting in the structure shown in fig. 27. Wherein the capacitor filling structure 232 completely fills the gap between the second capacitor layers 2313. The capacitor fill structure 232 may be formed by deposition and the material of the capacitor fill structure 232 may be polysilicon.

It should be noted that, in order to enhance the conductivity of the capacitor and improve the performance of the capacitor, the embodiment may also perform metal silicide treatment on the capacitor column 210, treat the capacitor column 210 as a metal silicide column 233, and then form a capacitor structure 231 on the surface of the metal silicide column 233, where the obtained structure is shown in fig. 28, and the metal silicide column 233 and the capacitor structure 231 on the surface thereof form a capacitor. The capacitor pillar 210 may be silicided by reacting a metal material with a silicon pillar to form a metal silicide. The metal material may be selected from titanium (Ti), cobalt (Co), nickel (Ni), and the like, which have low electrical resistance and good electrical conductivity. Thus, the conductivity of the capacitor can be improved through metal silicidation, which is beneficial to improving the performance of the semiconductor structure.

Further, the bit line region is processed to form a bit line, simply by removing the bit line sacrificial layer 208 of the bit line region to form a bit line trench, and then depositing a conductive material in the bit line trench to obtain a bit line. The process of forming the bit lines is not described in detail herein.

Referring to fig. 29, a schematic diagram of a three-dimensional structure of a semiconductor structure according to an embodiment of the present disclosure is shown (in fig. 29, part of the structure and part of the detailed information are omitted). As shown in fig. 29, in the semiconductor structure, the bit line 234 may be a horizontal bit line structure, the first doped region 2151 wraps around the first source drain region 2091 and is connected to the bit line 234 as a source of the transistor, and the second doped region 2152 wraps around the second source drain region 2092 and is connected to the capacitor as a drain of the transistor. The channel layer 226 covers both sides of the channel region 2093 in the second direction as a channel of the transistor.

As indicated by the dashed arrows in fig. 29, the transistor of the semiconductor structure includes a channel layer formed by in-situ selective epitaxial growth (denoted as epitaxial channel), a first doped region formed by in-situ selective epitaxial growth (denoted as epitaxial source/epi S), and a second doped region formed by in-situ selective epitaxial growth (denoted as epitaxial drain/epi D).

It should be further noted that the deposition methods according to the embodiments of the present disclosure may include deposition methods such as chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), and atomic layer deposition (Selective Atomic Layer Deposition, ALD); the etching method may include dry etching, wet etching, photolithography, and the like, and may be specifically selected in combination with process conditions and material characteristics, which are not particularly limited.

In this way, the source electrode, the drain electrode and the channel of the transistor are formed by two in-situ selective epitaxial growth modes, so that the doping uniformity of the transistor is improved, and the complex doping problem of the 3D DRAM is solved.

Briefly, embodiments of the present disclosure form silicon pillars using silicon crystals in a Si/SiGe multilayer stack and in-situ epitaxial n-type silicon as source/drain and in-situ epitaxial p-type silicon as channel. The preparation flow can be briefly described as follows: (1) providing a wafer start-up procedure, the wafer comprising a substrate 201; (2) sequentially epitaxially growing Si and SiGe to form a multi-layer stack 204; (3) etching the stacked structure to form an active region; (4) forming a source drain mask layer 212 with a source drain pattern; (5) Etching the transfer source drain pattern, exposing the first source drain region 2091 and the second source drain region 2092; (6) Laterally etching the first source drain region 2091 and the second source drain region 2092 to form a recess; (7) In-situ selective epitaxial growth of n-type doped silicon as source and drain of transistor of 3D DRAM; (8) depositing silicon nitride as the second isolation layer 216; (9) removing the SiGe; (10) forming an isolation pattern; (11) transferring the isolation pattern to form isolation trenches 221; (12) depositing silicon nitride to form word line isolation structures 222; (13) laterally etching to form a recess in the channel region 2093; (14) In-situ selective epitaxial growth of p-doped silicon in the recess of channel region 2093 as a channel of the 3D DRAM; (15) Depositing oxide and metal materials to form a fourth oxide layer (gate oxide layer), a metal gate and a word line; (16) Forming a bottom electrode (Bottom Electrodes, BE, i.e., first capacitive layer 2311) of the capacitive structure 231; (17) A dielectric layer 2312 (High-K) and a Top Electrode (TE), i.e., a second capacitance layer 2313, of the capacitance structure 231 are formed, and polysilicon is deposited as a capacitance filling structure 232.

On one hand, the doped Si is selectively grown in situ epitaxially to be used as the S/D or channel of the three-dimensional DRAM transistor, so that the complex doping problem can be solved; on the other hand, selective epitaxial growth is a self-aligned process, and does not require complex process integration; in yet another aspect, in situ formation of doped Si as channel and source/drain doping has excellent uniformity.

In another embodiment of the present disclosure, a semiconductor structure is provided, which is prepared according to the method of the previous embodiments. Taking fig. 27 as an example, the semiconductor structure includes:

a stacked structure including a substrate 201 and at least one stacked layer 204 formed on the substrate 201; wherein the stacked layer 204 includes:

an active pillar 209 extending in a first direction; and along a first direction, the active pillars include a first source drain region 2091, a channel region 2093, and a second source drain region 2092;

a first doped region 2151 formed on the surface of the first source drain region 2091 and a second doped region 2152 formed on the surface of the second source drain region 2092;

a channel layer 226 formed on the surface of the channel region 2093; and channel layers 226 are formed on both side surfaces of the channel region 2093 in the second direction.

It should be noted that, the semiconductor structure provided in this embodiment may be prepared according to the method provided in the foregoing embodiment. In this semiconductor structure, as shown in fig. 27, the sacrificial layer 202 is no longer included in the stack layer 204 at this time due to the number of process steps.

In some embodiments, as shown in fig. 27, the stacked structure includes a bit line region, a transistor region, and a capacitor region along a first direction, and the active pillar 209 is located in the transistor region; the semiconductor structure further includes:

and a capacitor pillar 210 connected to the active pillar 209, and the capacitor pillar 210 is located in the capacitor region.

As shown in fig. 27, the capacitor pillar 210 and the active pillar 209 belong to the same silicon pillar, and in the example shown in fig. 28, the capacitor pillar 210 is also treated as a metal silicide pillar 233.

In some embodiments, as shown in fig. 27, the cross-sectional dimensions of the first source drain region 2091, the channel region 2093, and the second source drain region 2092 are all smaller than the cross-sectional dimensions of the capacitor pillar 210 in the second direction.

Note that, as described in the foregoing embodiment, when forming the source and the drain of the transistor, the first source drain region 2091 and the second source drain region 2092 are subjected to thinning treatment first; in forming the channel of the transistor, the channel region 2093 is thinned first, and the capacitor pillar 210 is not thinned, so that the cross-sectional dimensions of the first source drain region 2091, the channel region 2093, and the second source drain region 2092 are smaller than the cross-sectional dimensions of the capacitor pillar 210. Further, the first doped region 2151 is formed at the thinned position of the first source/drain region 2091 and serves as a source of the transistor, the second doped region 2152 is formed at the thinned position of the second source/drain region 2092 and serves as a drain of the transistor, and the channel layer 226 is formed at the thinned position of the channel region 2093 and serves as a channel of the transistor.

As can be seen in fig. 27, the first doped region 2151 completely surrounds the first source drain region 2091, and the second doped region 2152 completely surrounds the second source drain region 2092.

In some embodiments, as shown in fig. 27, the semiconductor structure further includes a word line isolation structure 222 and a word line structure formed in the transistor region, wherein:

in the second direction, the word line isolation structures 222 and the word line structures are spaced apart, and one word line structure is connected to a set of channel layers 226 arranged in the third direction.

As shown in fig. 27, the first conductive layer 2281 and the second conductive layer 2282 form a word line structure, and as can be seen from the interface in the cc' direction, the word line structure is separated by the word line isolation structure 222, so that the word line isolation structure 222 can avoid leakage between the word line structures, and ensure good insulation. At the same time, it can also be seen that the cross-section of the word line structures is inverted "U" shaped, each of which is connected to a column of channel layers 226 in a third direction.

In some embodiments, as shown in fig. 27, the semiconductor structure further includes a capacitance structure 231 and a capacitance filling structure 232 formed in the capacitance region, wherein:

the capacitor structure 231 includes a first capacitor layer 2311 formed on the surface of the capacitor pillar 210, a dielectric layer 2312 formed on the surface of the first capacitor layer 2311, and a second capacitor layer 2313 formed on the surface of the dielectric layer 2312; the capacitor filling structure 232 is formed in the gap of the second capacitor layer 2313.

As shown in fig. 28, the first capacitor layer 2311 may be formed on the surface of the metal silicide pillar 233 after the silicide process is performed on the capacitor pillar 210.

Further, the semiconductor structure also includes bit lines and the like. Details not disclosed in the present embodiment may be understood by referring to the foregoing description of the embodiments, and are not repeated here.

Thus, the semiconductor structure prepared by the method has particularly good doping uniformity, so that the performance is improved.

Further, referring to fig. 30, an embodiment of the present disclosure further provides a semiconductor memory device, where the semiconductor memory device 30 includes a semiconductor structure manufactured by the method described in the foregoing embodiment.

The semiconductor memory 30 may be a DRAM, particularly a 3D DRAM. The DRAM may conform to not only memory specifications such as Double Rate (DDR), DDR2, DDR3, DDR4, and DDR5, but also memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5, and is not limited in any way.

According to the embodiment of the disclosure, the S/D or channel of the transistor of the 3D DRAM is formed by utilizing in-situ selective epitaxial growth doped silicon, so that the problem of complex doping can be solved, and the performance of the semiconductor memory is further improved.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, comprising:

2. The method of claim 1, wherein, along the first direction, the stacked structure includes a bit line region, a transistor region, and a capacitor region, the method further comprising, after providing the stacked structure:

forming a first oxide layer on the stacked structure;

forming a first isolation layer on the first oxide layer;

3. The method of claim 2, wherein forming a source-drain trench in the stacked structure comprises:

4. The method of claim 3, wherein after exposing the first source drain region and the second source drain region, the method further comprises:

Thinning the first source drain region and the second source drain region;

5. The method of claim 3, wherein after forming the first doped region and the second doped region, the method further comprises:

forming a second isolation layer in the source drain groove;

6. The method of claim 5, wherein forming a word line isolation structure in the third oxide layer comprises:

and forming the word line isolation structure in the isolation trench.

7. The method of claim 5, wherein forming a channel trench in the stacked structure comprises:

thinning the exposed channel region to form the channel groove;

8. A semiconductor structure, comprising:

9. The semiconductor structure of claim 8, wherein the stacked structure includes a bit line region, a transistor region, and a capacitor region along a first direction, the active pillar being located in the transistor region; the semiconductor structure further includes:

the first doped region completely surrounds the first source drain region, and the second doped region completely surrounds the second source drain region.

10. The semiconductor structure of claim 9, further comprising a word line isolation structure and a word line structure formed in the transistor region, wherein: