CN115879555A - Quantum modulus fast multiplication method and device and modulus arithmetic component - Google Patents
Quantum modulus fast multiplication method and device and modulus arithmetic component Download PDFInfo
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Abstract
The invention discloses a quantum modulus fast multiplication operation method, a device and an analog-digital arithmetic assembly, wherein two target data to be operated are obtained and converted into two first target quantum states; performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution; and finally, outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated, so that the modulus fast multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
Description
Technical Field
The invention belongs to the technical field of quantum computation, and particularly relates to a quantum modulus fast multiplication method, a quantum modulus fast multiplication device and a modulus arithmetic component.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store, and process quantum information following quantum mechanics laws. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.
In the implementation process of the secret breaking quantum algorithm, various quantum logic gates are usually needed to construct the quantum algorithm, but when the quantum algorithm is constructed only by the various quantum logic gates, the quantum logic gates corresponding to the module basic arithmetic operation of classical module operation such as module addition, module multiplication, module square and module multiplication inverse are not provided. Therefore, it is urgently needed to provide a technique capable of realizing modulus basic arithmetic operation in quantum wires to fill the blank of the related art.
Disclosure of Invention
The invention aims to provide a quantum modulus fast multiplication operation method, a quantum modulus fast multiplication operation device, an electronic device and a modulus arithmetic assembly, aiming at realizing the modulus fast multiplication operation in a quantum circuit and filling the blank of the related technology.
One embodiment of the present invention provides a quantum modulus fast multiplication method, including:
acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution;
and outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
Optionally, in the aspect of performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus fast multiplication operation result, the method includes:
acquiring a modulus adder module and a modulus multiplier module;
the modulus adder module and the modulus multiplier module are cascaded to generate a target quantum circuit corresponding to a modulus fast multiplier;
and performing modulus fast multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the modulo adder modules is the same as the number n of the qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state; in the aspect of cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier, the method includes:
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulo adder module includes four input terms and four output terms, and the modulo multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier, the method includes:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be calculated, a modulus fast multiplication result input item, and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus quick multiplication result output item and a first auxiliary output item;
the two inputs of the modulus multiplier module comprise a first modulus fast multiplication result output and a first auxiliary output of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item.
Optionally, in the aspect that the modulus fast multiplication operation is performed on each qubit of the two first target quantum states through the target quantum line to generate a second target quantum state, the method includes:
preparing a modulus fast multiplication result input quantum state and an auxiliary input quantum state;
taking the two first target quantum states as the input of the two quantum state input items to be calculated, taking the modulus fast multiplication result input quantum state as the input of the modulus fast multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
and operating the target quantum circuit after the initial state is prepared, and measuring the quantum bit corresponding to the input quantum state of the modulus fast multiplication result to obtain a second target quantum state.
Another embodiment of the present invention provides a quantum-modulus fast multiplication apparatus, including:
the device comprises an acquisition unit, a calculation unit and a processing unit, wherein the acquisition unit is used for acquiring two target data to be calculated and converting the two target data to be calculated into two first target quantum states;
the evolution unit is used for carrying out quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain an evolved second target quantum state for storing a modulus fast multiplication operation result;
and the output unit is used for outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
Optionally, in the aspect that the quantum state evolution corresponding to the modulus fast multiplication operation is performed on the two first target quantum states to obtain the second target quantum state of the evolved storage modulus fast multiplication operation result, the evolution unit is specifically configured to:
acquiring a modulus adder module and a modulus multiplier module;
the modulus adder module and the modulus multiplier module are cascaded to generate a target quantum circuit corresponding to a modulus fast multiplier;
and performing modulus fast multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the modulo adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state; in the aspect of cascading the modulus adder module and the modulus multiplier module to generate a target quantum line corresponding to the modulus fast multiplier, the evolution unit is specifically configured to:
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulo adder module includes four input terms and four output terms, and the modulo multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n analog-to-digital adder modules and the n-1 analog-to-digital multiplier modules to generate a target quantum line corresponding to the analog-to-digital fast multiplier, the evolution unit is specifically configured to:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be operated, a modulus fast multiplication result input item, and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus fast multiplication result output item and a first auxiliary output item;
the two inputs of the modulus multiplier module comprise a first modulus fast multiplication result output and a first auxiliary output of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item.
Optionally, in the aspect that the fast modulo multiplication is performed on each qubit in the two first target quantum states through the target quantum line to generate a second target quantum state, the evolution unit is specifically configured to:
preparing a modulus fast multiplication result input quantum state and an auxiliary input quantum state;
taking the two first target quantum states as the input of two quantum state input items to be operated, inputting the modulus fast multiplication result into a quantum state as the input of the modulus fast multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
and operating the target quantum circuit after the initial state is prepared, and measuring the quantum bit corresponding to the input quantum state of the modulus fast multiplication result to obtain a second target quantum state.
Yet another embodiment of the invention provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method of any of the above when run.
Yet another embodiment of the invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method described in any of the above.
Yet another embodiment of the present invention provides a quantum modulo arithmetic assembly comprising a quantum modulus fast multiplier determined according to the method described in any one of the above.
Compared with the prior art, the quantum modulus fast multiplication method provided by the invention has the advantages that two target data to be calculated are obtained and converted into two first target quantum states; performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state storing a modulus fast multiplication operation result after the evolution; and finally, outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated, so that the modulus fast multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
Drawings
Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum-modulus fast multiplication method according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a quantum-modulus fast multiplication method according to an embodiment of the present invention;
fig. 3 is a diagram of a target quantum circuit corresponding to the fast modulus multiplier provided in the embodiment of the present invention;
fig. 4 is a quantum circuit diagram corresponding to the modulo adder according to the embodiment of the present invention;
FIG. 5 is a quantum circuit diagram corresponding to a modulus multiplier according to an embodiment of the present invention;
FIG. 6 is a diagram of a quantum circuit corresponding to a comparator according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a quantum-modulus fast multiplication apparatus according to an embodiment of the present invention.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The embodiment of the invention firstly provides a quantum modulus fast multiplication method, which can be applied to electronic equipment, such as a computer terminal, and specifically, a common computer, a quantum computer and the like.
This will be described in detail below by way of example as it would run on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum-modulus fast multiplication method according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more processors 102 (only one is shown in fig. 1) (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing quantum analog-to-digital fast multiplication methods based on quantum wires, and optionally may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum modulus fast multiplication method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, so as to implement the above method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet via wireless.
It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by a quantum language such as a Qrun language, so that the support of the operation of the quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.
In practical applications, due to the development of hardware limited to quantum devices, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program referred in the embodiment of the invention is a program written in a classical language for representing quantum bits and evolution thereof, wherein the quantum bits, quantum logic gates and the like related to quantum computation are all represented by corresponding classical codes.
A quantum circuit, which is a commonly used general quantum computing model, represents a circuit that operates on a quantum bit under an abstract concept, and includes the quantum bit, the circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation.
Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.
The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that the timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H-gates, hadamard-gates), pauli-X gates (X-gates), pauli-Y gates (Y-gates), pauli-Z gates (Z-gates), RX-gates, RY-gates, RZ-gates, and so on; multi-bit quantum logic gates such as CNOT gates, CR gates, isswap gates, toffoli gates, etc. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.
In number theory, a unit of measurement is called a modulus or a module, and for example, a clock counts cycles in 12-ary, i.e., modulo 12. The modular operation is widely applied to both number theory and program design, the identification of odd and even numbers to the identification of prime numbers, the arithmetic from modular exponentiation to greatest common divisor, the problem of grandson to Kaiser codes and the like have no figure which does not fill the modular operation. Modulo fast multiplication refers to an operation of modulo the product of any two data, such as any modulo fast multiplication of 10, 5 × 9mod 10=5. In the field of quantum computing, it is urgently needed to provide a technology capable of realizing fast multiplication operation of modulus in quantum lines, so as to fill up the blank of the related technology.
Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum-modulus fast multiplication method according to an embodiment of the present invention. The method comprises the following steps:
step 201: acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
specifically, in the aspect of acquiring two target data to be operated and converting the two target data to be operated into two first target quantum states, the decimal data to be operated may be converted into binary quantum state representation by using an existing amplitude encoding manner. For example, one target data is 7, signed binary representation 0111; another target data is 4, signed binary representation 011; wherein, the most significant bit is 0 to represent positive number, and 1 to represent negative number. The target quantum state is an eigen state corresponding to two target quantum bits, and the number of all eigen state representations corresponding to the quantum bits is the power of 2 quantum bits. For example: e.g. a group of qubits q 0 、q 1 、q 2 Represents the 0 th, 1 st and 2 nd quantum bits, and is ordered from the high order to the low order as q 2 q 1 q 0 Then, the number of eigenstates (i.e. quantum states) corresponding to the set of qubits is 8 in total, which is: |000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>The superposition state between the 8 eigenstates. The number of the quantum bit set can be set according to the actual operation requirement.
Step 202: performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution;
the present embodiment is used to describe how to implement a logic circuit for fast multiplication in a quantum computer, and each module is described with reference to pre-developed software QPanda. Any classical logic circuit may also be represented by quantum wires. The classical circuit corresponds to the quantum circuit one by one, the input and the output of the quantum logic gate/quantum circuit are quantum bits, and the quantity of the input quantum bits is equal to that of the output quantum bits. Quantum wires allow quantum states to be input in a superposition, and output states can be output in the same superposition. The reversible computation is the basis of quantum computation, that is, any reversible line has an inverse line, that is, each original output is used as an input, and can be mapped to the original input. A reversible line means that for each output there is exactly one input to which this mapping is a one-to-one mapping. For example, a not gate is a typical reversible logic gate, and its inverse line is itself. A typical non-reciprocal logic gate is an and gate, or gate. For example, the input to the AND gate is 0,0;0,1;1,0 is output, which means that there is no unique mapping from output to input. Reversible computation means that information is not lost during computation, and the original state can be restored after inverse transformation. Irreversible computation means that information is lost. For example, the state of the input cannot be inferred from the output of the and gate. For reversible calculations, it is possible to deduce. Any continuously executing reversible logic gates together are a reversible operation. The quantum logic gates are all reversible logic gates, so the quantum wires are reversible wires. But quantum measurements are not reversible calculations.
Specifically, in the aspect of performing quantum state evolution corresponding to modulo fast multiplication operation on the two first target quantum states to obtain a second target quantum state of an evolved storage modulo fast multiplication operation result, the method includes:
acquiring a modulus adder module and a modulus multiplier module;
the modulus adder module and the modulus multiplier module are cascaded to generate a target quantum circuit corresponding to a modulus fast multiplier;
and performing modulus fast multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Further, the number of the modulo adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state; the cascade connection of the modulus adder module and the modulus multiplier module to generate the target quantum circuit corresponding to the modulus fast multiplier comprises:
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Wherein the number of qubits of the first target quantum state is the number of qubits used for encoding the target data. The specific form of the alternating cascade is as follows:
A 0 B 0 A 1 B 1 ······A i B i ······A n-2 B n-2 A n-1
wherein A is i Is the ith modulo addition module, B i Is the ith modulus multiplier module.
Still further, the modulo adder module comprises four input terms and four output terms, and the modulo multiplier module comprises two input terms and two output terms; the alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate the target quantum circuit corresponding to the modulus fast multiplier comprises:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
The four input items of the modulus adder module comprise two quantum state input items to be calculated, a modulus fast multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus quick multiplication result output item and a first auxiliary output item;
the two inputs of the modulus multiplier module comprise a first modulus fast multiplication result output and a first auxiliary output of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item.
Each quantum state input item to be operated comprises n sub-quantum state input items, each sub-quantum state input item corresponds to a quantum state of a quantum bit as input, and the quantum state of the quantum bit is |0> or |1 >. An input item of the modulus adder module is a sub-quantum state input item of a quantum state input item to be calculated, a quantum state input by the sub-quantum state input item is used for controlling whether to execute the modulus addition operation of the modulus adder module, and therefore the sub-quantum state input item can also be called a control bit input item. If the input quantum state of the control bit input item is |0>, the modulus addition operation is not executed; if the input quantum state is |1 >, performing modulo addition operation. The control bit input item of the ith modulus adder module is a sub quantum state input item corresponding to the (n-1) -i) th quantum bit, wherein i is taken from 0.
Further, before obtaining the modulo adder module and the modulo multiplier module, the method further comprises:
acquiring a first common adder module, a constant modulus subtractor module, a constant modulus adder module and a comparator module;
and cascading the first common adder module, the constant modulus subtractor module, the constant modulus adder module and the comparator module to generate a modulus adder module.
Still further, the first generic adder block comprises four input terms and four output terms, the constant modulus subtractor block comprises three input terms and three output terms, the constant modulus adder block comprises three input terms and three output terms, and the comparator block comprises four input terms and four output terms;
the cascade connection of the first common adder module, the constant modulus subtractor module, the constant modulus adder module, and the comparator module to generate a modulus adder module includes:
the method comprises the steps of using three output items of the first common adder module as three input items of the constant modulus adder module, using three output items of the constant modulus adder module and the other output item of the first common adder module as four input items of the comparator module, and cascading the first common adder module, the constant modulus adder module and the comparator module to generate a modulus adder module.
The four output items of the first common adder module comprise two first addition intermediate result output items, a first addition carry output item and a first addition auxiliary output item;
the three input items of the constant modulus subtracter module comprise a first addition intermediate result output item, a first addition carry output item and a first addition auxiliary output item of the first common adder module, and the three output items of the constant modulus subtracter module comprise a second addition intermediate result output item, a second addition carry output item and a second addition auxiliary output item;
the three input items of the constant modulus adder module comprise a second addition intermediate result output item, a second addition carry output item and a second addition auxiliary output item of the constant modulus adder module, and the three output items of the constant modulus adder module comprise a third addition intermediate result output item, a third addition carry output item and a third addition auxiliary output item;
the four input items of the comparator module comprise another first addition intermediate result output item of the first common adder module, a third addition intermediate result output item of the constant modulus adder module, a third addition carry output item and a third addition auxiliary output item, and the four output items of the comparator module comprise a quantum state output item to be added, a modulus addition result output item, an addition carry result output item and an addition auxiliary result output item.
In the embodiment of the present invention, two to-be-added quantum state entries correspond to one to-be-operated quantum state entry and one modulo fast multiplication result entry of the modulo adder module, and one addition carry entry and one addition auxiliary entry both correspond to one auxiliary entry of the modulo adder module, and the one auxiliary entry may include a plurality of sub-auxiliary entries; one quantum state output item to be added corresponds to one quantum state output item to be operated of the modulus adder module, one modulus addition result output item corresponds to one first modulus fast multiplication result output item of the modulus adder module, and one addition carry result output item and one addition auxiliary result output item both correspond to one first auxiliary output item.
Further, before obtaining the modulo adder module and the modulo multiplier module, the method further comprises:
acquiring a constant multiplier module, a constant modulus subtracter module and a constant modulus adder module;
and cascading the constant multiplier module, the constant modulus subtractor module and the constant modulus adder module to generate a modulus multiplier module.
Still further, the constant multiplier module, the constant modulus subtractor module, and the constant modulus adder module each include three input terms and three output terms, and the cascading the constant multiplier module, the constant modulus subtractor module, and the constant modulus adder module generates a modulus multiplier module, including:
and the constant multiplier module, the constant modulus subtractor module and the constant modulus adder module are cascaded to generate the modulus multiplier module.
The constant multiplier module comprises three input items, namely a quantum state input item to be multiplied, a multiplication carry input item and a multiplication auxiliary input item; the three output items of the constant multiplier module comprise a first multiplication intermediate result output item, a first multiplication intermediate carry output item and a first multiplication intermediate auxiliary output item;
the three input items of the constant modulus subtractor module comprise a first multiplied intermediate result output item, a first multiplied intermediate carry output item and a first multiplied intermediate auxiliary output item of the constant multiplier module; the three output items of the constant modulus subtracter module comprise a second multiplication intermediate result output item, a second multiplication intermediate carry output item and a second multiplication intermediate auxiliary output item;
the three input terms of the constant modulus adder module comprise a second multiplied intermediate result output term, a second multiplied intermediate carry output term and a second multiplied intermediate auxiliary output term of the constant modulus subtractor module; the three output terms of the constant modulus adder module include a modulus multiplication result output term, a multiplication carry output term, and a multiplication assist output term.
In the embodiment of the invention, the input item of the quantum state to be multiplied corresponds to the output item of the first modulus quick multiplication result of the modulus adder module, and a multiplication carry input item and a multiplication auxiliary input item both correspond to the first auxiliary output item; the modulus multiplication result output item corresponds to a second modulus quick multiplication result output item, and a multiplication carry output item and a multiplication auxiliary output item correspond to a second auxiliary output item.
The constant multiplier can realize constant multiplication by switching quantum states on two adjacent qubits through a SWAP gate or realize constant multiplication directly in dislocation coding. For example, the target data is 7, binary representation 111, and the input added with the carry term is 0111, and the quantum states on two adjacent qubits are swapped through the SWAP gate to obtain an output 1110, represented as 14 in decimal. And for example a group of qubits q 0 、q 1 、q 2 、q 3 Represents the 0 th, 1 st and 2 nd quantum bits, and is ordered from the high order to the low order as q 3 q 2 q 1 q 0 . Converting binary representation 111 of target data 7 into qubit quantum states 111q 0 Q is prepared by 0 Is made to be 0, the output is 1110, expressed in decimal as 14.
Specifically, in the aspect of performing a modulus fast multiplication operation on each qubit of two first target quantum states through the target quantum circuit to generate a second target quantum state, the method includes:
preparing a modulus fast multiplication result input quantum state and an auxiliary input quantum state;
taking the two first target quantum states as the input of two quantum state input items to be operated, inputting the modulus fast multiplication result into a quantum state as the input of the modulus fast multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
and operating the target quantum circuit after the initial state is prepared, and measuring the quantum bit corresponding to the input quantum state of the modulus fast multiplication result to obtain a second target quantum state.
By way of example only, it is possible to illustrate,as shown in fig. 3, fig. 3 is a quantum circuit diagram corresponding to a modulus fast multiplier according to an embodiment of the present invention. The two first target quantum states are respectively | x>、|y>Where | x > is encoded with n qubits, which in turn can be written as | x > 0 >|x 1 >···|x n-1 >(ii) a The quantum state corresponding to the input item of the modulus fast multiplication result is represented by n quantum bits, the quantum state corresponding to the auxiliary input item is represented by n +3 quantum bits, and the input quantum state and the auxiliary input quantum state of the modulus fast multiplication result are prepared into |0 >. The module of the modulus adder is implemented by the circuit shown in fig. 4, the modulus multiplier is implemented by the circuit shown in fig. 5, fig. 4 is a quantum circuit diagram corresponding to the modulus adder provided in the embodiment of the present invention, and fig. 5 is a quantum circuit diagram corresponding to the modulus multiplier provided in the embodiment of the present invention. Four inputs to the first general adder block: the quantum state corresponding to the two quantum state input items to be added corresponds to the first target quantum state | y > coded by the n quantum bits and the modulus fast multiplication result input quantum state |0>) The quantum states corresponding to an addition carry entry and an addition assist entry are encoded with a qubit code and n +2 qubits, respectively, just for the quantum states corresponding to the assist entry to which the n +3 qubit code is applied.
For the first modulo adder block, by controlling bit | x n-1 If > judging whether to execute, if | x n-1 If > is |1 >, the output is | y mod p >; if x n-1 If > is |0>, the output is | y >; for the first modulus multiplier, if the input is | y mod p >, the output is |2 (y mod p)>If the input is y>Then the output is |2y mod p>The input and output of the subsequent modules can be derived according to the above principle, and are not described in detail herein.
For the last analog-digital adder module, the quantum states of the four output items of the comparator module, the quantum state of one to-be-added quantum state output item, the quantum state of one analog-digital addition result output item, the quantum state of one addition carry result output item and the quantum state of one addition auxiliary result output item are the final result.
Further, fig. 6 is a quantum circuit diagram of a comparator according to an embodiment of the present invention. First target quantum state y in fig. 4>The sum-module fast multiplication result input quantum state |0> is two quantum states to be added, corresponding to the two quantum states | x > and | y > to be compared in FIG. 6, where | x > represents the intermediate state of the operation process of the modulus fast multiplication result input quantum state |0> and is written as | x > 0 ···x n-2 > and | x n-1 Form > of (A). | a>And | b>The corresponding quantum bits are used for auxiliary carry and recording comparison results in the operation process respectively, and the final comparison result can be obtained according to | g>And (4) determining. The modules and their connection relationship in the comparator can be obtained according to fig. 6, and will not be described herein again.
Step 203: and outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
In this embodiment, two first target quantum states obtained by converting two target data to be operated are input to a quantum modulus fast multiplier (i.e., the target quantum circuit), so as to obtain a second target quantum state corresponding to a binary representation modulus fast multiplication result. And then directly outputting a second target quantum state which represents the modulus fast multiplication result and is expressed by binary system to finish the modulus fast multiplication operation of the target data.
Compared with the prior art, the quantum modulus fast multiplication method provided by the invention has the advantages that two target data to be calculated are obtained and converted into two first target quantum states; performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution; and finally, outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated, so that the modulus fast multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
It should be noted that the operation is fast through single or multiple modulusOther operations implemented by the multiplier and other operators are also within the scope of the present application, such as making the two first target quantum states be | x n >And 1 or let the two first target quantum states be | x respectively n-1 ＞、|x>Or other input quantum state, by | x>Implementation | x n The mode of the circuit is not limited, and the circuit can be a modulus operation component mentioned in the application, and can also be a component with other circuit forms.
Another embodiment of the present invention provides a fast multiplication device of quantum numbers, as shown in fig. 7, fig. 7 is a schematic structural diagram of the fast multiplication device of quantum numbers according to the embodiment of the present invention, and the device includes:
an obtaining unit 701, configured to obtain two target data to be operated, and convert the two target data to be operated into two first target quantum states;
an evolution unit 702, configured to perform quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states, to obtain a second target quantum state storing a modulus fast multiplication operation result after the evolution;
and an output unit 703, configured to output the finally obtained second target quantum state as a result of fast modulo multiplication of the two target data to be operated.
Optionally, in the aspect that the quantum state evolution corresponding to the modulus fast multiplication operation is performed on the two first target quantum states to obtain the second target quantum state of the evolved storage modulus fast multiplication operation result, the evolution unit 702 is specifically configured to:
acquiring a modulus adder module and a modulus multiplier module;
the modulus adder module and the modulus multiplier module are cascaded to generate a target quantum circuit corresponding to a modulus fast multiplier;
and performing modulus fast multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the modulo adder modules is the same as the number n of the qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state; in the aspect of cascading the modulus adder module and the modulus multiplier module to generate a target quantum line corresponding to a modulus fast multiplier, the evolution unit 702 is specifically configured to:
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulo adder module includes four input terms and four output terms, and the modulo multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n analog-to-digital adder modules and the n-1 analog-to-digital multiplier modules to generate a target quantum line corresponding to the analog-to-digital fast multiplier, the evolution unit 702 is specifically configured to:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be operated, a modulus fast multiplication result input item, and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus quick multiplication result output item and a first auxiliary output item;
the two inputs of the modulus multiplier module comprise a first modulus fast multiplication result output and a first auxiliary output of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item.
Optionally, in the aspect that the modulus fast multiplication operation is performed on each qubit in the two first target quantum states through the target quantum line to generate a second target quantum state, the evolution unit 702 is specifically configured to:
preparing a modulus fast multiplication result input quantum state and an auxiliary input quantum state;
taking the two first target quantum states as the input of two quantum state input items to be operated, inputting the modulus fast multiplication result into a quantum state as the input of the modulus fast multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
and operating the target quantum circuit after the initial state is prepared, and measuring the quantum bit corresponding to the input quantum state of the modulus fast multiplication result to obtain a second target quantum state.
A further embodiment of the invention provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps in any of the above method embodiments when executed.
Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state storing a modulus fast multiplication operation result after the evolution;
and outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Yet another embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the above method embodiments.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:
acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution;
and outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
Yet another embodiment of the present invention provides a quantum modulo arithmetic assembly comprising a quantum modulus fast multiplier determined according to the method described in any one of the above.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.
Claims (10)
1. A quantum modulus fast multiplication method, comprising:
acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
performing quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain a second target quantum state for storing a modulus fast multiplication operation result after the evolution;
and outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
2. The method of claim 1, wherein the performing quantum state evolution corresponding to the modulo fast multiplication operation on two of the first target quantum states to obtain an evolved second target quantum state storing a result of the modulo fast multiplication operation comprises:
acquiring a modulus adder module and a modulus multiplier module;
the modulus adder module and the modulus multiplier module are cascaded to generate a target quantum circuit corresponding to a modulus fast multiplier;
and performing modulus fast multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
3. The method of claim 2, wherein the number of modulo adder modules is the same as the number n of qubits for the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state; the cascade connection of the modulus adder module and the modulus multiplier module to generate the target quantum circuit corresponding to the modulus fast multiplier comprises:
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
4. The method of claim 3, wherein the modulo adder module includes four input terms and four output terms, the modulo multiplier module includes two input terms and two output terms; the alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate the target quantum circuit corresponding to the modulus fast multiplier comprises:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
5. The method of claim 4, wherein the four inputs of the modulo adder module include two input to quantum states to be computed, one input to the modulo fast multiplication result, and one auxiliary input; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus fast multiplication result output item and a first auxiliary output item;
the two inputs of the modulus multiplier module comprise a first modulus fast multiplication result output and a first auxiliary output of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item.
6. The method of claim 5, wherein said performing a modular fast multiplication operation on each qubit of two of said first target quantum states by said target quantum wires to generate a second target quantum state comprises:
preparing a modulus fast multiplication result input quantum state and an auxiliary input quantum state;
taking the two first target quantum states as the input of two quantum state input items to be operated, inputting the modulus fast multiplication result into a quantum state as the input of the modulus fast multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
and operating the target quantum circuit after the initial state is prepared, and measuring the quantum bit corresponding to the input quantum state of the modulus fast multiplication result to obtain a second target quantum state.
7. A quantum-modulus fast multiplication apparatus, comprising:
the device comprises an acquisition unit, a calculation unit and a processing unit, wherein the acquisition unit is used for acquiring two target data to be calculated and converting the two target data to be calculated into two first target quantum states;
the evolution unit is used for carrying out quantum state evolution corresponding to the modulus fast multiplication operation on the two first target quantum states to obtain an evolved second target quantum state for storing a modulus fast multiplication operation result;
and the output unit is used for outputting the finally obtained second target quantum state as a modulus fast multiplication result of the two target data to be operated.
8. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 6 when executed.
9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 6.
10. A quantum modulus arithmetic component comprising a quantum modulus fast multiplier determined according to the method of any one of claims 1 to 6.
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