CN115879554B - Quantum modulus square operation method and device, electronic device and modulus arithmetic component - Google Patents
Quantum modulus square operation method and device, electronic device and modulus arithmetic component Download PDFInfo
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Abstract
The invention discloses a quantum modulus square operation method, a device, an electronic device and a modulus arithmetic component, wherein the method is used for acquiring target data to be operated and converting the target data to be operated into a first target quantum state; performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result; and outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated, so that modulus square operation in a quantum circuit is realized, and the blank of the related technology is filled.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a quantum modulus square operation method, a device, an electronic device and a modulus arithmetic component.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
In the implementation process of the decryption quantum algorithm, the quantum algorithm is generally required to be built by means of various quantum logic gates, but when the quantum algorithm is built by means of various quantum logic gates, there is no quantum logic gate which corresponds to the operation of the modular basic arithmetic operation of classical modular operations such as modular addition, modular multiplication, modular squaring and modular inversion. Therefore, there is an urgent need to provide a technique capable of realizing the operation of the analog-to-digital basic arithmetic operation in the quantum wire, so as to fill the gap of the related art.
Disclosure of Invention
The invention aims to provide a quantum modulus square operation method, a device, an electronic device and a modulus arithmetic component, which aim to realize modulus square operation in a quantum circuit so as to fill the blank of the related technology.
One embodiment of the present invention provides a quantum modulus squaring operation method, which includes:
acquiring target data to be operated, and converting the target data to be operated into a first target quantum state;
Performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result;
And outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
Optionally, in the aspect of performing the quantum state evolution corresponding to the modulus square operation on the first target quantum state to obtain a second target quantum state of the evolving storage modulus square operation result, the method includes:
acquiring a CNOT gate, a modulus adder module and a modulus multiplier module;
cascading the CNOT gate, the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to a modulus squarer;
And performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the CNOT gates is twice the number of the qubits n of the first target quantum state, the number of the modulo adder modules is the same as the number of the qubits n of the first target quantum state, and the number of the modulo multiplier modules is one less than the number of the qubits n of the first target quantum state.
Optionally, in the aspect of cascading the CNOT gate, the modulo adder module and the modulo multiplier module to generate a target quantum circuit corresponding to a modulo squarer, the method includes:
cascading every two CNOT gates with one modulus adder module to generate n first arithmetic unit modules;
And alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to the module squarer.
Optionally, the CNOT gate includes two input items and two output items, the modulo adder module includes four input items and four output items, and the step of cascading each two CNOT gates with one modulo adder module to generate n first operator modules includes:
two output items of one CNOT gate in every two CNOT gates are used as two input items of one modulo adder module, two output items corresponding to the two input items of the modulo adder module are used as two input items of the other CNOT gate in every two CNOT gates, and every two CNOT gates and one modulo adder module are cascaded to generate n first arithmetic unit modules.
Optionally, the two input items of one of the two CNOT gates include a first control input item and a first quantum state input item to be operated; two output items of one CNOT gate in every two CNOT gates comprise a first control output item and a first quantum state output item to be operated;
The four input items of one modulus adder module comprise a first control output item and a first quantum state output item to be operated of one CNOT gate of every two CNOT gates, and a first modulus square input item and a first auxiliary input item; the four output items of the modulus adder module comprise a second control output item and a second quantum state output item to be operated, and a first modulus square output item and a first auxiliary output item;
Two input items of the other CNOT gate in every two CNOT gates comprise a second control output item and a second quantum state output item to be operated of one modulus adder module; two output items of the other CNOT gate in every two CNOT gates comprise a third control output item and a third quantum state output item to be operated.
Optionally, the first operator module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to a module squarer, the method comprises the following steps:
And taking two output items of the current first arithmetic unit module as two input items of the current modulus multiplier module, taking the other two output items of the current first arithmetic unit module and the two output items of the current modulus multiplier module as four input items of the next first arithmetic unit module, and alternately cascading n first arithmetic unit modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus squarer.
Optionally, the four input items of the first arithmetic unit module include a second control input item, a second quantum state input item to be operated, a second module square input item and a second auxiliary input item, and the four output items of the first arithmetic unit module include a fourth control output item, a fourth quantum state output item to be operated, a second module square output item and a second auxiliary output item;
The two input items of the modulus multiplier module comprise one second modulus square output item and one second auxiliary output item, and the two output items of the modulus multiplier module comprise a third modulus square output item and a third auxiliary output item.
Optionally, the performing a modulus multiplication operation on each qubit of the first target quantum state through the target quantum circuit to generate a second target quantum state includes:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the second control input item, taking the first target quantum state as the input of the second quantum state input item to be operated, taking the modulus square input quantum state as the input of the second modulus square input item, and taking the auxiliary input quantum state as the input of the second auxiliary input item to obtain the target quantum circuit after initial state preparation;
and operating the target quantum circuit after the preparation of the initial state, and measuring the quantum bit corresponding to the second modulus square input item to obtain a second target quantum state.
Yet another embodiment of the present invention provides a quantum modulus squaring operation device, the device comprising:
the device comprises an acquisition unit, a first quantum state generation unit and a second quantum state generation unit, wherein the acquisition unit is used for acquiring target data to be operated and converting the target data to be operated into a first target quantum state;
The evolution unit is used for carrying out quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of the evolving storage modulus square operation result;
And the output unit is used for outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
Optionally, in the aspect of performing a quantum state evolution corresponding to the modulus square operation on the first target quantum state to obtain a second target quantum state of the evolving storage modulus square operation result, the evolution unit is specifically configured to:
acquiring a CNOT gate, a modulus adder module and a modulus multiplier module;
cascading the CNOT gate, the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to a modulus squarer;
And performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the CNOT gates is twice the number of the qubits n of the first target quantum state, the number of the modulo adder modules is the same as the number of the qubits n of the first target quantum state, and the number of the modulo multiplier modules is one less than the number of the qubits n of the first target quantum state.
Optionally, in the aspect of cascading the CNOT gate, the modulo adder module and the modulo multiplier module to generate a target quantum circuit corresponding to a modulo squarer, the evolution unit is specifically configured to:
cascading every two CNOT gates with one modulus adder module to generate n first arithmetic unit modules;
And alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to the module squarer.
Optionally, the CNOT gate includes two input items and two output items, the modulo adder module includes four input items and four output items, and the step of cascading each two CNOT gates with one modulo adder module to generate n first operator modules, where the evolution unit is specifically configured to:
two output items of one CNOT gate in every two CNOT gates are used as two input items of one modulo adder module, two output items corresponding to the two input items of the modulo adder module are used as two input items of the other CNOT gate in every two CNOT gates, and every two CNOT gates and one modulo adder module are cascaded to generate n first arithmetic unit modules.
Optionally, the two input items of one of the two CNOT gates include a first control input item and a first quantum state input item to be operated; two output items of one CNOT gate in every two CNOT gates comprise a first control output item and a first quantum state output item to be operated;
The four input items of one modulus adder module comprise a first control output item and a first quantum state output item to be operated of one CNOT gate of every two CNOT gates, and a first modulus square input item and a first auxiliary input item; the four output items of the modulus adder module comprise a second control output item and a second quantum state output item to be operated, and a first modulus square output item and a first auxiliary output item;
Two input items of the other CNOT gate in every two CNOT gates comprise a second control output item and a second quantum state output item to be operated of one modulus adder module; two output items of the other CNOT gate in every two CNOT gates comprise a third control output item and a third quantum state output item to be operated.
Optionally, the first operator module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to a module squarer, the evolution unit is specifically configured to:
And taking two output items of the current first arithmetic unit module as two input items of the current modulus multiplier module, taking the other two output items of the current first arithmetic unit module and the two output items of the current modulus multiplier module as four input items of the next first arithmetic unit module, and alternately cascading n first arithmetic unit modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus squarer.
Optionally, the four input items of the first arithmetic unit module include a second control input item, a second quantum state input item to be operated, a second module square input item and a second auxiliary input item, and the four output items of the first arithmetic unit module include a fourth control output item, a fourth quantum state output item to be operated, a second module square output item and a second auxiliary output item;
The two input items of the modulus multiplier module comprise one second modulus square output item and one second auxiliary output item, and the two output items of the modulus multiplier module comprise a third modulus square output item and a third auxiliary output item.
Optionally, the performing a modulus multiplication operation on each qubit of the first target quantum state through the target quantum circuit to generate a second target quantum state, where the evolution unit is specifically configured to:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the second control input item, taking the first target quantum state as the input of the second quantum state input item to be operated, taking the modulus square input quantum state as the input of the second modulus square input item, and taking the auxiliary input quantum state as the input of the second auxiliary input item to obtain the target quantum circuit after initial state preparation;
and operating the target quantum circuit after the preparation of the initial state, and measuring the quantum bit corresponding to the second modulus square input item to obtain a second target quantum state.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Yet another embodiment of the invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Compared with the prior art, the quantum modulus square operation method provided by the invention has the advantages that the target data to be operated is obtained, and the target data to be operated is converted into the first target quantum state; performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result; and outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated, so that modulus square operation in a quantum circuit is realized, and the blank of the related technology is filled.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal of a quantum modulus squaring operation method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a quantum modulus squaring operation method according to an embodiment of the present invention;
FIG. 3 is a quantum circuit diagram corresponding to a modulo adder according to an embodiment of the invention;
FIG. 4 is a quantum circuit diagram corresponding to an analog-to-digital multiplier according to an embodiment of the present invention;
FIG. 5 is a diagram of a target quantum circuit corresponding to an analog-to-digital squarer according to an embodiment of the present invention;
Fig. 6 is a schematic structural diagram of a quantum module squaring operation device according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a quantum modulus square operation method which can be applied to electronic equipment such as computer terminals, in particular to common computers, quantum computers and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing quantum wire-based quantum modulus squaring methods, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum modulus squaring method in the embodiment of the present invention, and the processor 102 executes the software programs and modules stored in the memory 104 to perform various functional applications and data processing, i.e., implement the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written in a quantum language such as QRunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs and weigh sub-logic circuits as well, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, and their composition includes qubits, circuits (timelines), and various quantum logic gates, and finally the result often needs to be read out through quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens of hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The general function of a quantum logic gate on a quantum state is to calculate through a unitary matrix multiplied by a matrix corresponding to the right vector of the quantum state.
In the number theory, a unit of measure is referred to as a modulus or a modulus, for example, the clock is counted in 12 cycles, i.e., in 12. The modular operation has wide application in both number theory and program design, and the distinguishing of odd and even numbers to the distinguishing of prime numbers, from modular exponentiation operation to the solving of greatest common divisor, from the grandson problem to the Kaiser password problem, has no figure of influence of the modular operation. The modulus square operation refers to the operation of square modulo any one data, such as any modulus square operation of 10, 5 2 mod 10=5. In the field of quantum computing, there is an urgent need to provide a technology capable of implementing the operation of modular squaring operation in quantum circuits, so as to fill the gap of the related technology.
Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum modulus squaring operation method according to an embodiment of the present invention.
The embodiment provides a quantum modulus square operation method, which comprises the following steps:
step 201: acquiring target data to be operated, and converting the target data to be operated into a first target quantum state;
Specifically, in the aspect of acquiring the target data to be operated and converting the target data to be operated into the first target quantum state, the decimal data to be operated may be converted into binary quantum state representation by using an existing amplitude coding mode. For example, one target data is 7, a signed binary representation 0111; another target data is 4, a signed binary representation 011; wherein, the most significant bit 0 represents a positive number and 1 represents a negative number. The target quantum states are eigenstates corresponding to two target quantum bits, and the number of all eigenstate representations corresponding to the quantum bits is the power of 2 quantum bits. For example: for example, a group of qubits is q 0、q1、q2, which represents the 0 th, 1 st and 2 nd qubits, and the sequence from the high order to the low order is q 2q1q0, the number of eigenstates (i.e., quantum states) corresponding to the group of qubits is 8 in total, and the eigenstates are respectively: |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, the superposition state between the 8 eigenstates. The number of the group of the quantum bits can be set according to actual operation requirements.
Step 202: performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result;
The present embodiment is used to describe how to implement the logic circuit of squaring operation in the quantum computer, and describes each module in conjunction with pre-development software QPanda. Any classical logic circuit may also be represented by a quantum circuit. The classical circuit corresponds to the quantum circuit one by one, the input and the output of the quantum logic gate/the quantum circuit are all quantum bits, and the quantity of the quantum bits of the input and the output is equal. The quantum circuit allows quantum states to be input in a superposition manner, and states of output can be output in a superposition manner in the same manner. Reversible computation is the fundamental of quantum computation, i.e. any reversible line exists as a reverse line, i.e. each original output is taken as an input, just mapped onto the original input. Reversible wiring means that there is exactly one input for each output, and this mapping is a one-to-one mapping. For example, an NOT gate is a typical reversible logic gate, whose inverse is itself. Typical irreversible logic gates are and gates, or gates. For example, the inputs to the AND gates are 0,0;0,1;1,0, which indicates that there is no unique mapping from output to input. Reversible computation means that the information is not lost in the computation process, and the original state can be recovered after the inverse transformation. Irreversible computation means that the information is lost. The state of the input cannot be deduced, for example, from the output of an and gate. For reversible calculations, it can be inferred. Any successively executing reversible logic gates together are one reversible operation. The quantum logic gates are all reversible logic gates, so the quantum wires are reversible wires. But quantum measurements are not reversible calculations.
Specifically, in the aspect of performing the quantum state evolution corresponding to the modulus square operation on the first target quantum state to obtain a second target quantum state of the evolving storage modulus square operation result, the method includes:
acquiring a CNOT gate, a modulus adder module and a modulus multiplier module;
cascading the CNOT gate, the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to a modulus squarer;
And performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state.
The matrix form of the CNOT gates is as follows:
when the control bit of the CNOT gate is |0>, the controlled bit is unchanged; when the control bit of the CNOT gate is |1>, the controlled bit is inverted.
In a specific embodiment of the present invention, the first generic adder module, the constant modulus subtractor module, the constant modulus adder module, and the comparator module are cascaded to generate the modulus adder module. As shown in fig. 3, fig. 3 is a quantum circuit diagram corresponding to a modulo adder according to an embodiment of the present invention.
The first common adder module comprises four input items and four output items, the constant modulus subtractor module comprises three input items and three output items, the constant modulus adder module comprises three input items and three output items, and the comparator module comprises four input items and four output items;
And cascading the first ordinary adder module, the constant modulus subtractor module, the constant modulus adder module and the comparator module to generate a modulus adder module.
The four input items of the first common adder module comprise two quantum state input items to be added, one addition carry input item and one addition auxiliary input item, and the four output items of the first common adder module comprise two first addition intermediate result output items, one first addition carry output item and one first addition auxiliary output item;
The three input items of the constant modulus subtracter module comprise one first addition intermediate result output item, one first addition carry output item and one first addition auxiliary output item of the first common adder module, and the three output items of the constant modulus subtracter module comprise one second addition intermediate result output item, one second addition carry output item and one second addition auxiliary output item;
The three input items of the constant modulus adder module comprise a second addition intermediate result output item, a second addition carry output item and a second addition auxiliary output item of the constant modulus subtractor module, and the three output items of the constant modulus adder module comprise a third addition intermediate result output item, a third addition carry output item and a third addition auxiliary output item;
The four input items of the comparator module comprise another first addition intermediate result output item of the first common adder module, a third addition intermediate result output item of the constant modulus adder module, a third addition carry output item and a third addition auxiliary output item, and the four output items of the comparator module comprise a quantum state output item to be added, a modulus addition result output item, an addition carry result output item and an addition auxiliary result output item.
In fig. 3, quantum states |x > and |y > corresponding to two quantum state input items to be added are represented by n quantum bits, respectively; the quantum state corresponding to one addition carry input item is represented by one quantum bit, and the initial quantum state is prepared as |0>; the quantum state corresponding to one addition auxiliary input item is represented by n+2 quantum bits, and the initial quantum state is prepared as |0>.
In a specific embodiment of the present invention, the constant multiplier module, the constant modulus subtractor module, and the constant modulus adder module are cascaded to produce a modulus multiplier module. As shown in fig. 4, fig. 4 is a quantum circuit diagram corresponding to an analog-to-digital multiplier according to an embodiment of the present invention.
And cascading the constant multiplier module, the constant modulus subtractor module and the constant modulus adder module to generate a modulus multiplier module.
The three input items of the constant multiplier module comprise a quantum state input item to be multiplied, a multiplication carry input item and a multiplication auxiliary input item; the three output terms of the constant multiplier module comprise a first multiplication intermediate result output term, a first multiplication intermediate carry output term and a first multiplication intermediate auxiliary output term;
The three inputs of the constant modulus subtractor module include a first multiplication intermediate result output term, a first multiplication intermediate carry output term, and a first multiplication intermediate auxiliary output term of the constant multiplier module; the three output items of the constant modulus subtracter module comprise a second multiplication intermediate result output item, a second multiplication intermediate carry output item and a second multiplication intermediate auxiliary output item;
The three inputs of the constant modulus adder module include a second multiplication intermediate result output term, a second multiplication intermediate carry output term, and a second multiplication intermediate auxiliary output term of the constant modulus subtractor module; the three output terms of the constant modulus adder module include a modulus multiplication result output term, a multiplication carry output term, and a multiplication auxiliary output term.
In fig. 4, the quantum state |z > corresponding to the quantum state input item to be multiplied is represented by n qubits; the quantum state corresponding to one multiplication carry input item is represented by one quantum bit, and the initial quantum state is prepared as |0>; the quantum state corresponding to one multiplication auxiliary input item is represented by n+2 quantum bits, and the initial quantum state is prepared as |0>.
Wherein the number of CNOT gates is twice the number of quantum bits n of the first target quantum state, the number of modulo adder modules is the same as the number of quantum bits n of the first target quantum state, and the number of modulo multiplier modules is one less than the number of quantum bits n of the first target quantum state. The qubit of the first target quantum state refers to a qubit for encoding the first target quantum state.
Further, in the aspect of cascading the CNOT gate, the modulo adder module and the modulo multiplier module to generate a target quantum circuit corresponding to a modulo squarer, the method includes:
cascading every two CNOT gates with one modulus adder module to generate n first arithmetic unit modules;
And alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to the module squarer.
Each two CNOT gates are cascaded with one modular adder module, namely one CNOT gate is connected with the modular adder module, and then the modular adder is connected with the other CNOT gate to form a structure like ABA.
The specific form of the alternate cascade is as follows:
A0B0A1B1······AiBi······An-2Bn-2An-1
Wherein A i is the ith first operator module, and B i is the ith modulus multiplier module.
Specifically, the CNOT gates include two input terms and two output terms, and the modulo adder module includes four input terms and four output terms, where the cascading each two CNOT gates with one modulo adder module generates n first operator modules, where the n first operator modules include:
two output items of one CNOT gate in every two CNOT gates are used as two input items of one modulo adder module, two output items corresponding to the two input items of the modulo adder module are used as two input items of the other CNOT gate in every two CNOT gates, and every two CNOT gates and one modulo adder module are cascaded to generate n first arithmetic unit modules.
Wherein, two input items of one CNOT gate in every two CNOT gates comprise a first control input item and a first quantum state input item to be operated; two output items of one CNOT gate in every two CNOT gates comprise a first control output item and a first quantum state output item to be operated;
The four input items of one modulus adder module comprise a first control output item and a first quantum state output item to be operated of one CNOT gate of every two CNOT gates, and a first modulus square input item and a first auxiliary input item; the four output items of the modulus adder module comprise a second control output item and a second quantum state output item to be operated, and a first modulus square output item and a first auxiliary output item;
Two input items of the other CNOT gate in every two CNOT gates comprise a second control output item and a second quantum state output item to be operated of one modulus adder module; two output items of the other CNOT gate in every two CNOT gates comprise a third control output item and a third quantum state output item to be operated.
It should be noted that, for the CNOT gates, the control bit of the CNOT gate is a quantum state corresponding to one sub-input item of the first quantum state input item to be operated, for example, for two CNOT gates in the first operator module, the control bit is |x n-1 >; for two CNOT gates in the second first operator block, the control bit is |x n-2 >, the rest of which can determine its control bit and control bit. For the modulo-adder module, the control bit is the quantum state corresponding to the first control input. For example, the initial quantum state corresponding to the first control input is |0>, if |x n-1 > is |0>, no swapping is performed, and the first modulo adder module does not execute; if |x n-1 > is |1>, then the exchange is performed, the quantum state corresponding to the first control input is evolved to |1>, and the first modulo adder module executes with two quantum states to be added being |1> and |0>.
Specifically, the first operator module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to a module squarer, the method comprises the following steps:
And taking two output items of the current first arithmetic unit module as two input items of the current modulus multiplier module, taking the other two output items of the current first arithmetic unit module and the two output items of the current modulus multiplier module as four input items of the next first arithmetic unit module, and alternately cascading n first arithmetic unit modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus squarer.
The four input items of the first arithmetic unit module comprise a second control input item, a second quantum state input item to be operated, a second module square input item and a second auxiliary input item, and the four output items of the first arithmetic unit module comprise a fourth control output item, a fourth quantum state output item to be operated, a second module square output item and a second auxiliary output item;
The two input items of the modulus multiplier module comprise one second modulus square output item and one second auxiliary output item, and the two output items of the modulus multiplier module comprise a third modulus square output item and a third auxiliary output item.
It should be noted that, for the four output items of the last first arithmetic unit module, a fourth control output item, a fourth to-be-operated quantum state output item, a second modulus square output item, and a second auxiliary output item are the final result output items.
Specifically, in terms of performing a modular multiplication operation on each qubit of the first target quantum state through the target quantum circuit to generate a second target quantum state, the method includes:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the second control input item, taking the first target quantum state as the input of the second quantum state input item to be operated, taking the modulus square input quantum state as the input of the second modulus square input item, and taking the auxiliary input quantum state as the input of the second auxiliary input item to obtain the target quantum circuit after initial state preparation;
and operating the target quantum circuit after the preparation of the initial state, and measuring the quantum bit corresponding to the second modulus square input item to obtain a second target quantum state.
It should be noted that, the second control input item corresponds to the first control input item, the second quantum state input item to be operated corresponds to the first quantum state input item to be operated, the second modulus square input item corresponds to the first modulus square input item, and the second auxiliary input item corresponds to the first auxiliary input item. The fourth control output item corresponds to the third control output item, the fourth quantum state output item to be operated corresponds to the third quantum state output item to be operated, the second modulus square output item corresponds to the first modulus square output item, and the second auxiliary output item corresponds to the first auxiliary output item.
Therefore, in the aspect of generating the second target quantum state by performing the modulo multiplication operation on each quantum bit of the first target quantum state through the target quantum circuit, another embodiment is as follows:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the first control input item, taking the first target quantum state as the input of the first quantum state input item to be operated, taking the modulus square input quantum state as the input of the first modulus square input item, and taking the auxiliary input quantum state as the input of the first auxiliary input item to obtain the target quantum circuit after the initial state preparation;
And operating the target quantum circuit after the initial state preparation, and measuring the quantum bit corresponding to the first modulus square input item to obtain a second target quantum state.
For example, as shown in fig. 5, fig. 5 is a quantum circuit diagram corresponding to an analog-to-digital squarer according to an embodiment of the present invention. Fig. 5 includes n first operator modules and n-1 modulo multipliers alternately cascaded, each first operator module including two CNOT gates and one modulo adder module. The control input quantum state is encoded with one quantum bit, the first target quantum state is encoded with n quantum bits, the modulus squared input quantum state is encoded with n quantum bits, and the auxiliary input quantum state is encoded with n+3 quantum bits.
For the four inputs of the first common adder block in fig. 3, the two quantum states |x > and |y > corresponding to the two quantum state inputs to be added, where |y > is |0>. The quantum bits used for coding the quantum state corresponding to the addition carry input item and the quantum state corresponding to the addition auxiliary input item are n+3, and the quantum bits corresponding to the auxiliary input quantum state are n+3.
In the embodiment of the invention, the control input quantum state, the modulus square input quantum state and the auxiliary input quantum state are all prepared as |0>, the final evolution result is that the quantum state of the four output items of the last first arithmetic unit module, the quantum state of the fourth control output item and the quantum state of the second auxiliary output item are also |0>, the quantum state output item to be operated is still |x >, the quantum state output item to be operated can be used for subsequent other operations, and the quantum state of the second modulus square output item is |x 2 mod p >.
Step 203: and outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
In this embodiment, the first target quantum state after the conversion of the target data to be operated is input into a quantum modulus squarer (i.e. the target quantum circuit), so as to obtain the second target quantum state of the corresponding binary representation modulus square result. And then directly outputting a second target quantum state which is expressed by the binary system and represents the modulus square result, and completing the modulus square operation of the target data.
Compared with the prior art, the quantum modulus square operation method provided by the invention has the advantages that the target data to be operated is obtained, and the target data to be operated is converted into the first target quantum state; performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result; and outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated, so that modulus square operation in a quantum circuit is realized, and the blank of the related technology is filled.
Another embodiment of the present invention provides a quantum modulus squaring operation device, as shown in fig. 6, including:
an obtaining unit 601, configured to obtain target data to be operated, and convert the target data to be operated into a first target quantum state;
the evolution unit 602 is configured to perform quantum state evolution corresponding to a modulus square operation on the first target quantum state, and obtain a second target quantum state after evolution, where the second target quantum state stores a modulus square operation result;
and an output unit 603, configured to output the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
Optionally, in the aspect of performing the quantum state evolution corresponding to the modulus square operation on the first target quantum state to obtain the second target quantum state of the evolving storage modulus square operation result, the evolution unit 602 is specifically configured to:
acquiring a CNOT gate, a modulus adder module and a modulus multiplier module;
cascading the CNOT gate, the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to a modulus squarer;
And performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state.
Optionally, the number of the CNOT gates is twice the number of the qubits n of the first target quantum state, the number of the modulo adder modules is the same as the number of the qubits n of the first target quantum state, and the number of the modulo multiplier modules is one less than the number of the qubits n of the first target quantum state.
Optionally, in the aspect of cascading the CNOT gate, the modulo adder module, and the modulo multiplier module to generate a target quantum circuit corresponding to a modulo squarer, the evolution unit 502 is specifically configured to:
cascading every two CNOT gates with one modulus adder module to generate n first arithmetic unit modules;
And alternately cascading the n first operator modules and the n-1 module multiplier modules to generate a target quantum circuit corresponding to the module squarer.
Optionally, the CNOT gate includes two input items and two output items, the modulo adder module includes four input items and four output items, and each two CNOT gates and one modulo adder module are cascaded to generate n first operator modules, where the evolution unit 502 is specifically configured to:
two output items of one CNOT gate in every two CNOT gates are used as two input items of one modulo adder module, two output items corresponding to the two input items of the modulo adder module are used as two input items of the other CNOT gate in every two CNOT gates, and every two CNOT gates and one modulo adder module are cascaded to generate n first arithmetic unit modules.
Optionally, the two input items of one of the two CNOT gates include a first control input item and a first quantum state input item to be operated; two output items of one CNOT gate in every two CNOT gates comprise a first control output item and a first quantum state output item to be operated;
The four input items of one modulus adder module comprise a first control output item and a first quantum state output item to be operated of one CNOT gate of every two CNOT gates, and a first modulus square input item and a first auxiliary input item; the four output items of the modulus adder module comprise a second control output item and a second quantum state output item to be operated, and a first modulus square output item and a first auxiliary output item;
Two input items of the other CNOT gate in every two CNOT gates comprise a second control output item and a second quantum state output item to be operated of one modulus adder module; two output items of the other CNOT gate in every two CNOT gates comprise a third control output item and a third quantum state output item to be operated.
Optionally, the first operator module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n first operator modules with the n-1 analog-to-digital multiplier modules to generate a target quantum circuit corresponding to an analog-to-digital squarer, the evolution unit 602 is specifically configured to:
And taking two output items of the current first arithmetic unit module as two input items of the current modulus multiplier module, taking the other two output items of the current first arithmetic unit module and the two output items of the current modulus multiplier module as four input items of the next first arithmetic unit module, and alternately cascading n first arithmetic unit modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus squarer.
Optionally, the four input items of the first arithmetic unit module include a second control input item, a second quantum state input item to be operated, a second module square input item and a second auxiliary input item, and the four output items of the first arithmetic unit module include a fourth control output item, a fourth quantum state output item to be operated, a second module square output item and a second auxiliary output item;
The two input items of the modulus multiplier module comprise one second modulus square output item and one second auxiliary output item, and the two output items of the modulus multiplier module comprise a third modulus square output item and a third auxiliary output item.
Optionally, the performing a modular multiplication operation on each qubit of the first target quantum state through the target quantum circuit to generate a second target quantum state, and the evolution unit is specifically configured to:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the second control input item, taking the first target quantum state as the input of the second quantum state input item to be operated, taking the modulus square input quantum state as the input of the second modulus square input item, and taking the auxiliary input quantum state as the input of the second auxiliary input item to obtain the target quantum circuit after initial state preparation;
and operating the target quantum circuit after the preparation of the initial state, and measuring the quantum bit corresponding to the second modulus square input item to obtain a second target quantum state.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
acquiring target data to be operated, and converting the target data to be operated into a first target quantum state;
Performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result;
And outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Still another embodiment of the present invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
acquiring target data to be operated, and converting the target data to be operated into a first target quantum state;
Performing quantum state evolution corresponding to modulus square operation on the first target quantum state to obtain a second target quantum state of an evolved storage modulus square operation result;
And outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
Yet another embodiment of the invention provides a quantum modulus arithmetic assembly comprising a quantum modulus squarer determined according to the method described in any of the preceding claims.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (11)
1. A method of quantum modulus squaring operation, the method comprising:
acquiring target data to be operated, and converting the target data to be operated into a first target quantum state;
cascading every two CNOT gates with one modular adder module to generate n first operator modules;
Taking two output items of the current first operator module as two input items of the current modulus multiplier module, taking the other two output items of the current first operator module and the two output items of the current modulus multiplier module as four input items of the next first operator module, so that n first operator modules and n-1 modulus multiplier modules are alternately cascaded, and generating target quantum circuits corresponding to modulus squarers; two output items of the first arithmetic unit module comprise a first modulus square output item and a first auxiliary output item, and the other two output items of the first arithmetic unit module comprise a second control output item and a second quantum state output item to be operated; the two output terms of the modulus multiplier module include a third modulus squared output term and a third auxiliary output term;
Performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state;
And outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
2. The method of claim 1, wherein, before concatenating each two CNOT gates with one modulo adder module to generate n first operator modules, the method further comprises:
And acquiring a CNOT gate, a modulus adder module and a modulus multiplier module.
3. The method of claim 1, wherein the number of CNOT gates is twice the number of qubits n of the first target quantum state, the number of modulo-adder modules is the same as the number of qubits n of the first target quantum state, and the number of modulo-multiplier modules is one less than the number of qubits n of the first target quantum state.
4. The method of claim 1, wherein the CNOT gates comprise two inputs and two outputs, the modulo-adder module comprises four inputs and four outputs, the cascading each two of the CNOT gates with one of the modulo-adder modules generates n first operator modules comprising:
two output items of one CNOT gate in every two CNOT gates are used as two input items of one modulo adder module, two output items corresponding to the two input items of the modulo adder module are used as two input items of the other CNOT gate in every two CNOT gates, and every two CNOT gates and one modulo adder module are cascaded to generate n first arithmetic unit modules.
5. The method of claim 4, wherein the two inputs of one of each two of the CNOT gates comprises a first control input and a first quantum state input to be operated on; two output items of one CNOT gate in every two CNOT gates comprise a first control output item and a first quantum state output item to be operated;
The four input items of one modulus adder module comprise a first control output item and a first quantum state output item to be operated of one CNOT gate of every two CNOT gates, and a first modulus square input item and a first auxiliary input item; the four output items of the modulus adder module comprise a second control output item and a second quantum state output item to be operated, and a first modulus square output item and a first auxiliary output item;
Two input items of the other CNOT gate in every two CNOT gates comprise a second control output item and a second quantum state output item to be operated of one modulus adder module; two output items of the other CNOT gate in every two CNOT gates comprise a third control output item and a third quantum state output item to be operated.
6. The method of claim 5, wherein the four inputs of the first operator module comprise a second control input, a second quantum state input to be operated, a second modulus square input, and a second auxiliary input.
7. The method of claim 6, wherein the performing a modular multiplication operation on each qubit of the first target quantum state via the target quantum circuit to generate a second target quantum state comprises:
preparing a control input quantum state, a modulus square input quantum state and an auxiliary input quantum state;
Taking the control input quantum state as the input of the second control input item, taking the first target quantum state as the input of the second quantum state input item to be operated, taking the modulus square input quantum state as the input of the second modulus square input item, and taking the auxiliary input quantum state as the input of the second auxiliary input item to obtain the target quantum circuit after initial state preparation;
and operating the target quantum circuit after the preparation of the initial state, and measuring the quantum bit corresponding to the second modulus square input item to obtain a second target quantum state.
8. A quantum modulus squaring operation device, the device comprising:
the device comprises an acquisition unit, a first quantum state generation unit and a second quantum state generation unit, wherein the acquisition unit is used for acquiring target data to be operated and converting the target data to be operated into a first target quantum state;
The evolution unit is used for cascading every two CNOT gates with one modular adder module to generate n first operator modules; taking two output items of the current first operator module as two input items of the current modulus multiplier module, taking the other two output items of the current first operator module and the two output items of the current modulus multiplier module as four input items of the next first operator module, so that n first operator modules and n-1 modulus multiplier modules are alternately cascaded, and generating target quantum circuits corresponding to modulus squarers; two output items of the first arithmetic unit module comprise a first modulus square output item and a first auxiliary output item, and the other two output items of the first arithmetic unit module comprise a second control output item and a second quantum state output item to be operated; the two output terms of the modulus multiplier module include a third modulus squared output term and a third auxiliary output term; performing modular square operation on each quantum bit of the first target quantum state through the target quantum circuit to generate a second target quantum state;
And the output unit is used for outputting the finally obtained second target quantum state as a modulus square operation result of the target data to be operated.
9. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when run.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 7.
11. A quantum modulus arithmetic assembly comprising a quantum modulus squarer determined according to the method of any one of claims 1 to 7.
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