CN115877186B - Method and device for testing chip by wafer - Google Patents
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- CN115877186B CN115877186B CN202310052629.XA CN202310052629A CN115877186B CN 115877186 B CN115877186 B CN 115877186B CN 202310052629 A CN202310052629 A CN 202310052629A CN 115877186 B CN115877186 B CN 115877186B
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Abstract
The application discloses a method and a device for testing a chip by a wafer, wherein the method and the device can acquire a first electrical parameter of a storage unit and a second electrical parameter of a connecting circuit; then, determining a first test result of the chip according to the first electrical parameter and the second electrical parameter; then judging whether to adjust the second electrical parameter according to the first test result; then, if the second electrical parameter needs to be adjusted, acquiring the first electrical parameter again after adjusting the second electrical parameter; and then, determining a second test result according to the first electrical parameter acquired again and the second electrical parameter after adjustment. After the first test, the second electrical parameters can be adjusted according to the first test result to acquire the first electrical parameters again, so that the second test result is obtained, whether the chip is qualified or not can be comprehensively judged from the first test result and/or the second test result, and misjudgment is avoided.
Description
Technical Field
The present disclosure relates to the field of chip testing technologies, and in particular, to a method and an apparatus for testing a chip on a wafer.
Background
The cost of the chip is very important for improving the competitiveness of the product, and besides reducing the area of the chip from the chip design point of view, improving the test yield of the chip is also very important for reducing the cost of the chip.
However, in the related art, in the method for testing the chip by the wafer, after the first time of testing the chip, if the electrical parameter of the chip does not meet the test threshold, the chip is directly judged as a defective product, and because the factors influencing the electrical parameter of the chip are more, the method judges whether the chip is a qualified chip, which is easy to misjudge, and results in higher defective rate of the chip.
Disclosure of Invention
The application provides a method and a device for testing a chip on a wafer, a computer readable storage medium and an electronic device, so as to solve the problems.
In a first aspect, the present application provides a method for testing a chip on a wafer, the wafer including a plurality of chips, the chips including connected memory cells and connection circuits, the method comprising:
acquiring a first electrical parameter of the storage unit and a second electrical parameter of the connection circuit;
determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
judging whether to adjust the second electrical parameter according to the first test result;
if the second electrical parameter needs to be adjusted, acquiring the first electrical parameter again after adjusting the second electrical parameter;
and determining a second test result according to the first electrical parameter acquired again and the second electrical parameter after adjustment.
Optionally, the first electrical parameter includes a first sub-electrical parameter and a second sub-electrical parameter;
the obtaining the first electrical parameter of the memory cell and the second electrical parameter of the connection circuit includes:
acquiring the first sub-electrical parameter of the memory cell when erasing data, the second sub-electrical parameter of the memory cell when programming data, and the second electrical parameter of the connection circuit;
wherein the first sub-electrical parameter comprises a first voltage value, the second sub-electrical parameter comprises a second voltage value, and the second electrical parameter comprises a first current value.
Optionally, the determining the first test result of the chip according to the first electrical parameter and the second electrical parameter includes:
judging whether the first voltage value is in a first threshold interval, whether the second voltage value is in a second threshold interval and whether the first current value is in a third threshold interval;
if the first voltage value is in a first threshold interval, the second voltage value is in a second threshold interval, and the first current value is in a third threshold interval, the first test result is that the chip is qualified;
and if one of the three conditions that the first voltage value is in a first threshold interval, the second voltage value is in a second threshold interval and the first current value is in a third threshold interval is not met, the first test result is that the chip is defective.
Optionally, the determining whether to adjust the second electrical parameter according to the first test result includes:
and if the first test result is that the chip is defective, adjusting the first current value, wherein the first current value is in a third threshold interval.
Optionally, if the first test result is that the chip is defective, the first current value is adjusted, and the first current value is in a third threshold interval, including:
if the first test result is that the chip is defective, the first current value is adjusted;
making the difference between the absolute value of the first voltage value and the absolute value of the second voltage value smaller by adjusting the first current value;
wherein the first current value varies within the third threshold interval.
Optionally, the method further comprises:
randomly extracting a preset number of chips from the wafer for testing;
and determining the yield according to the test results of the chips with the preset number.
Optionally, the randomly extracting a preset number of the chips from the wafer for testing includes:
determining a plurality of sampling regions on the wafer;
and randomly extracting the chips in each sampling area for testing, wherein the sum of the number of the chips extracted in each sampling area is equal to the preset number.
In a second aspect, the present application provides an apparatus for testing chips on a wafer, including:
an acquisition unit configured to acquire a first electrical parameter of the storage unit and a second electrical parameter of the connection circuit;
the determining unit is used for determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
the judging unit is used for judging whether to adjust the second electrical parameters according to the first test result;
and the adjusting unit is used for adjusting the second electrical parameter if the second electrical parameter needs to be adjusted.
In a third aspect, the present application provides a computer readable storage medium storing a computer program for executing the method for testing chips on a wafer according to any one of the first aspects.
In a fourth aspect, the present application provides an electronic device comprising a processor and a memory storing execution instructions, the processor performing the method according to any one of the first aspects when executing the execution instructions stored in the memory.
The application provides a method for testing a chip by a wafer, which can acquire a first electrical parameter of a storage unit and a second electrical parameter of a connecting circuit; then, determining a first test result of the chip according to the first electrical parameter and the second electrical parameter; then judging whether to adjust the second electrical parameter according to the first test result; then, if the second electrical parameter needs to be adjusted, acquiring the first electrical parameter again after adjusting the second electrical parameter; and then, determining a second test result according to the first electrical parameter acquired again and the second electrical parameter after adjustment. After the first test, the second electrical parameters can be adjusted according to the first test result to acquire the first electrical parameters again, so that the second test result is obtained, whether the chip is qualified or not can be comprehensively judged from the first test result and/or the second test result, and misjudgment is avoided.
Further effects of the above-described non-conventional alternatives are described below in connection with the embodiments.
Drawings
In order to more clearly illustrate the embodiments or prior art solutions of the present application, the drawings that are required for the description of the embodiments or prior art will be briefly described below, it being apparent that the drawings in the following description are only some of the embodiments described in the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flowchart illustrating a method for testing chips on a wafer according to one embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for testing chips on a wafer according to one embodiment of the present disclosure;
FIG. 3 is a sample area layout of a wafer according to one embodiment of the present application;
FIG. 4 is a schematic structural diagram of an apparatus for testing chips on a wafer according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the related art, in the method for testing the chip by the wafer, after the chip is tested for the first time, if the electrical parameters of the chip do not meet the test threshold, the chip is directly judged as defective products, and as the factors influencing the electrical parameters of the chip are more, the method judges whether the chip is a qualified chip or not, and is easy to misjudge, so that the defective rate of the chip is higher.
In view of the foregoing, the present application provides a method for testing chips on a wafer. Referring to fig. 1, an embodiment of a method for testing chips on a wafer is provided. The method for testing the chips by the wafer is applied to a wafer which is not cut into single chips, wherein the wafer comprises a plurality of chips, namely, the chips are integrated on the wafer and are to be cut into the single chips, the chips comprise connected storage units and connecting circuits, the chips can be flash memory chips, control chips and the like, and the flash memory chips are taken as an example in the embodiment. In this embodiment, the method includes step S01, step S02, step S03, step S04, and step S05.
Step S01, acquiring a first electrical parameter of the storage unit and a second electrical parameter of the connection circuit;
step S02: determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
step S03: judging whether to adjust the second electrical parameter according to the first test result;
step S04: if the second electrical parameter needs to be adjusted, acquiring the first electrical parameter again after adjusting the second electrical parameter;
step S05: and determining a second test result according to the first electrical parameter acquired again and the second electrical parameter after adjustment.
The connection circuit and the storage unit have stronger correlation in the whole operation of the chip, so that the first electrical parameter of the storage unit and the second electrical parameter of the connection circuit have stronger correlation, the second electrical parameter is increased, and the absolute value of the first electrical parameter is increased. As such, during the testing process, the value of the second electrical parameter affects the value of the first electrical parameter. When the chip is tested for the first time, a first test result is obtained, if the first test result is that the chip is unqualified, the second electrical parameter can be adjusted, then the value of the first electrical parameter can be changed along with the change of the second electrical parameter, a second test result is obtained, and whether the chip is qualified or not can be comprehensively judged according to the first test result and the second test result. For example, the first test result may be that the chip is not acceptable, the second test result may be that the chip is acceptable, and the chip may be determined to be acceptable. If the first test result and the second test result are both unqualified, the chip can be judged to be unqualified. The method and the device can comprehensively judge whether the chip is qualified or not according to the first test result and/or the second test result, and avoid misjudgment.
In one embodiment, an analog test circuit is configured in communication with the connection circuit, and current and electrical signals are provided to the connection circuit by the analog test circuit to cause the chip to operate. And adjusting the second electrical parameter by adjusting the current provided by the analog test circuit to the connection circuit.
In some embodiments, the first electrical parameter includes a first sub-electrical parameter and a second sub-electrical parameter. Step S01, the obtaining the first electrical parameter of the memory cell and the second electrical parameter of the connection circuit includes step S011.
Step S011: the first sub-electrical parameter of the memory cell when erasing data, the second sub-electrical parameter of the memory cell when programming data, and the second electrical parameter of the connection circuit are obtained.
Wherein the first sub-electrical parameter comprises a first voltage value V te The second sub-electrical parameter includes a second voltage value V tp The second electrical parameter includes a first current value I ref . A first voltage value V of the memory cell when erasing data te And the second voltage value V of the memory cell when programming data tp Can reflect the state of the memory cell at runtime.
Illustratively, step S02, the determining the first test result of the chip according to the first electrical parameter and the second electrical parameter includes:
step S021: judging the first voltage value V te Whether or not in a first threshold interval, the second voltage value V tp Whether or not the first current value I is within a second threshold interval, and determining ref Whether in the third threshold interval.
Step S022: if the first voltage value V te In a first threshold interval, the second voltage value V tp In a second threshold interval, and the first current value I ref In the third threshold intervalThe first test result is that the chip is a qualified product;
step S023: the first voltage value V te In a first threshold interval, the second voltage value V tp In a second threshold interval, and the first current value I ref And in the three conditions in the third threshold interval, if one of the three conditions is not met, the first test result is that the chip is defective.
The first voltage value V during normal operation of the chip te The second voltage value V tp The first current value I ref And fluctuates within the corresponding threshold interval. If the functional module of the chip has a problem and cannot normally operate, the first voltage value V te The second voltage value V tp Or the first current value I ref Not within the corresponding threshold interval. For example, the first voltage value V te The second voltage value V not being in the first threshold interval tp In a second threshold interval, and the first current value I ref And in the third threshold interval, the chip is judged to be unqualified. The first voltage value V te In a first threshold interval, the second voltage value V tp Is not in the second threshold interval, and the first current value I ref And in the third threshold interval, the chip is judged to be unqualified. The first voltage value V te In a first threshold interval, the second voltage value V tp In a second threshold interval, and the first current value I ref If the chip is not in the third threshold interval, the chip is judged to be unqualified. When the first voltage value V te The second voltage value V tp And the first current value I ref If one value is not in the corresponding threshold value interval, the chip is judged to be unqualified, namely the chip is a defective product.
In some embodiments, step S03, the determining whether to adjust the second electrical parameter according to the first test result includes:
step S031: if the first test result is that the chip is defective, adjusting the first current value I ref And the first electricityFlow value I ref And in a third threshold interval.
Since the memory cell is connected to the connection circuit, in one example, the connection circuit is provided with two data windows connected in series, the two data windows are respectively connected to the memory cell, and the two data windows respectively monitor the first voltage value V te The second voltage value V tp The first current value I ref Is connected in series with two of the data windows. There are two cases of the first test result of the first test performed on the chip. In the first case, the first test result is that the chip is defective. Second case: and the first test result is that the chip is a qualified product. In order to prevent the first case from being misjudged, the chip needs to be tested again, and the first current value I can be adjusted at the moment ref And then, testing the chip again to obtain a second test result. Due to the first current value I ref Is also one of the factors for judging whether the chip is qualified, so the first current value I ref Within the third threshold interval, i.e. so the first current value I ref And changes within a third threshold interval.
In step S031, if the first test result is that the chip is defective, the first current value I is adjusted ref And the first current value I ref In a third threshold interval, comprising:
step S0311: if the first test result is that the chip is defective, adjusting the first current value I ref ；
Step S0312: by adjusting the first current value I ref Causing the first voltage value V to te And the second voltage value V tp The difference in absolute values of (c) becomes smaller. Wherein the first current value I ref And changing within the third threshold interval.
In the whole operation of the flash memory chip, the first current value I of the connection circuit ref The electrical parameters associated with the memory cells are strongly related. For example, if the first current value I of the circuit is connected ref The first voltage value V increases te And a second voltage value V tp The absolute value of (a) becomes smaller, whereas the first voltage value V te And a second voltage value V tp The absolute value of (c) increases. The first current value I of the connection circuit with optimal configuration ref So that the measured first voltage value V te And a second voltage value V tp Is equal in absolute value to a first voltage value V te Negative, the second voltage value V tp Is positive, i.e. both V te +V tp The matching degree between the memory cell and the connection circuit of the flash memory chip is best, i.e., the flash memory chip can work reliably.
In some embodiments, as shown in fig. 2, in order to test the yield of the chips in the wafer, the method further includes step S06 and step S07.
Step S06: randomly extracting a preset number of chips from the wafer for testing;
step S07: and determining the yield according to the test results of the chips with the preset number.
The random sampling can save the test time of chips in the wafer, reflect the yield of the chips in the test wafer, reduce the test time and improve the test efficiency.
Illustratively, in step S06, the randomly extracting a preset number of the chips from the wafer for testing includes:
step S061: determining a plurality of sampling regions on the wafer;
step S062: and randomly extracting the chips in each sampling area for testing, wherein the sum of the number of the chips extracted in each sampling area is equal to the preset number.
In order to randomly sample the extracted chips with representativeness, and to ensure more accurate test results, a sampling area is determined, the chips extracted in the sampling area are tested, and the chip yield of the wafer is determined according to the test results of the chips extracted in each sampling area.
Illustratively, as shown in fig. 3, 9 sampling regions are disposed on the wafer, wherein 3 sampling regions are disposed at left, middle and right positions distributed on the upper half of the wafer, 3 sampling regions are disposed at left, middle and right positions distributed on the middle portion of the wafer, and the remaining 3 sampling regions are disposed at left, middle and right positions distributed on the lower half of the wafer. Each wafer comprises 128 chips, and the yield of the chips in the 9 sampling areas selected in this way can effectively represent the yield distribution level of the whole wafer.
In one embodiment, the first current value I is adjusted ref The chip obtained by random sampling can be tested to obtain a first voltage value V te And a second voltage value V tp Statistical random sampling of the maximum first voltage value V in the chip test te (max) and a minimum second voltage value V tp (max). There is a lot of experimental data to obtain the first current value I of the flash memory chip ref And a first voltage value V te And a second voltage value V tp The relation of the sum DeltaV, I ref =I 0 +k.DELTA.V, where k>And 0 and k are adjustment coefficients, and can be set according to actual conditions. I 0 For an initial first current value I ref The current configuration value of (1) is the first current value I measured in the first test ref . If V is te (max)+V tp (min)=△V>0, then adjust the first current value I ref Causing a first current value I to ref And becomes larger. If V is te (max)+V tp (min)=△V<0, then adjust the first current value I ref Causing a first current value I to ref And becomes smaller. Finally find a more proper first current value I ref Let the first voltage value V te And a second voltage value V tp The sum is close to 0, so that the matching degree of the memory cell of the flash memory chip and the peripheral circuit is the best, and the final test yield is greatly improved.
Referring to fig. 4, an embodiment of an apparatus for testing chips on a wafer is shown. The apparatus of this embodiment is a physical apparatus for performing the method described in fig. 1-2. The technical solution is essentially identical to the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in this embodiment includes:
an acquisition unit configured to acquire a first electrical parameter of the storage unit and a second electrical parameter of the connection circuit;
the determining unit is used for determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
the judging unit is used for judging whether to adjust the second electrical parameters according to the first test result;
and the adjusting unit is used for adjusting the second electrical parameter if the second electrical parameter needs to be adjusted.
Additionally, in an optional manner, the embodiment shown in fig. 4, the first electrical parameter includes a first sub-electrical parameter and a second sub-electrical parameter, and the obtaining unit is configured to:
acquiring the first sub-electrical parameter of the memory cell when erasing data, the second sub-electrical parameter of the memory cell when programming data, and the second electrical parameter of the connection circuit;
wherein the first sub-electrical parameter comprises a first voltage value V te The second sub-electrical parameter includes a second voltage value V tp The second electrical parameter includes a first current value I ref 。
Optionally, the determining unit is configured to:
judging the first voltage value V te Whether or not in a first threshold interval, the second voltage value V tp Whether or not the first current value I is within a second threshold interval, and determining ref Whether it is within a third threshold interval;
if the first voltage value V te In a first threshold interval, the second voltage value V tp In a second threshold interval, and the first current value I ref In a third threshold interval, the first test result is that the chip is a qualified product;
the first voltage value V te In a first threshold interval, the second voltage value V tp In a second threshold interval, and the first current value I ref Three conditions in the third threshold intervalIf one of the conditions is not met, the first test result is that the chip is defective.
Optionally, the judging unit is configured to:
if the first test result is that the chip is defective, adjusting the first current value I ref And the first current value I ref And in a third threshold interval.
Optionally, the adjusting unit is configured to:
if the first test result is that the chip is defective, adjusting the first current value I ref ；
By adjusting the first current value I ref Causing the first voltage value V to te And the second voltage value V tp The difference in absolute values of (c) becomes smaller;
wherein the first current value I ref And changing within the third threshold interval.
The device in this embodiment further includes:
the extraction unit is used for randomly extracting a preset number of chips from the wafer for testing;
and the second determining unit is used for determining the yield according to the test results of the chips with the preset number.
Optionally, the extracting unit is configured to:
determining a plurality of sampling regions on the wafer;
and randomly extracting the chips in each sampling area for testing, wherein the sum of the number of the chips extracted in each sampling area is equal to the preset number.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application. At the hardware level, the electronic device comprises a processor, optionally an internal bus, a network interface, a memory. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, network interface, and memory may be interconnected by an internal bus, which may be an ISA (Industry StandardArchitecture ) bus, a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus, or EISA (Extended IndustryStandard Architecture ) bus, among others. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one bi-directional arrow is shown in FIG. 5, but not only one bus or type of bus.
And the memory is used for storing the execution instruction. In particular, a computer program that executes instructions may be executed. The memory may include memory and non-volatile storage and provide the processor with instructions and data for execution.
In one possible implementation manner, the processor reads the corresponding execution instruction from the nonvolatile memory into the memory and then executes the execution instruction, and may also acquire the corresponding execution instruction from other devices to form the device of the wafer test chip on the logic level. The processor executes the execution instructions stored in the memory to implement the method for testing the chip on the wafer provided in any embodiment of the present application through the execution of the execution instructions.
The method performed by the apparatus for testing chips on wafers according to the embodiment shown in fig. 4 of the present application may be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific IntegratedCircuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a computer readable storage medium well known in the art such as random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, and the like. The computer readable storage medium is located in a memory, and the processor reads information in the memory and, in combination with its hardware, performs the steps of the above method.
The embodiment of the application also provides a readable storage medium, and the computer readable storage medium stores a computer program, where the computer program is used to execute the method for testing the chip by using the wafer, and in particular is used to execute the method shown in fig. 1 or fig. 2.
The electronic device described in the foregoing embodiments may be a computer.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware aspects.
All embodiments in the application are described in a progressive manner, and identical and similar parts of all embodiments are mutually referred, so that each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (6)
1. A method of testing a die on a wafer, the wafer including a plurality of dies, the dies including connected memory cells and connection circuitry, the method comprising:
acquiring a first electrical parameter of the storage unit and a second electrical parameter of the connection circuit;
determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
judging whether to adjust the second electrical parameter according to the first test result;
if the second electrical parameter needs to be adjusted, acquiring the first electrical parameter again after adjusting the second electrical parameter;
determining a second test result according to the first electrical parameter acquired again and the adjusted second electrical parameter;
the first electrical parameter includes a first sub-electrical parameter and a second sub-electrical parameter;
the obtaining the first electrical parameter of the memory cell and the second electrical parameter of the connection circuit includes:
acquiring the first sub-electrical parameter of the memory cell when erasing data, the second sub-electrical parameter of the memory cell when programming data, and the second electrical parameter of the connection circuit;
wherein the first sub-electrical parameter comprises a first voltage value, the second sub-electrical parameter comprises a second voltage value, and the second electrical parameter comprises a first current value;
the determining the first test result of the chip according to the first electrical parameter and the second electrical parameter includes:
judging whether the first voltage value is in a first threshold interval, whether the second voltage value is in a second threshold interval and whether the first current value is in a third threshold interval;
if the first voltage value is in a first threshold interval, the second voltage value is in a second threshold interval, and the first current value is in a third threshold interval, the first test result is that the chip is qualified;
the first test result is that the chip is defective if one of three conditions of the first voltage value in a first threshold interval, the second voltage value in a second threshold interval and the first current value in a third threshold interval is not met;
the step of judging whether to adjust the second electrical parameter according to the first test result includes:
if the first test result is that the chip is defective, the first current value is adjusted, and the first current value is in a third threshold interval;
if the first test result is that the chip is defective, the first current value is adjusted, and the first current value is in a third threshold interval, including:
if the first test result is that the chip is defective, the first current value is adjusted;
making the difference between the absolute value of the first voltage value and the absolute value of the second voltage value smaller by adjusting the first current value;
wherein the first current value varies within the third threshold interval.
2. The method of wafer testing chips of claim 1, further comprising:
randomly extracting a preset number of chips from the wafer for testing;
and determining the yield according to the test results of the chips with the preset number.
3. The method of testing chips on a wafer of claim 2, wherein randomly extracting a predetermined number of said chips from said wafer for testing comprises:
determining a plurality of sampling regions on the wafer;
and randomly extracting the chips in each sampling area for testing, wherein the sum of the number of the chips extracted in each sampling area is equal to the preset number.
4. An apparatus for testing chips on a wafer, comprising:
the acquisition unit is used for acquiring the first electrical parameter of the storage unit and the second electrical parameter of the connecting circuit;
the determining unit is used for determining a first test result of the chip according to the first electrical parameter and the second electrical parameter;
the judging unit is used for judging whether to adjust the second electrical parameters according to the first test result;
the adjusting unit is used for acquiring the first electrical parameter again after adjusting the second electrical parameter when the second electrical parameter needs to be adjusted; determining a second test result according to the first electrical parameter acquired again and the adjusted second electrical parameter;
the first electrical parameter includes a first sub-electrical parameter and a second sub-electrical parameter;
the obtaining the first electrical parameter of the memory cell and the second electrical parameter of the connection circuit includes:
acquiring the first sub-electrical parameter of the memory cell when erasing data, the second sub-electrical parameter of the memory cell when programming data, and the second electrical parameter of the connection circuit;
wherein the first sub-electrical parameter comprises a first voltage value, the second sub-electrical parameter comprises a second voltage value, and the second electrical parameter comprises a first current value;
the determining the first test result of the chip according to the first electrical parameter and the second electrical parameter includes:
judging whether the first voltage value is in a first threshold interval, whether the second voltage value is in a second threshold interval and whether the first current value is in a third threshold interval;
if the first voltage value is in a first threshold interval, the second voltage value is in a second threshold interval, and the first current value is in a third threshold interval, the first test result is that the chip is qualified;
the first test result is that the chip is defective if one of three conditions of the first voltage value in a first threshold interval, the second voltage value in a second threshold interval and the first current value in a third threshold interval is not met;
the step of judging whether to adjust the second electrical parameter according to the first test result includes:
if the first test result is that the chip is defective, the first current value is adjusted, and the first current value is in a third threshold interval;
if the first test result is that the chip is defective, the first current value is adjusted, and the first current value is in a third threshold interval, including:
if the first test result is that the chip is defective, the first current value is adjusted;
making the difference between the absolute value of the first voltage value and the absolute value of the second voltage value smaller by adjusting the first current value;
wherein the first current value varies within the third threshold interval.
5. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program for executing the method of wafer testing chips according to any of the preceding claims 1-3.
6. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for testing a chip on a wafer according to any one of claims 1-3.
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