CN113075527A - Integrated circuit chip testing method, system and medium based on Shmoo test - Google Patents
Integrated circuit chip testing method, system and medium based on Shmoo test Download PDFInfo
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Abstract
The invention provides an integrated circuit chip testing method based on Shmoo testing, which comprises the steps of obtaining tested parameter information of a tested integrated circuit chip and associated data of the tested integrated circuit chip; inputting the measured parameter information and the measured integrated circuit chip associated data into a preset machine learning model, and outputting a predicted working boundary result and a predicted error corresponding to the measured integrated circuit chip by the preset machine learning model; selecting a test value area in a preset set value area corresponding to the measured parameter information according to the predicted working boundary result and the predicted error; and controlling an automatic testing machine to carry out the Shmoo test on the integrated circuit chip to be tested according to the parameter information to be tested and the test value area to obtain an accurate working boundary result. The integrated circuit chip testing method based on the Shmoo test reduces the time required by the test and avoids the influence on the development cycle and the test cost of the product due to longer test time.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a method, a system and a medium for testing an integrated circuit chip based on Shmoo testing.
Background
The production process of the integrated circuit chip comprises a plurality of links such as circuit design, wafer manufacturing, product sealing and testing and the like. After the wafer is manufactured, die (bare chip) on the wafer needs to be evaluated (CP test), and chips with qualified performance are selected for package delivery, so that the package cost is reduced. The packaged chips need final testing (FT testing) before shipment, ensuring that the products ultimately delivered to customers meet the specifications.
The performance of an integrated circuit chip is typically related to a number of operating condition parameters, such as voltage, current, temperature, and the like. When testing the Shmoo, the Shmoo (Shmoo) test is a common integrated circuit test method, and during the Shmoo test, various condition parameters related to a test target are respectively scanned within a certain value range to obtain the states of the test target under different working conditions, so that the performance of a chip is comprehensively evaluated.
At present, the Shmoo test usually involves the value combination of two or more condition parameters, so that the value interval for selecting to scan is very large during the Shmoo test, which results in longer time required by the test and influences on the development cycle of the product and the test cost.
Disclosure of Invention
In order to overcome the defects of the prior art, one of the objectives of the present invention is to provide an integrated circuit chip testing method based on Shmoo testing, which can solve the problems that the Shmoo testing generally involves the value combination of two or more condition parameters, so that the value interval for selecting to scan is very large during Shmoo testing, which results in long testing time, and affects both the development cycle of products and testing cost.
The second purpose of the present invention is to provide an integrated circuit chip testing system based on Shmoo testing, which can solve the problem that the Shmoo testing usually involves the value combination of two or more condition parameters, so that the value interval for selecting to scan is very large during Shmoo testing, which results in long testing time and affects the development cycle and testing cost of the product.
The invention also aims to provide a computer readable storage medium which can solve the problems that the existing Shmoo test usually involves the value combination of two or more condition parameters, so that the value interval for selecting to scan is very large during the Shmoo test, the time required by the test is long, and the development cycle and the test cost of a product are influenced.
One of the purposes of the invention is realized by adopting the following technical scheme:
the integrated circuit chip testing method based on the Shmoo test comprises the following steps:
acquiring data, and acquiring measured parameter information and measured integrated circuit chip associated data of the measured integrated circuit chip;
the method comprises the steps of performing preliminary prediction, namely inputting measured parameter information and measured integrated circuit chip associated data into a preset machine learning model, and outputting a predicted working boundary result and a predicted error corresponding to a measured integrated circuit chip by the preset machine learning model;
selecting a test area, and selecting a test value area in a preset set value area corresponding to the measured parameter information according to the predicted working boundary result and the predicted error, wherein the test value area is smaller than the preset set value area;
and performing the Shmoo test, namely controlling an automatic testing machine to perform the Shmoo test on the integrated circuit chip to be tested according to the parameter information to be tested and the test value area to obtain a Shmoo test result, wherein the Shmoo test result comprises an accurate working boundary result.
Further, the measured parameter information includes two or more measured parameters, when the measured parameter information includes two measured parameters, the working boundary result is a dividing curve between a measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip normally works and a measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip abnormally works, and when the measured parameter information includes two or more measured parameters, the working boundary result is a dividing curve between the measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip normally works and the measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip abnormally works.
Furthermore, before the data acquisition, a preset machine learning model is established, the pre-stored tested data of a plurality of tested integrated circuit chips is used as a data set for establishing the model, and importing the data set of the established model into an initial machine learning model for training, wherein each tested integrated circuit chip corresponding to the tested data comprises tested parameters, the associated data of the tested integrated circuit chip and a predicted working boundary result, the data set for establishing the model comprises a training data set and a verification data set, the training data set is used for training an initial machine learning model to obtain a preset machine learning model, and the verification data set is used for verifying the trained preset machine learning model to obtain a verification result containing an error value, and the error value in the verification result is used as a prediction error corresponding to the predicted working boundary result.
And further, online training is further included, and the measured parameter information of the measured integrated circuit chip, the measured integrated circuit chip associated data and the accurate working boundary result are used as new training data to perform online training and updating on a preset machine learning model.
Further, the related data of the tested integrated circuit chip includes, but is not limited to, processing data of the tested integrated circuit chip, test data of a wafer test structure in the tested integrated circuit chip, and test collection data of the tested integrated circuit chip, and the related data of the tested integrated circuit chip includes, but is not limited to, processing data of the tested integrated circuit chip, test data of the wafer test structure in the tested integrated circuit chip, and test collection data of the tested integrated circuit chip.
Further, the measured parameters include, but are not limited to, one or more of temperature, input voltage, supply voltage, pulse width, clock frequency, data setup time, data hold time.
Further, the Shmoo test result further includes an accurate measured parameter value region corresponding to the integrated circuit chip under test when the integrated circuit chip under test normally operates and an accurate measured parameter value region corresponding to the integrated circuit chip under test when the integrated circuit chip under test abnormally operates, and the accurate working boundary result is located between the accurate measured parameter value region corresponding to the integrated circuit chip under test when the integrated circuit chip under test normally operates and the accurate measured parameter value region corresponding to the integrated circuit chip under test when the integrated circuit chip under test abnormally operates.
The second purpose of the invention is realized by adopting the following technical scheme:
the integrated circuit chip test system based on the Shmoo test comprises an acquisition module, a machine learning module and a test area selection module, wherein the acquisition module is used for acquiring the tested parameter information of the tested integrated circuit chip and the associated data of the tested integrated circuit chip; the machine learning module is used for outputting a predicted working boundary result and a predicted error corresponding to the tested integrated circuit chip according to the tested parameter information and the relevant data of the tested integrated circuit chip, the test value selection module is used for selecting a test value area in a preset set value area corresponding to the tested parameter information according to the predicted working boundary result and the predicted error, the test value area is smaller than the preset set value area, and an automatic testing machine is controlled to carry out a Shmoo test on the tested integrated circuit chip according to the tested parameter information and the test value area.
And the model online training deployment module is used for taking the measured parameter information of the measured integrated circuit chip, the measured integrated circuit chip associated data and an accurate working boundary result as new training data to perform online training and updating on the preset machine learning model.
The third purpose of the invention is realized by adopting the following technical scheme:
a computer-readable storage medium having stored thereon a computer program for executing by a processor the Shmoo test-based integrated circuit chip testing method of the present application.
Compared with the prior art, the invention has the beneficial effects that: in the integrated circuit chip testing method based on the Shmoo test, the tested parameter information and the tested integrated circuit chip associated data are input into a preset machine learning model, the preset machine learning model outputs a predicted working boundary result and a predicted error corresponding to the tested integrated circuit chip, a testing value area is selected from a preset setting value area corresponding to the tested parameter information according to the predicted working boundary result and the predicted error, the testing value area is smaller than the preset setting value area, an automatic testing machine is controlled to carry out the Shmoo test on the tested integrated circuit chip according to the tested parameter information and the testing value area to obtain the Shmoo test result, the Shmoo test result comprises an accurate working boundary result, the scanning value interval of the whole Shmoo test is reduced, and the time required by the test is reduced, the influence on the development period and the test cost of the product due to long test time is avoided.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic flow chart of the integrated circuit chip testing method based on the Shmoo test of the present invention;
FIG. 2 is a schematic diagram of a conventional Shmoo test result obtained after performing Shmoo testing on an integrated circuit chip under test;
FIG. 3 is a schematic diagram of a Shmoo test result in the Shmoo test-based integrated circuit chip testing method of the present invention;
fig. 4 is a schematic diagram of a Shmoo test result obtained when performing a Shmoo test on an integrated circuit chip under test with three parameters under test in the conventional manner.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
As shown in fig. 1 to 4, the Shmoo test-based integrated circuit chip testing method in the present application includes the following steps:
establishing a preset machine learning model, using pre-stored tested data of a plurality of tested integrated circuit chips as a data set for establishing the model, importing the data set for establishing the model into an initial machine learning model for training, wherein each tested integrated circuit chip corresponds to the tested data and comprises tested parameters, tested integrated circuit chip associated data and a predicted working boundary result, the data set for establishing the model comprises a training data set and a verification data set, the training data set is used for training the initial machine learning model to obtain the preset machine learning model, the verification data set is used for verifying the trained preset machine learning model to obtain a verification result containing error values, the error values in the verification result are used as prediction errors corresponding to the predicted working boundary result, and the prediction errors obtained in the machine learning model verification in the embodiment are the predicted working boundary result and the actual working boundary result The resulting error in the area of the value. In this embodiment, the measured parameters include one or more of temperature, input voltage, power voltage, pulse width, clock frequency, data setup time, data retention time, etc., the measured data associated with the integrated circuit chip includes measured integrated circuit chip processing data, test data of a wafer test structure in the measured integrated circuit chip, and test collection data of the measured integrated circuit chip, and the measured integrated circuit chip processing data includes data of the measured integrated circuit chip during processing, such as lot of wafer, position of chip on wafer, thickness of thin film deposition, size of photolithography process, parameter data of equipment, etc.; the test data of the wafer test structure in the tested integrated circuit chip comprises but is not limited to the threshold voltage, the saturation current, the resistance value of a wire and the like of a transistor on the tested integrated circuit chip; the test collection data of the tested integrated circuit chip includes, but is not limited to, static operating current, dynamic operating current, etc. The predicted working boundary result refers to a critical position or a division position between a measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip normally works and a measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip abnormally works, when the measured parameter is two different measured parameters, the working boundary result is one or more curves, and when the measured parameter is more than two different measured parameters, the working boundary result is one or more curves. The initial machine learning model used in the present application is a common machine learning model including, but not limited to, linear regression, logistic regression, K nearest neighbor, naive bayes, decision trees, clustering, support vector machines, gaussian processes, random forests, lifting trees, and various neural networks. And acquiring data, and acquiring the measured parameter information of the integrated circuit chip to be measured and the associated data of the integrated circuit chip to be measured. In this embodiment, measured parameter information input by a user is obtained, where the measured parameter information includes two or more measured parameters, and in this embodiment, the measured parameters include one or more of temperature, input voltage, power supply voltage, pulse width, clock frequency, data setting time, data holding time, and the like.
And (3) performing preliminary prediction, namely inputting the measured parameter information and the measured integrated circuit chip correlation data into a preset machine learning model, and outputting a predicted working boundary result and a predicted error corresponding to the measured integrated circuit chip by the preset machine learning model. In this embodiment, the measured parameter information includes two parameters, specifically, a parameter 1 and a parameter 2, and the working boundary result corresponding to the integrated circuit chip under test is a curve. As shown in fig. 3, 221 in the Shmoo test result is a predicted working boundary result output by the machine learning model, and a point on each square in fig. 3 represents a different parameter value combination.
Selecting a test area, and selecting a test value area in a preset set value area corresponding to the measured parameter information according to the predicted working boundary result and the predicted error, wherein the test value area is smaller than the preset set value area.
And performing the Shmoo test, namely controlling an automatic testing machine to perform the Shmoo test on the integrated circuit chip to be tested according to the parameter information to be tested and the test value area to obtain a Shmoo test result, wherein the Shmoo test result comprises an accurate working boundary result. In this embodiment, the measured parameter information includes two parameters, specifically, a parameter 1 and a parameter 2, and the working boundary result corresponding to the integrated circuit chip under test is a curve. As shown in fig. 3, the Shmoo test result is a Shmoo test result, the abscissa in the graph is a value coordinate of a parameter 1, the ordinate is a value coordinate of a parameter 2, a point on each square in fig. 3 represents a different parameter value combination, the predicted working boundary result 221 is a predicted working boundary curve output by the machine learning model, in this embodiment, the prediction error is actually an error value range of the predicted working boundary result and the actual working boundary result, as shown in fig. 3, a test value area where the actual working boundary result is located can be selected according to the prediction error and the predicted working boundary result, that is, the preset set value area is reduced, the preset set value area is a plurality of squares formed by covering all combinations of two parameters that need to be tested in advance, and the test value area can include two parts, namely, the left area and the right area of the predicted working boundary result are substantially to determine the first boundary line 222 and the second boundary line 223, the area between the first boundary line 222 and the predicted working boundary result 221 is a part of the test value evaluation area, the area between the second boundary line 223 and the predicted working boundary result 221 is another part of the test value evaluation area, at this time, the actual working boundary result 220 is always located in the test value evaluation area, compared with the prior art that the combined values of all parameters 1 and 2 in all preset set value evaluation areas in fig. 2 need to be substituted into the automatic testing machine to control the automatic testing machine to scan the integrated circuit chip to be tested, in this embodiment, through the recognition of the machine learning model, only the combined values of two parameters in the partial areas (i.e. the test value evaluation areas) in the preset set value evaluation areas need to be substituted into the automatic testing machine to scan the integrated circuit chip to be tested, the testing time is greatly shortened, and all set parameter combination data are not required to be substituted for testing. Fig. 2 illustrates Shmoo test results obtained in a test of an integrated circuit chip to be tested by the conventional method, with the same parameters 1 and 2 as described above, where the Shmoo test results include an actual working boundary curve 200, the working boundary curve 200 is located between the first normal working area 100 and the first abnormal working area 300, and in the conventional Shmoo test, a combination of the parameter 1 and the parameter 2 in fig. 2 needs to be used as a preset set value area, and all combination data in the preset set value area is substituted into an automatic test machine to scan the integrated circuit chip to be tested, so that workload of the whole Shmoo test process is very large, and test time is long.
In this embodiment, when the number of the measured parameters is more than two, the working boundary result corresponding to the integrated circuit chip under test is one or more curved surfaces, for example, as shown in fig. 4, a Shmoo test result obtained when a Shmoo test is performed on an integrated circuit chip under test including three measured parameters is shown, where the measured parameters include parameter 1, parameter 2, and parameter 3, and the working boundary curved surface 210 corresponding to the integrated circuit chip under test is located between the second normal working area 110 and the second abnormal working area 310.
In this embodiment, when the automatic testing machine is controlled to scan the integrated circuit chip to be tested, whether the integrated circuit chip to be tested normally works is judged according to different working parameters of the integrated circuit chip to be tested according to different types and characteristics of the integrated circuit chip to be tested, and the integrated circuit chip to be tested may include a digital module, an analog module, a radio frequency module and the like according to the characteristics and functions of the integrated circuit chip to be tested; when the integrated circuit chip to be tested comprises a digital module, the performance to be tested comprises input high voltage, input low voltage, output high voltage, output low voltage, leakage current, static current, dynamic current, data setting time, data holding time, delay time, pulse width, highest working frequency and the like; when the integrated circuit chip to be tested comprises an analog module, the performance to be tested may include signal-to-noise ratio, total harmonic deformation, power supply voltage rejection ratio, common mode voltage rejection ratio, filter Q value, setup time, intermodulation distortion, differential linearity, integral linearity, and the like; when the ic chip under test includes a radio frequency module, the performance to be tested may include signal-to-noise ratio, total harmonic distortion, setup time, amplification factor, noise floor, intermodulation distortion, jitter, phase noise, and the like. The above parameters are used to judge whether the ic chip under test is working properly, for example, the input high voltage parameter of the ic chip with digital module is specified to ensure that the input signal is correctly treated as "1" when the input voltage is higher than the preset threshold (e.g. 0.7V, given by the product specification). If the input signal is judged to be 0 by mistake when the input voltage is 0.71V during the test, the chip is judged to be a defective product; taking the input low voltage as an example, the specification of the input low voltage must ensure that the input signal is properly treated as a "0" when the input voltage is below a certain threshold (e.g., 0.3V, given by the product specification). If the input signal is judged to be '1' by mistake when the input voltage is 0.29V during the test, the chip is judged to be a defective product; taking the output voltage of the chip as an example, the output high voltage must be higher than a certain threshold, the output low voltage must be lower than a certain threshold, parameters such as leakage current, static current, dynamic current and the like must be within a range defined by a product specification, and if the measured value exceeds the range or the threshold, the chip is judged to be unqualified; similarly, the data setup time, data hold time, delay time, pulse width, maximum clock frequency, etc. must be within the limits defined by the product specification, and if the measured values are outside the limits, the chip will be determined to be defective. For example, if the highest clock frequency of the chip during operation is 200MHz specified in the product specification, but the chip cannot normally operate when the clock frequency is 199MHz, the chip will be determined as a defective product.
In this embodiment, the method further includes performing online training, in which the measured parameter information of the measured integrated circuit chip, the measured integrated circuit chip association data, and the accurate working boundary result are used as new training data to perform online training and updating on a preset machine learning model.
The application also provides an integrated circuit chip testing system based on the Shmoo test, which comprises an acquisition module, a machine learning module and a test area selection module, wherein the acquisition module is used for acquiring the tested parameter information of the tested integrated circuit chip and the associated data of the tested integrated circuit chip; the machine learning module is used for outputting a predicted working boundary result and a predicted error corresponding to the tested integrated circuit chip according to the tested parameter information and the relevant data of the tested integrated circuit chip, the test value selection module is used for selecting a test value area in a preset set value area corresponding to the tested parameter information according to the predicted working boundary result and the predicted error, the test value area is smaller than the preset set value area, and an automatic testing machine is controlled to carry out a Shmoo test on the tested integrated circuit chip according to the tested parameter information and the test value area. In this embodiment, the system further includes a model online training deployment module, where the model online training deployment module is configured to perform online training and updating on a preset machine learning model by using the measured parameter information of the measured integrated circuit chip, the measured integrated circuit chip associated data, and the accurate working boundary result as new training data.
The present application also provides a computer-readable storage medium having stored thereon a computer program for execution by a processor of the Shmoo test-based integrated circuit chip testing method of the present application.
In the integrated circuit chip testing method based on the Shmoo test, the tested parameter information and the tested integrated circuit chip associated data are input into a preset machine learning model, the preset machine learning model outputs a predicted working boundary result and a predicted error corresponding to the tested integrated circuit chip, a testing value area is selected from a preset setting value area corresponding to the tested parameter information according to the predicted working boundary result and the predicted error, the testing value area is smaller than the preset setting value area, an automatic testing machine is controlled to carry out the Shmoo test on the tested integrated circuit chip according to the tested parameter information and the testing value area to obtain the Shmoo test result, the Shmoo test result comprises an accurate working boundary result, the scanning value interval of the whole Shmoo test is reduced, and the time required by the test is reduced, the influence on the development period and the test cost of the product due to long test time is avoided.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can readily practice the invention as shown and described in the drawings and detailed description herein; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (10)
1. The integrated circuit chip testing method based on the Shmoo test is characterized by comprising the following steps of: the method comprises the following steps:
acquiring data, and acquiring measured parameter information and measured integrated circuit chip associated data of the measured integrated circuit chip;
the method comprises the steps of performing preliminary prediction, namely inputting measured parameter information and measured integrated circuit chip associated data into a preset machine learning model, and outputting a predicted working boundary result and a predicted error corresponding to a measured integrated circuit chip by the preset machine learning model;
selecting a test area, and selecting a test value area in a preset set value area corresponding to the measured parameter information according to the predicted working boundary result and the predicted error, wherein the test value area is smaller than the preset set value area;
and performing the Shmoo test, namely controlling an automatic testing machine to perform the Shmoo test on the integrated circuit chip to be tested according to the parameter information to be tested and the test value area to obtain a Shmoo test result, wherein the Shmoo test result comprises an accurate working boundary result.
2. The Shmoo test-based integrated circuit chip testing method of claim 1, wherein: the measured parameter information comprises two or more measured parameters, when the measured parameter information comprises two measured parameters, the working boundary result is a segmentation curve between a measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip works normally and a corresponding measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip works abnormally, and when the measured parameter information comprises more than two measured parameters, the working boundary result is a segmentation curve between the measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip works normally and the corresponding measured parameter value area corresponding to the measured integrated circuit chip when the measured integrated circuit chip works abnormally.
3. The Shmoo test-based integrated circuit chip testing method of claim 1, wherein: before the data acquisition, a preset machine learning model is established, the pre-stored tested data of a plurality of tested integrated circuit chips is used as a data set for establishing the model, and importing the data set of the established model into an initial machine learning model for training, wherein each tested integrated circuit chip corresponding to the tested data comprises tested parameters, the associated data of the tested integrated circuit chip and a predicted working boundary result, the data set for establishing the model comprises a training data set and a verification data set, the training data set is used for training an initial machine learning model to obtain a preset machine learning model, and the verification data set is used for verifying the trained preset machine learning model to obtain a verification result containing an error value, and the error value in the verification result is used as a prediction error corresponding to the predicted working boundary result.
4. The Shmoo-test-based integrated circuit chip testing method of claim 3, wherein: and the method also comprises on-line training, wherein the measured parameter information of the measured integrated circuit chip, the measured integrated circuit chip associated data and the accurate working boundary result are used as new training data to carry out on-line training and updating on a preset machine learning model.
5. The Shmoo-test-based integrated circuit chip testing method of claim 4, wherein: the related data of the tested integrated circuit chip comprises but is not limited to processing data of the tested integrated circuit chip, test data of a wafer test structure in the tested integrated circuit chip and test collection data of the tested integrated circuit chip, and the related data of the tested integrated circuit chip comprises but is not limited to processing data of the tested integrated circuit chip, test data of the wafer test structure in the tested integrated circuit chip and test collection data of the tested integrated circuit chip.
6. The Shmoo-test-based integrated circuit chip testing method of claim 5, wherein: the measured parameters include, but are not limited to, one or more of temperature, input voltage, supply voltage, pulse width, clock frequency, data setup time, data hold time.
7. The Shmoo test-based integrated circuit chip testing method of claim 1, wherein: the Shmoo test result further comprises an accurate measured parameter value area corresponding to the integrated circuit chip to be tested when the integrated circuit chip to be tested normally works and an accurate measured parameter value area corresponding to the integrated circuit chip to be tested when the integrated circuit chip to be tested abnormally works, and the accurate working boundary result is located between the accurate measured parameter value area corresponding to the integrated circuit chip to be tested when the integrated circuit chip to be tested normally works and the accurate measured parameter value area corresponding to the integrated circuit chip to be tested when the integrated circuit chip to be tested abnormally works.
8. Integrated circuit chip test system based on Shmoo test, its characterized in that: the device comprises an acquisition module, a machine learning module and a test area selection module, wherein the acquisition module is used for acquiring the tested parameter information of the tested integrated circuit chip and the associated data of the tested integrated circuit chip; the machine learning module is used for outputting a predicted working boundary result and a predicted error corresponding to the tested integrated circuit chip according to the tested parameter information and the relevant data of the tested integrated circuit chip, the test value selection module is used for selecting a test value area in a preset set value area corresponding to the tested parameter information according to the predicted working boundary result and the predicted error, the test value area is smaller than the preset set value area, and an automatic testing machine is controlled to carry out a Shmoo test on the tested integrated circuit chip according to the tested parameter information and the test value area.
9. The Shmoo test-based integrated circuit chip testing system of claim 8, wherein: the online training and deploying system comprises a model online training and deploying module, wherein the model online training and deploying module is used for taking the measured parameter information of the measured integrated circuit chip, the associated data of the measured integrated circuit chip and an accurate working boundary result as new training data to perform online training and updating on a preset machine learning model.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program is executed by a processor to perform the Shmoo test-based integrated circuit chip testing method of any one of claims 1 to 7.
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| CN113672442A (en) * | 2021-08-18 | 2021-11-19 | 长鑫存储技术有限公司 | Signal testing method and device and storage medium |
| CN113687995A (en) * | 2021-10-27 | 2021-11-23 | 成都嘉纳海威科技有限责任公司 | Chip screening method based on neural network |
| CN114236363A (en) * | 2022-01-04 | 2022-03-25 | 深圳凯瑞通电子有限公司 | Stability testing method and system based on integrated circuit chip |
| CN115616374A (en) * | 2022-09-20 | 2023-01-17 | 重庆鹰谷光电股份有限公司 | Machine learning-based semiconductor chip test system |
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