CN115864796A - Self-adaptive SiC-MOSFET parallel current-sharing control circuit and control method - Google Patents

Abstract

The invention discloses a self-adaptive control circuit and a control method for parallel current sharing of SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor), belonging to the technical field of electronic power devices, and used for collecting steady-state working current Ids of each SiC-MOSFET in a SiC-MOSFET parallel circuit in real time; conditioning the collected steady-state working current Ids to a signal in an ADC sampling range; inputting the signal to a high-speed singlechip for judgment and comparison; the high-speed single chip microcomputer controls each grid source voltage VGS of the parallel SiC-MOSFET tubes, meanwhile, the high-speed single chip microcomputer controls the trigger to output a grid driving signal, so that the rising edges of the grid driving signals corresponding to the SiC-MOSFET tubes in the parallel circuit are delayed, the problem of non-uniform current caused by inconsistent grid source threshold voltages of the SiC-MOSFET tubes is solved, and the current equalization of the parallel SiC-MOSFET tubes is realized through static and dynamic control.

Description

Self-adaptive SiC-MOSFET parallel current-sharing control circuit and control method

Technical Field

The invention belongs to the technical field of application of power electronic power devices, and particularly relates to a control circuit and a control method for parallel current sharing of self-adaptive SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor).

Background

With the rapid development of power electronic technology, the voltage class and capacity class of power electronic application fields are more and more required, such as various converters and various motor driving systems, the current capacity of a single discrete SiC-MOSFET tube is limited, and the requirement of equipment with higher power cannot be met, so that the SiC-MOSFET tube is generally subjected to capacity expansion in a parallel connection mode to meet the application requirements of the occasions.

The characteristic parameter difference of the SiC-MOSFET device has a large influence on the parallel current sharing characteristic, and the unbalanced current can cause unbalanced distribution of conduction loss and switching loss of the SiC-MOSFET, so that partial devices can be overheated. In addition, the unbalance of the transient current can also cause the current peak of the device to be overlarge and possibly exceed the safe working area of the device, and the reliability of the circuit is influenced, so that the problem of current sharing of the SiC-MOSFET is solved, and the method has important significance for the parallel connection of the SiC-MOSFET and the MOSFET to enlarge the power level.

Disclosure of Invention

In view of the above, in order to solve the above problems in the prior art, the present invention provides a control circuit and a control method for parallel current sharing of adaptive SiC-MOSFET transistors, so as to achieve the purpose of performing adaptive current sharing control on a parallel circuit.

The technical scheme adopted by the invention is as follows:

a control circuit for parallel current sharing of adaptive SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor) tubes comprises: the SiC-MOSFET parallel circuit, this control circuit still includes:

a high-speed single chip microcomputer;

the grid driving circuits correspond to the SiC-MOSFET tubes in the SiC-MOSFET tube parallel circuit respectively, and the grid driving circuits are in communication connection with the high-speed single chip microcomputer through VGS voltage control circuits respectively;

the current acquisition circuits respectively correspond to each path of SiC-MOSFET in the SiC-MOSFET parallel circuit, and each current acquisition circuit is in communication connection with the high-speed singlechip through a signal conditioning circuit;

and the VGS voltage control circuit is used for regulating the gate-source voltage VGS of the parallel SiC-MOSFET so as to realize the current sharing control of the parallel SiC-MOSFET.

Furthermore, each gate driving circuit is respectively and electrically connected with a VGS delay circuit, and the VGS delay circuits are in communication connection with the high-speed single chip microcomputer so as to further control the gate loading voltage delay time of each SiC-MOSFET, thereby solving the problem of uneven current caused by inconsistent device parameters of the parallel SiC-MOSFET.

Further, the gate driving circuit includes at least: and the driving chip is electrically connected with the grid electrode of the corresponding SiC-MOSFET tube, and the VGS voltage control circuit and the VGS delay circuit corresponding to the SiC-MOSFET tube are respectively and electrically connected with the driving chip. The UCC5350MC driving chip has a Miller clamping function and can prevent a SiC-MOSFET tube from being switched on by mistake, the Miller clamping function is mainly used for sampling the voltage of a grid and comparing the voltage with a threshold voltage, when the voltage of the grid is lower than the threshold voltage, a comparator is reversed, so that the built-in Miller clamping is switched on, a low-on-impedance path is formed, the grid of the SiC-MOSFET tube can be switched off by the low-impedance path, and therefore the mistaken switching-on is avoided.

Further, the VGS delay circuit includes at least: the trigger is in communication connection with the high-speed single chip microcomputer, a PWM signal end of the trigger is in communication connection with the driving chip so as to control the time difference between the output PWM1 signal and the output PWM2 signal, and further control the rising edge delay time of a grid driving signal of a rear-stage SiC-MOSFET tube;

the VGS voltage control circuit at least comprises: the step-down converter is in communication connection with the high-speed single chip microcomputer, the VCC output end of the step-down converter is electrically connected with the driving chip, the voltage output by the step-down converter is adjusted by software through the I2C interface, the operation parameters can be configured, and namely the output VCC of the integrated step-down converter controlled by the I2C interface of the MCU is adopted.

Further, the source electrode of the SiC-MOSFET tube is grounded in series through a current sampling resistor; the current acquisition circuit includes: and two input ends of the differential amplifier are respectively connected to two ends of the current sampling resistor, and the output end of the differential amplifier is electrically connected with the signal conditioning circuit.

Further, the signal conditioning circuit includes: the output end of the differential amplifier is connected in series to the high-speed single chip microcomputer through the in-phase amplifying circuit and the low-pass filter in sequence; the signal conditioning circuit can condition the current detection output signal of each SiC-MOSFET tube again, so that the signal conditioning circuit is suitable for the ADC input range of the MCU.

Furthermore, the single chip microcomputer is connected with an RS-232 interface, the communication between the external PC and the MCU is realized through the communication between the RS-232 interface and the external PC, and various parameters can be acquired and adjusted by using configuration software.

The invention also provides a control method for the parallel current sharing of the self-adaptive SiC-MOSFET, which is based on the control circuit for the parallel current sharing of the self-adaptive SiC-MOSFET and comprises the following steps:

s1: collecting the steady-state working current Ids of each SiC-MOSFET in the SiC-MOSFET parallel circuit in real time;

s2: conditioning the collected steady-state working current Ids to an ADC sampling range through a signal;

s3: inputting the signals in the ADC sampling range into a high-speed single chip microcomputer for judgment and comparison;

s4: and controlling the gate-source voltage VGS of each parallel SiC-MOSFET through a high-speed singlechip to realize the current sharing control of the parallel SiC-MOSFET.

Further, in S1, the high-speed single chip microcomputer is used for switching on and off of the gate drive corresponding to each SiC-MOSFET so as to acquire the steady-state working current Ids of each SiC-MOSFET in turn.

Further, in S4, the method further includes:

the high-speed single chip microcomputer controls the trigger to output a grid driving signal with time difference, and current balance of each path of SiC-MOSFET tube is realized through the rising edge delay of the grid driving signal corresponding to the SiC-MOSFET tube in the SiC-MOSFET tube parallel circuit.

The invention has the beneficial effects that:

by adopting the control circuit and the control method for parallel current sharing of the self-adaptive SiC-MOSFET, the control circuit judges and compares the working current IDS of the parallel SiC-MOSFET to adjust the grid voltage VGS of the parallel SiC-MOSFET, so that the current sharing of each parallel SiC-MOSFET is realized through static control; and on the other hand, the PWM signals of the SiC-MOSFET tubes are controlled to generate time difference so as to solve the problem of non-uniform current caused by inconsistent gate-source threshold voltages UGS (TH) of the SiC-MOSFET tubes, and the current balance of the parallel SiC-MOSFET tubes is realized by dynamic control.

Drawings

FIG. 1 is an overall circuit architecture diagram of a control circuit for parallel current sharing of adaptive SiC-MOSFET transistors;

FIG. 2 is a circuit schematic diagram of a gate drive in a control circuit of parallel current sharing of self-adaptive SiC-MOSFET tubes;

FIG. 3a is a schematic diagram of a first part of a VGS voltage control circuit in a control circuit of parallel current sharing of adaptive SiC-MOSFET;

FIG. 3b is a schematic diagram of a second part of a VGS voltage control circuit in a control circuit for parallel current sharing of adaptive SiC-MOSFET transistors;

FIG. 4 is a graph of VGS versus Rds (on) curves in a control circuit for parallel current sharing of adaptive SiC-MOSFET transistors;

FIG. 5 is a graph of the relationship between the current-sharing parameters in the current-sharing process of the control circuit with parallel current-sharing SiC-MOSFET adaptive transistors;

FIG. 6 is a schematic diagram of a current acquisition circuit in a control circuit for parallel current sharing of self-adaptive SiC-MOSFET tubes;

FIG. 7 is a schematic diagram of a signal conditioning circuit in a control circuit for parallel current sharing of adaptive SiC-MOSFET transistors;

FIG. 8 is a schematic diagram of a VGS delay circuit in a control circuit for parallel current sharing of adaptive SiC-MOSFET transistors;

FIG. 9 is a PWM signal curve diagram in the control circuit of the parallel current sharing of the self-adaptive SiC-MOSFET.

Description of the preferred embodiment

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar modules or modules having the same or similar functionality throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. On the contrary, the embodiments of the application include all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.

Example 1

The embodiment specifically provides a self-adaptive control circuit for parallel connection and current sharing of SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor), which aims to realize current balance of each path of SiC-MOSFET in the SiC-MOSFET parallel circuit, so that the use stability of the SiC-MOSFET is improved, and the device damage of the SiC-MOSFET is reduced.

Therefore, as shown in fig. 1, the control circuit is based on the SiC-MOSFET parallel circuit to realize its corresponding function, and the control circuit mainly includes: the high-speed single chip microcomputer is composed of an MCU-I (U1A), an MCU-II (U1B) and an MCU-III (U1C).

The SiC-MOSFET parallel circuit is provided with two paths of SiC-MOSFET tubes, namely a SiC-MOSFET tube Q8 and a SiC-MOSFET tube Q9, wherein the SiC-MOSFET tube (the model is CEB25M120PR 4) is of a Kelvin structure of TO247-4pin, the Kelvin electrode of the SiC-MOSFET tube is grounded, and the source electrode of the SiC-MOSFET tube is connected with a current sampling resistor and realizes the mutual decoupling of the Kelvin electrode and the source electrode. Each channel of SiC-MOSFET tube is correspondingly connected with a gate driving circuit, as shown in fig. 2, the gate driving circuit includes: the drive chip is a drive integration (such as a UCC5350MC drive chip), and is a single-channel isolated gate driver with Miller clamp and used for driving an IGBT (insulated gate bipolar transistor), a SiC-MOSFET (silicon-metal-oxide-semiconductor field effect transistor) and a drive chip U32 and a drive chip U30 which are respectively corresponding to the SiC-MOSFET Q8 and the SiC-MOSFET Q9; the output end of the driving chip allows the power supply range to be a voltage range: 15 v-33 v. The UCC5350MC driving chip is also provided with an under-voltage protection point UVLO, the minimum driving voltage of the switching tube during normal operation is determined for the under-voltage protection point UVLO of the driving chip, in order to prevent the SiC-MOSFET tube from being turned on mistakenly, the SiC-MOSFET tube is driven by negative voltage generally, but for most driving chips without a single COM pin, the UVLO of the driving chip is generally referred to a VEE/VSS pin of the driving chip.

The CLAMP pin of the driving chip U32 is electrically connected with the grid electrode of the SiC-MOSFET tube Q8, the VCC2 pin (VCC 2 is connected with a positive voltage end and provides positive driving voltage for the SiC-MOSFET through an external power supply) of the driving chip U32 is connected with the VCC-L pin of the buck converter, the IN + pin of the driving chip U32 is connected with the PWM2 port of the VGS delay circuit, and the IN-pin of the driving chip U32 is connected with the DRV2-EN pin of the MCU-II (U2B). Similarly, the CLAMP pin of the driver chip U32 is electrically connected to the gate of the SiC-MOSFET Q9, the VCC2 pin of the driver chip U30 (VCC 2 is connected to the positive voltage terminal to provide positive driving voltage for the SiC-MOSFET by an external power supply) is connected to the VCC-H pin of the buck converter, the IN + pin of the driver chip U30 is connected to the PWM1 port of the VGS delay circuit, and the IN-pin of the driver chip U30 is connected to the DRV1-EN pin of the MCU-ii (U1B).

The soft-off function of the SiC-MOSFET can be realized by combining the MCU-I (U1A) with the grid drive (the drive chip U30 and the drive chip U32), and the soft-off can be adopted to effectively prevent the situation that the voltage of the circuit is increased at the moment of turning off. When a short circuit or overcurrent signal is detected, the PWM output by the MCU-I (U1A) is not in soft shutdown or directly shut down, but the corresponding grid voltage VGS is immediately reduced first, and whether the SIC-MOSFET is in overcurrent or short circuit or not is judged accordingly, if yes, the MCU shuts down the PWM signal by controlling the driving chips U30 and U32 according to the short circuit bearing time of the SIC-MOSFET.

The method comprises the following specific implementation steps:

when a short circuit or overcurrent signal is detected, the MCU-II (U1B) respectively controls the IN + pin and the IN-pin of the driving chip U30 and the driving chip U32, and the steady-state working current Ids of the two-branch SiC-MOSFET tube is detected at different time periods, for example: when the steady-state working current Ids of the SiC-MOSFET tube Q9 or the steady-state working current Ids of the SiC-MOSFET tube Q8 is detected, and when the SiC-MOSFET tube is short-circuited or overcurrent, the MCU-II (U1B) controls an IN + pin and an IN-pin of a drive chip U32 to close the output of the drive chip U32; the MCU-II (U1B) closes the output of the driving chip U30 by controlling an IN + pin and an IN-pin of the driving chip U30.

Compared with the switching transient process, the on-resistance has larger influence on the current sharing of the SiC-MOSFET after the steady state, and the device with smaller on-resistance bears larger current, so that the reliability of the branch device is influenced, the difference of the on-resistance of each tube of the parallel SiC-MOSFET has larger influence on the steady state current sharing, and therefore, the grid voltage VGS of each parallel SiC-MOSFET can be controlled to achieve the current sharing of each parallel SiC-MOSFET branch; as shown in fig. 4 below, which is a relationship between VGS and Rds (on), it can be seen that the higher the gate voltage VGS, the smaller Rds (on).

The resistance value Rds (on) is different due to different currents, as shown in fig. 5 below, in a time period T1-T2, as the gate voltage VGS is gradually increased from the threshold voltage VGS (th) to the miller plateau voltage VGP, the current IDS is gradually increased from 0, the SiC-MOSFET transistor starts to be turned on, the gate voltage VDS starts to be decreased within a time period T3 of the miller plateau, the miller plateau is ended after T3, the SiC-MOSFET transistor enters the variable resistance region, and the gate voltage VGS is continuously increased to the maximum value under the driving of the gate charge, so that the SiC-MOSFET is further completely turned on; in the variable resistance region, the corresponding gate voltage VGS corresponds to a certain drain-source voltage VDS, i.e. the resistance Rds (on) between the drain D and the source S is controlled by the gate voltage VGS; then, for parallel connection of SiC-MOSFETs with different on-resistance values Rds (on), in order to achieve current sharing, i.e. the same current IDS, the gate-source voltage VGS of each parallel SiC-MOSFET can be adjusted.

Therefore, the driving chip is electrically connected with the gate of the SiC-MOSFET tube where the corresponding branch is located, and the VGS voltage control circuit and the VGS delay circuit corresponding to the SiC-MOSFET tube are respectively electrically connected with the driving chip.

The gate-source voltages VGS of the parallel SiC-MOSFET transistors are adjusted by the VGS voltage control circuit to realize the current sharing control of the parallel SiC-MOSFET transistors, as shown in fig. 3a and 3b, the VGS voltage control circuit is designed as follows:

an output VCC circuit of an integrated buck converter (the model is MP 8849) controlled by an I2C interface of MCU-II (U1B) is used for supplying power to a driving chip and respectively supplying power to an integrated buck converter U23 and an integrated buck converter U24 (the model is MP 8849), output voltages VCC _ H and VCC _ L of the integrated buck converter U23 and the integrated buck converter U24 are respectively connected to VCC2 pins of the driving chip U30 and the driving chip U32, and the gate source voltage VGS of two SiC-MOSFETs (Q8 and Q9) connected in parallel can be realized by adjusting the voltages of VCC _ H and VCC _ L. The integrated buck converter (model number MP 8849) supports a wide operating input voltage range of 2.8V to 22V, and can provide an output voltage in the range of 1V to 20.47V, with 10mV as a step size.

In order to realize the regulation of the gate-source voltage VGS, the steady-state working current Ids of the SiC-MOSFET tube Q8 and the SiC-MOSFET tube Q9 needs to be collected firstly, so that each branch SiC-MOSFET tube in the SiC-MOSFET tube parallel circuit is correspondingly connected with a current collecting circuit respectively, and each current collecting circuit is in communication connection with the high-speed single chip microcomputer through a signal conditioning circuit respectively.

The source electrode of the SiC-MOSFET is grounded in series through the current sampling resistor; as shown in fig. 6, the current collection circuit includes: the two differential amplifiers are respectively a differential amplifier U29B and a differential amplifier U31B, two input ends of the differential amplifier U29B are respectively connected to two ends (VIN 1+ and VIN 1-) of the current sampling resistor R148, and an output end VOUT1 of the differential amplifier U29B is electrically connected with the signal conditioning circuit. Two input ends of the differential amplifier U31B are respectively connected to two ends (VIN 2+ and VIN 2-) of the current sampling resistor R147, and an output end VOUT2 of the differential amplifier U31B is electrically connected with the signal conditioning circuit. In the above, the output dc signals amplified by the differential amplifier are the output terminal VOUT1 and the output terminal VOUT2, respectively.

The existing high-performance shunt resistor has a high-power model resistor which can consume a power value as high as 5W and a high-precision shunt resistor (such as an ROHM current detection chip resistor LRT18 series) with an ultralow resistance value of 0.1m omega, and the corresponding shunt resistor can be selected according to the requirements of actual working conditions. The loss is reduced by reducing the resistance of the shunt resistor, but the voltage drop of the shunt resistor is also reduced, and the voltage detection becomes smaller, so in this embodiment, the differential amplifier selects a high-precision operational amplifier, and meanwhile, the operational amplifier with a wider bandwidth is selected. The following is a description of the design of the differential amplifier:

in the circuit design, R139= R146 and R137= R149 are selected, and the following can be obtained by the superposition theorem:

VOUT1=R137/R139 X [（VIN1+）-（VIN1-）]+VREF

adding a voltage offset VREF to the positive end of the operational amplifier, aiming at ensuring that negative direct current voltage exists in the circuit during acquisition, so that the MCU can acquire positive voltage when the output voltage is positive, and therefore, a resistor R149 at the same phase end is connected with a voltage value VREF, namely offset voltage; the diode D25 is added to remove the alternating current part which is connected in series at the front stage, and the R140 and the C104 form a low pass to prevent the output capacitor of the operational amplifier from causing overshoot. The circuit design of the differential amplifier U31B is the same, and will not be described again.

Further, the signal conditioning circuit includes: the output end VOUT1 of the differential amplifier U29B is sequentially connected to the ADC1 pin of the MCU-III (U1C) in series through the in-phase amplifying circuit and the low-pass filter, and the output end VOUT2 of the differential amplifier U31B is sequentially connected to the ADC2 pin of the MCU-III (U1C) in series through the in-phase amplifying circuit and the low-pass filter. In this embodiment, to improve the measurement accuracy, the circuit uses an operational amplifier (such as OPA2356 of TI) with low noise, high accuracy, single power supply, large output swing, rail-to-rail output, and high open-loop gain to detect the input signal. As shown in fig. 7, the operational amplifier U25C, the resistor R123, the resistor R117, and the resistor R118 form an in-phase amplifying circuit, the gain is (resistor R117/resistor R118), the R117 can be adjusted to change the amplification factor, and the gain is adjusted to amplify the voltage of the input VOUT1 so as to meet the sampling requirement of the MCU-iii (U1C) at the subsequent stage. On the other hand, a second-order active low-pass filter is formed by the operational amplifier U25B, the resistor R121 and the resistor C86, so that high-frequency interference signals in front-end sampling signals can be filtered, and the purity of the signals can be well kept; the time constant network of the resistor R121 and the capacitor C86 is designed to give the ADC enough sampling time that otherwise the accuracy of the ADC is degraded, and the capacitor C86 should be as small as possible to avoid voltage residue. The circuit design principle of the other signal conditioning circuit is the same, and the details are not repeated here.

Each gate driving circuit is electrically connected with a VGS delay circuit, namely, the PWM1 signal and the PWM2 signal of the driving chip U30 and the driving chip U32 come from the VGS delay circuits respectively, and the VGS delay circuits are in communication connection with the MCU-I (U1A). The VGS delay circuit is designed as follows: and the PWM signal end of the trigger is in communication connection with the driving chip. Specifically, as shown in fig. 8, a D trigger end of the flip-flop U27 is connected to GPIO1 of the MCU-i (U1A), a pulse signal input end is connected to a clock output end CLK of the MCU-i (U1A), and the flip-flop U27 and the MCU control end form a VGS delay circuit; the circuit design principle of the other path of VGS delay circuit is the same, and the detailed description is omitted here.

The VGS delay circuit is composed of a trigger and an MCU and outputs a grid delay control source signal, wherein the trigger adopts a T1 SN74LVC1G79 trigger, the device is a single-path positive edge trigger D-type trigger, and the power supply voltage can be from 1.65V to 5.5V; the clocks CLK of the two flip-flops are connected to the same clock CLK of the MCU-i (U1A), the two flip-flops are controlled to output PWM1 signals and PWM2 signals through different GPIO1 and GPIO2 interfaces of the MCU-i (U1A), and the waveform of controlling the PWM1 delay through the MCU-i (U1A) is shown in fig. 9.

The high-speed single chip microcomputer is connected with an RS-232 interface, the high-speed single chip microcomputer is communicated with an external PC through the RS-232 interface and can be connected to the PC through the interface, the communication between the PC and the high-speed single chip microcomputer is realized, and various parameters can be collected and adjusted through configuration software.

Example 2

The invention also provides a control method for the parallel current sharing of the self-adaptive SiC-MOSFET, which is based on the control circuit for the parallel current sharing of the self-adaptive SiC-MOSFET in the embodiment 1, and the control method comprises the following steps:

s1: collecting the steady-state working current Ids of each SiC-MOSFET in the SiC-MOSFET parallel circuit in real time; the method specifically comprises the following steps: the current collection circuit 1 and the current collection circuit 2 are respectively connected to collection points at two ends of a resistor R147 and a resistor R148 connected with the source electrodes of the SiC-MOSFET tube Q8 and the SiC-MOSFET tube Q9, and the steady-state working current Ids of the SiC-MOSFET tube Q8 and the SiC-MOSFET tube Q9 is collected in real time;

in practical application, the sampling mode of the ADC is configured to synchronous regular sampling through the high-speed singlechip,

the ADC1 and the ADC2 have the same sampling mode, and the mode can be configured in an ADC _ CR1 register of the high-speed singlechip; thereby detecting the steady-state working current Ids of the two-branch SiC-MOSFET tube in real time,

s2: conditioning the collected steady-state working current Ids to an ADC sampling range through signals, converting the current collected by each branch SiC-MOSFET tube into a voltage output signal, amplifying and filtering the voltage output signal to enable the voltage output signal to be suitable for the ADC input range of the MCU, and performing data processing by the MCU;

s3: inputting signals in an ADC sampling range into a high-speed single chip microcomputer for judgment and comparison so as to compare the magnitude of output current of each branch SiC-MOSFET tube;

s4: from dynamic control of current sharing: and the high-speed single chip microcomputer is used for controlling the gate-source voltage VGS of the parallel SiC-MOSFET so as to realize the current sharing control of the parallel SiC-MOSFET. The control logic is as follows:

because the resistance value Rds (on) between the drain D and the source S is controlled by the gate-source voltage VGS, if it is detected that the output current of a branch SiC-MOSFET is relatively large, according to the relationship between the gate-source voltage VGS and the resistance value Rds (on) (the higher the gate voltage VGS, the smaller the resistance value Rds (on)), the gate-source voltage VGS needs to be reduced to increase the resistance value Rds (on), and then the output current of the branch SiC-MOSFET is reduced to achieve current balance; otherwise, the same process will not be repeated herein.

And adopting dynamic control current sharing: the high-speed single chip microcomputer controls the trigger to output a grid driving signal with time difference, so that the rising edge of the grid driving signal corresponding to the SiC-MOSFET in the SiC-MOSFET parallel circuit is delayed, the current balance of each path of SiC-MOSFET is realized, and the problem of uneven current caused by the fact that the parameters of the parallel SiC-MOSFET are not consistent is solved. The working current of each branch SiC-MOSFET tube in parallel connection is collected, the output current of each SiC-MOSFET tube is compared, and the gate loading voltage delay time of each branch SiC-MOSFET tube is further controlled (by controlling the trigger time of the GPIO1 and the GPIO2, the time difference between the output PWM1 signal and the PWM2 signal can be controlled, so that the rising edge delay time of the gate driving signal of the rear-stage SiC-MOSFET tube is controlled). The control logic is as follows:

usually, the gate-source threshold voltages Ugs (TH) of the SiC-MOSFET tubes are not the same, if in a parallel circuit of two SiC-MOSFET tubes, the gate-source threshold voltage Ugs (TH) of a certain SiC-MOSFET tube is lower, and the gate-source threshold voltage Ugs (TH) of another SiC-MOSFET tube is higher, the delay time of the rising edge of the gate driving signal of the SiC-MOSFET tube with the lower gate-source threshold voltage Ugs (TH) is controlled, so that the tube can be prevented from bearing larger switching current.

It should be noted that any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and that the scope of the preferred embodiments of the present application includes additional implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are exemplary and should not be construed as limiting the present application and that changes, modifications, substitutions and alterations in the above embodiments may be made by those of ordinary skill in the art within the scope of the present application.

Claims (10)

1. A control circuit for parallel current sharing of self-adaptive SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor) tubes comprises: the SiC-MOSFET parallel circuit is characterized in that the control circuit further comprises:

a high-speed single chip microcomputer;

the grid driving circuits correspond to the SiC-MOSFET tubes in the SiC-MOSFET tube parallel circuit respectively, and the grid driving circuits are in communication connection with the high-speed single chip microcomputer through VGS voltage control circuits respectively;

the current acquisition circuits respectively correspond to each path of SiC-MOSFET in the SiC-MOSFET parallel circuit, and each current acquisition circuit is in communication connection with the high-speed singlechip through a signal conditioning circuit;

and the gate-source voltage VGS of each parallel SiC-MOSFET is regulated by the VGS voltage control circuit so as to realize the current sharing control of the parallel SiC-MOSFET.

2. The parallel current sharing control circuit of the self-adaptive SiC-MOSFET tubes according to claim 1, wherein each gate drive circuit is electrically connected with a VGS delay circuit, and each VGS delay circuit is in communication connection with a high-speed single chip microcomputer.

3. The adaptive SiC-MOSFET parallel current sharing control circuit according to claim 2, wherein the gate driving circuit comprises at least: and the driving chip is electrically connected with the grid electrode of the corresponding SiC-MOSFET, and the VGS voltage control circuit and the VGS delay circuit corresponding to the SiC-MOSFET are electrically connected with the driving chip respectively.

4. The adaptive SiC-MOSFET parallel current sharing control circuit of claim 3, wherein the VGS delay circuit comprises at least: the trigger is in communication connection with the high-speed single chip microcomputer, and a PWM signal end of the trigger is in communication connection with the driving chip;

the VGS voltage control circuit at least comprises: and the voltage reducing converter is in communication connection with the high-speed single chip microcomputer, and the VCC output end of the voltage reducing converter is electrically connected with the driving chip.

5. The adaptive SiC-MOSFET parallel current sharing control circuit of claim 4, wherein the source electrodes of the SiC-MOSFET are grounded in series through a current sampling resistor; the current acquisition circuit includes: and two input ends of the differential amplifier are respectively connected to two ends of the current sampling resistor, and the output end of the differential amplifier is electrically connected with the signal conditioning circuit.

6. The adaptive SiC-MOSFET parallel current sharing control circuit of claim 5, wherein the signal conditioning circuit comprises: the output end of the differential amplifier is connected in series to the high-speed single chip microcomputer through the in-phase amplifying circuit and the low-pass filter in sequence.

7. The adaptive SiC-MOSFET parallel current sharing control circuit according to claim 1, wherein the high-speed single chip microcomputer is connected with an RS-232 interface, and communicates with an external PC through the RS-232 interface.

8. A control method for parallel current sharing of self-adaptive SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor) tubes is characterized in that the control method is based on a control circuit for parallel current sharing of the self-adaptive SiC-MOSFET tubes as claimed in any one of claims 1-7, and the control method comprises the following steps:

s1: collecting the steady-state working current Ids of each SiC-MOSFET in the SiC-MOSFET parallel circuit in real time;

s2: conditioning the collected steady-state working current Ids to an ADC sampling range through a signal;

s3: inputting signals in the ADC sampling range into a high-speed single chip microcomputer for judgment and comparison;

s4: and the high-speed single chip microcomputer is used for controlling the gate-source voltage VGS of the parallel SiC-MOSFET so as to realize the current sharing control of the parallel SiC-MOSFET.

9. The parallel current sharing control method for the self-adaptive SiC-MOSFET (silicon carbide-metal oxide semiconductor field effect transistor) tubes according to claim 8, wherein in S1, the high-speed single chip microcomputer is used for switching on and off of the gate drive corresponding to each SiC-MOSFET tube so as to alternately collect the steady-state working current Ids of each SiC-MOSFET tube.

10. The method for controlling parallel current sharing of adaptive SiC-MOSFET transistors according to claim 8, wherein in S4, the method further comprises:

the high-speed single chip microcomputer controls the trigger to output a grid driving signal with time difference, and current balance of each path of SiC-MOSFET tube is realized through the rising edge delay of the grid driving signal corresponding to the SiC-MOSFET tube in the SiC-MOSFET tube parallel circuit.

Images