CN115863183B - Manufacturing method of micro-flow channel with measurable flow for heat dissipation of three-dimensional integrated wafer system - Google Patents
Manufacturing method of micro-flow channel with measurable flow for heat dissipation of three-dimensional integrated wafer system Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a micro-flow channel with measurable flow for heat dissipation of a three-dimensional integrated wafer system, which comprises the following steps: the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of the silicon wafer on the insulator, and constructing a force-sensitive resistor and a temperature measuring resistor; releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide of the oxygen-buried layer below the release hole by a wet method to form a micro-channel; a release hole electroplated copper sealing step: depositing seed layer metal on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel; and (3) carrying out inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro-channel by using a chemical method.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a manufacturing method of a micro-flow channel with measurable flow for heat dissipation of a three-dimensional integrated wafer system.
Background
In the 'post-molar age', along with the development of advanced packaging technology, different chips can be integrated through high-density three-dimensional stacking, so that the performance of the system is greatly improved. However, the high-density integrated system can generate a large amount of heat, which seriously affects the normal operation of the chip. In recent years, heat dissipation from the inside of a three-dimensionally integrated chip has been started using a micro flow channel carrying a cooling liquid. The traditional method is that a groove body structure of a micro-channel is etched on the back surface of a chip, and then the micro-channel is aligned and bonded with another silicon chip or glass chip which is also etched with the groove body structure of the micro-channel to form a micro-channel closed pipeline; another common method is to coat the back of the chip with a groove structure of micro-channels by organic polymerization and etching, and then to attach with other liners to form micro-channel closed pipelines. Conventional practice requires the additional introduction of other liners and bonding processes, which not only increase the complexity of the process but also increase the thickness of the chip.
Disclosure of Invention
Aiming at the problems existing in the prior art, the embodiment of the application aims to provide a preparation method of a wafer heat dissipation micro-channel with a piezoresistive flow detection function, a Silicon-On-Insulator (SOI) wafer is used for developing a Silicon dioxide sacrificial release process of an oxygen buried layer, and a micro-channel closed pipeline can be formed by means of device layer Silicon, silicon dioxide of the oxygen buried layer and substrate layer Silicon of the SOI wafer without filling organic polymers; the copper electroplating sealing process and the inner wall selective electroless copper plating process are developed, and the formed copper column heat sink and the inner wall metallized copper layer greatly improve the heat dissipation capacity of the micro-channel; meanwhile, the piezoresistive flowmeter is integrated in the micro-flow channel, so that the flow velocity and the temperature of the cooling liquid micro-fluid can be detected in real time.
According to a first aspect of embodiments of the present application, there is provided a method for manufacturing a micro flow channel with a measurable flow for heat dissipation of a three-dimensional integrated wafer system, including:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of the silicon wafer on the insulator, and constructing a force-sensitive resistor and a temperature measuring resistor;
releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide of the oxygen-buried layer below the release hole by a wet method to form a micro-channel;
a release hole electroplated copper sealing step: depositing seed layer metal on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel;
and (3) carrying out inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro-channel by using a chemical method.
Further, the silicon-on-insulator wafer is the back side of the interposer with active integrated circuits or the back side of the silicon wafer interposer with completed vertical through-silicon vias and re-wiring layers.
Further, the piezoresistive flowmeter manufacturing steps include:
photoetching and etching the upper surface of the silicon-on-insulator wafer to form a first force-sensitive strain structure, wherein the first force-sensitive strain structure is a cantilever beam, a folding beam-flat plate or a film with holes;
forming a semiconductor force sensitive resistor on the first force sensitive strain structure by ion implantation;
forming a temperature measuring resistor by depositing metal near the force sensing resistor;
sputtering chromium/gold to form an ohmic contact electrode of the force-sensitive resistor and an interconnection line of the temperature-measuring resistor, and depositing a first passivation layer silicon dioxide by plasma enhanced chemical vapor deposition.
Further, the buried oxide layer silicon dioxide release step includes:
photoetching a release hole and a cooling liquid inlet and outlet hole on the upper surface of the silicon wafer on the insulator;
coating thick photoresist on the outer side wall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper surface of the insulator, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and wet etching the silicon dioxide of the oxygen-buried layer below the release hole through the release hole and the cooling liquid inlet and outlet hole to form a micro-channel for the cooling liquid to flow in the horizontal direction.
Further, the release hole electroplated copper sealing step comprises the following steps:
depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the sidewalls of the release holes;
growing copper in the release holes by an electroplating method to form copper column heat sinks;
stripping thick photoresist on the surface, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and depositing a second passivation layer silicon dioxide on the lower surface of the silicon-on-insulator wafer.
Further, the micro-channel inner wall inorganic copper plating step comprises the following steps:
and immersing the silicon wafer on the insulator into an electroless copper plating solution to form an upper surface copper deposition layer and a lower surface copper deposition layer on the upper surface and the lower surface of the inner wall of the micro-channel.
Further, the electroless copper plating solution comprises an activating solution and a reaction solution, the silicon wafer on the insulator is immersed into the activating solution for activation, and then immersed into the reaction solution for copper plating, wherein the activating solution comprises deionized water, hydrofluoric acid and palladium chloride, and the reaction solution comprises copper sulfate and formaldehyde.
Further, the method further comprises a vibration compensation step, wherein the vibration compensation step is arranged before the step of releasing the silicon dioxide of the buried oxide layer, and the step comprises the following steps:
and constructing a second force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer outside the micro-channel so as to eliminate errors generated by vibration on fluid pressure measurement.
Further, after the micro flow channel inner wall inorganic copper plating step, the second passivation layer silicon dioxide is removed.
According to a second aspect of embodiments of the present application, there is provided an application of the micro flow channel for heat dissipation of a three-dimensional integrated wafer system manufactured by the method according to the first aspect to prepare a silicon wafer interposer with a silicon vertical through hole or a redistribution layer for three-dimensional vertical stack integration of multi-layer integrated circuit chips or wafers.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
firstly, the micro-fluid channel is directly manufactured on the back of the wafer based on the SOI wafer, and the micro-fluid channel is not required to be formed by bonding with other silicon chips or glass sheets with micro-fluid channels, so that the process complexity is reduced;
secondly, the application skillfully develops a silicon dioxide sacrifice release process of the buried oxide layer based on the SOI wafer, and the micro-channel closed pipeline can be formed by means of the device layer silicon, the silicon dioxide of the buried oxide layer and the substrate layer silicon of the SOI wafer without filling organic polymers;
thirdly, the application skillfully develops an electroplated copper sealing process and an inner wall selective electroless copper plating process, wherein the electroplated copper column structure not only can seal the side wall of the micro-channel, but also can form a heat sink structure to improve heat dissipation capacity; the inner wall selective electroless copper plating process can deposit copper layers on the upper and lower surfaces of the inner wall of the micro-channel, so that the heat dissipation capacity of the inner wall of the micro-channel is further improved;
fourth, the present application developed a piezoresistive flow meter that was integrated with the micro-channel on-chip, and had temperature compensation and vibration compensation functions, and was able to monitor the flow rate and temperature of the cooling fluid in real time.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flowchart illustrating a flow-measurable micro flow channel manufacturing method for heat dissipation of a three-dimensional integrated wafer system according to an exemplary embodiment, wherein (a) in fig. 1 to (h) in fig. 1 are schematic structural diagrams of respective flows in the flow-measurable micro flow channel manufacturing method for heat dissipation of a three-dimensional integrated wafer system.
Fig. 2 is a schematic diagram illustrating a vibration compensation structure according to an exemplary embodiment.
Fig. 3 is a schematic top view of a flow-measurable micro-fluidic channel for three-dimensional integrated wafer system heat dissipation, according to an example embodiment.
Fig. 4 is a schematic diagram of an embodiment of a flow-measurable micro-fluidic channel for heat dissipation of a three-dimensional integrated wafer system in a three-dimensional integrated application field, according to an exemplary embodiment.
In the figure: 1. an SOI wafer; 2. a first force-sensitive strain structure; 3. a force sensitive resistor; 4. a temperature measuring resistor; 5. a first passivation layer of silicon dioxide; 6. a release hole; 7. buried oxide layer silicon dioxide; 8. a cooling liquid inlet and outlet hole; 9. thick photoresist; 10. a microchannel; 11. closing the column; 12. a second passivation layer of silicon dioxide; 13. a copper deposition layer on the upper surface; 14. a lower surface copper deposition layer; 15. a second force-sensitive strain structure; 16. an integrated circuit chip; 17. a micro bump; 18. a rewiring layer; 19. and a silicon vertical through hole.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
Fig. 1 is a flow chart illustrating a flow-measurable micro-fluidic channel manufacturing method for three-dimensional integrated wafer system heat dissipation, as shown in fig. 1, according to an exemplary embodiment, the method may include the steps of:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure 2 and constructing a force-sensitive resistor 3 and a temperature measuring resistor 4 on the upper surface of a silicon-on-insulator wafer;
releasing the buried oxide layer silicon dioxide 7: etching a release hole 6 on the upper surface of the silicon wafer on the insulator, and corroding the buried oxide layer silicon dioxide 7 below the release hole 6 by a wet method to form a micro-channel 10;
a step of copper electroplating and sealing the release holes 6: depositing seed layer metal on the upper surface of the silicon-on-insulator wafer and the side wall of the release hole 6, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel 10;
the inner wall of the micro-channel 10 is plated with copper in an inorganic way: copper heat dissipation layers are plated on the upper and lower surfaces of the inner wall of the micro flow channel 10 using a chemical method.
From the above embodiments, it can be seen that the present application directly makes a microfluidic channel on the back of the wafer based on the SOI wafer 1, and does not need to bond with other silicon wafers or glass sheets with the micro-channels 10 to form the micro-channels 10, thereby reducing the complexity of the process; the sacrificial release process of the buried oxide layer silicon dioxide 7 based on the SOI wafer 1 is skillfully developed, organic polymers are not required to be filled, and a micro-channel 10 closed pipeline can be formed by only relying on the device layer silicon, the buried oxide layer silicon dioxide 7 and the substrate layer silicon of the SOI wafer 1; the copper electroplating sealing process and the inner wall selective electroless copper plating process are skillfully developed, wherein the copper electroplating column structure not only can seal the side wall of the micro-channel 10, but also can form a heat sink structure to improve heat dissipation capacity; the inner wall selective electroless copper plating process can deposit copper layers on the upper and lower surfaces of the inner wall of the micro-channel 10, so that the heat dissipation capacity of the inner wall of the micro-channel 10 is further improved; a piezoresistive flow meter integrated with the micro flow channel 10 on the crystal is developed, and the piezoresistive flow meter has the functions of temperature compensation and vibration compensation, and can monitor the flow rate and the temperature of the cooling liquid in real time.
In a specific implementation of the piezoresistive flow meter manufacturing step, a first force-sensitive strain structure 2 is constructed on the upper surface of a silicon-on-insulator (SOI) wafer and a force-sensitive resistor 3 and a temperature-measuring resistor 4 are constructed;
as shown in fig. 1, the micro flow channels 10 are fabricated starting with a silicon-on-insulator (SOI) wafer, which may be the backside of a silicon wafer interposer already carrying active integrated circuits, or the backside of a silicon wafer interposer already completed with silicon vertical vias 19 (TSVs) and redistribution layers 18 (RDLs). This step may specifically comprise the following processes:
photoetching and etching the upper surface of the silicon wafer on the insulator to form a first force-sensitive strain structure 2, wherein the first force-sensitive strain structure 2 is a cantilever beam, a folded beam-flat plate or a film with holes; forming a semiconductor force-sensitive resistor 3 on the first force-sensitive strain structure 2 by ion implantation; forming a temperature measuring resistor 4 by depositing metal near the force sensing resistor 3; sputtering chromium/gold to form ohmic contact electrodes and interconnection lines of the force sensitive resistor 3, and depositing a first passivation layer silicon dioxide 5 by plasma enhanced chemical vapor deposition. In a specific implementation, the temperature measuring resistor 4 is preferably formed by sputtering chromium/platinum, the ohmic contact electrode and the interconnection line of the force sensitive resistor 3 are preferably formed by sputtering chromium/gold, and the first passivation layer silicon dioxide 5 is preferably deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) (fig. 1 (b)).
The method may further include a vibration compensation step before the buried oxide layer silicon dioxide 17 release step, and may include:
a second force-sensitive strain structure 15 is formed on the upper surface of the silicon-on-insulator wafer outside the micro flow channel 10 to eliminate errors in the fluid pressure measurement caused by vibration.
Fig. 2 shows a vibration compensation structure of the micro flow channel 10 capable of measuring flow velocity, pressure and temperature according to the present invention. Since the first force-sensitive strain structure 2 has a certain vibration sensitivity, in order to eliminate errors generated in the measurement of fluid pressure by vibration, a second force-sensitive strain structure 15 with the same mechanical sensitive structure as the first force-sensitive strain structure 2 can be manufactured at a position outside the micro flow channel 10, and the second force-sensitive strain structure 15 is also provided with a force-sensitive resistor 3 and a temperature measuring resistor 4, and the specific forming process is the same as the manufacturing steps of the piezoresistive flowmeter, which are not described herein. The force-sensing resistor 3 on the second force-sensing strain structure 15 only senses the piezoresistive resistance value change caused by vibration and is not affected by micro-fluid, so that the piezoresistive resistance values measured by the two force-sensing resistors 3 can be used for eliminating the vibration effect through calculation.
In the implementation of the release step of the buried oxide layer silicon dioxide 7, a release hole 6 is etched on the upper surface of the silicon wafer on the insulator, and the buried oxide layer silicon dioxide 7 below the release hole 6 is etched by a wet method to form a micro-channel 10;
specifically, the upper surface of the silicon wafer on the insulator is subjected to photoetching to etch a release hole 6 and a cooling liquid inlet and outlet hole 8; coating thick photoresist 9 on the outer side wall of the cooling liquid inlet and outlet hole 8 and the first passivation layer silicon dioxide 5 on the upper surface of the silicon on insulator, wherein the thickness of the thick photoresist 9 is more than or equal to 10 micrometers, in a specific implementation, the thickness of the photoresist depends on the thickness of a step, and in order to ensure the wall thickness of a micro-channel, a device layer SOI wafer of more than 5 micrometers is generally selected, so the thickness of the thick photoresist 9 is preferably 10 micrometers; the buried oxide layer silicon dioxide 7 below the release holes 6 is subjected to wet etching through the release holes 6 and the cooling liquid inlet and outlet holes 8 to form micro flow channels 10 for the cooling liquid to flow in the horizontal direction. In a specific implementation, the first passivation layer silicon dioxide 5 and the upper surface silicon of the SOI wafer 1 are etched to form an oxygen-buried layer release hole 6 ((c) in fig. 1), the upper surface silicon of the SOI wafer 1 and the oxygen-buried layer silicon dioxide 7 are etched to form a cooling liquid access hole 8 ((d) in fig. 1), thick photoresist 9 is coated by spin coating or spray coating, and a structure in which only the inner side wall and the inner bottom of the microfluidic access hole and the exposed outer side wall and the outer surface are protected by photoresist is formed by photolithography (e) in fig. 1). The buried oxide layer silicon dioxide 7 of the SOI wafer 1 is released by a wet process, preferably hydrofluoric acid, to form a micro flow channel 10.
In the implementation of the step of electroplating copper to close the release holes 6, depositing seed layer metal on the upper surface of the silicon-on-insulator wafer and the side walls of the release holes 6, and forming copper pillars to close the upper surface of the micro flow channels 10 based on the seed layer electroplating copper;
specifically, a chromium/copper seed layer is deposited on the upper surface of the silicon-on-insulator wafer and the sidewalls of the release holes 6; growing copper in the release holes 6 by electroplating to form copper column heat sinks, and stripping thick photoresist 9 on the surfaces; a second passivation layer of silicon dioxide 12 is deposited on the lower surface of the silicon-on-insulator wafer. In practice, it is preferable to sputter chromium/copper, form a seed layer on the side wall and the outer surface of the release hole 6, and perform copper electroplating to form a closed cylinder 11, which functions as both a closure for the upper side wall of the micro flow channel 10 and a heat sink. And stripping the thick photoresist 9 coated on the outer side wall of the cooling liquid inlet and outlet hole 8 and the first passivation layer silicon dioxide 5 on the upper surface of the silicon on insulator after electroplating. Finally, a second passivation layer silicon dioxide 12 is deposited on the lower surface of the SOI wafer 1 by PECVD ((f) in fig. 1).
In the embodiment of the step of plating the inner wall of the micro flow channel 10 with copper, a chemical method is used to plate copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro flow channel 10.
Specifically, the silicon-on-insulator wafer is immersed in an electroless copper plating solution, and then an upper surface copper deposition layer 13 and a lower surface copper deposition layer 14 are formed on the upper and lower surfaces of the inner wall of the micro flow channel 10. In practice, the SOI wafer 1 is immersed in an electroless copper plating solution to form a copper deposit on the silicon surface, but no copper deposit on the inactive silicon oxide surface. Thus, the upper surface copper deposition layer 13 and the lower surface copper deposition layer 14 are also formed on the upper and lower surfaces of the inner wall of the micro flow channel 10, further improving the heat dissipation capability of the micro flow channel 10 ((g) in fig. 1). Methods of electroless plating metal layers include, but are not limited to, copper, gold, nickel. Taking electroless copper plating as an example, the electroless copper plating solution comprises an activating solution and a reaction solution, the silicon wafer on the insulator is immersed into the activating solution for activation, and then immersed into the reaction solution for copper plating, wherein the activating solution comprises deionized water, hydrofluoric acid and palladium chloride, and the reaction solution comprises copper sulfate and formaldehyde.
After the step of inorganic copper plating on the inner wall of the micro flow channel 10, the second passivation layer silicon dioxide 12 is removed ((h) in fig. 1).
Fig. 3 (a) is a schematic top view of a wafer heat dissipation micro-fluidic channel 10 with piezoresistive flow detection function. The measuring principle of the micro-fluid flow velocity is piezoresistance, and when in operation, the cooling liquid flows to drive the first force-sensitive strain structure 2 of the cantilever structure to generate elastic deformation, so that the resistance value of the force-sensitive resistor 3 is changed, and the corresponding flow velocity and flow of the cooling liquid can be obtained by detecting the change of the resistance value. Since the resistance value of the force sensitive resistor 3 is sensitive to temperature, the invention is provided with a platinum temperature measuring resistor 4 near the force sensitive resistor 3 for temperature drift compensation of the force sensitive resistor 3. An embodiment of a first force-sensitive strain structure 2 based on a beam-slab structure according to the invention is shown in fig. 3 (b).
The application also provides an application of the micro-flow channel with measurable flow for heat dissipation of the three-dimensional integrated wafer system, which is manufactured by the method, and is used for preparing the silicon wafer adapter plate with the silicon vertical through holes or the rewiring layer, so as to be used for three-dimensional vertical stacking integration of the multi-layer integrated circuit chips or wafers. Fig. 4 illustrates an embodiment of the flow-measurable micro-fluidic channel for heat dissipation of a three-dimensional integrated wafer system in a three-dimensional integrated application field. The integrated circuit chip 16 is bonded with the silicon wafer adapter plate with the rewiring layer 18 and the heat dissipation micro-channel 10 through the micro-bumps 17, and signals are led out from the bottom through the silicon vertical through holes 19 (TSVs), so that the heat dissipation capacity of the three-dimensional integrated system can be effectively improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof.
Claims (9)
1. The manufacturing method of the micro-flow channel with measurable flow for heat dissipation of the three-dimensional integrated wafer system is characterized by comprising the following steps of:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of the silicon wafer on the insulator, and constructing a force-sensitive resistor and a temperature measuring resistor;
releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide of the oxygen-buried layer below the release hole by a wet method to form a micro-channel;
a release hole electroplated copper sealing step: depositing seed layer metal on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and electroplating copper on the basis of the seed layer to form a copper column to seal the upper surface of the micro-channel;
and (3) carrying out inorganic copper plating on the inner wall of the micro-channel: plating copper heat dissipation layers on the upper and lower surfaces of the inner wall of the micro-channel by using a chemical method;
wherein, the step of releasing the silicon dioxide of the buried oxide layer comprises the following steps:
photoetching a release hole and a cooling liquid inlet and outlet hole on the upper surface of the silicon wafer on the insulator;
coating thick photoresist on the outer side wall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper surface of the insulator, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and wet etching the silicon dioxide of the oxygen-buried layer below the release hole through the release hole and the cooling liquid inlet and outlet hole to form a micro-channel for the cooling liquid to flow in the horizontal direction.
2. The method of claim 1, wherein the silicon-on-insulator wafer is a backside of a silicon wafer interposer with active integrated circuits or completed silicon vertical vias and re-wiring layers.
3. The method of claim 1, wherein the piezoresistive flow meter manufacturing step comprises:
photoetching and etching the upper surface of the silicon-on-insulator wafer to form a first force-sensitive strain structure, wherein the first force-sensitive strain structure is a cantilever beam, a folding beam-flat plate or a film with holes;
forming a semiconductor force sensitive resistor on the first force sensitive strain structure by ion implantation;
forming a temperature measuring resistor by depositing metal near the force sensing resistor;
sputtering chromium/gold to form an ohmic contact electrode of the force-sensitive resistor and an interconnection line of the temperature-measuring resistor, and depositing a first passivation layer silicon dioxide by plasma enhanced chemical vapor deposition.
4. The method of claim 1, wherein the release hole electroplated copper closing step comprises:
depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the sidewalls of the release holes;
growing copper in the release holes by an electroplating method to form copper column heat sinks;
stripping thick photoresist on the surface, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and depositing a second passivation layer silicon dioxide on the lower surface of the silicon-on-insulator wafer.
5. The method of claim 1, wherein the micro-fluidic channel inner wall inorganic copper plating step comprises:
and immersing the silicon wafer on the insulator into an electroless copper plating solution to form an upper surface copper deposition layer and a lower surface copper deposition layer on the upper surface and the lower surface of the inner wall of the micro-channel.
6. The method of claim 5, wherein the electroless copper plating solution comprises an activation solution and a reaction solution, the silicon-on-insulator wafer is activated by immersing in the activation solution, and then copper plating is performed by immersing in the reaction solution, wherein the activation solution comprises deionized water, hydrofluoric acid, and palladium chloride, and the reaction solution comprises copper sulfate and formaldehyde.
7. The method of claim 1, further comprising a shock compensation step disposed prior to the buried oxide layer silicon dioxide release step, the step comprising:
and constructing a second force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer outside the micro-channel so as to eliminate errors generated by vibration on fluid pressure measurement.
8. The method of claim 4, wherein the second passivation layer silicon dioxide is removed after the micro-fluidic channel inner wall inorganic copper plating step.
9. Use of a flow-measurable micro-fluidic channel for heat dissipation of a three-dimensional integrated wafer system manufactured according to the method of any of claims 1-8 for the preparation of a silicon wafer interposer with vertical through-silicon vias or redistribution layers for three-dimensional vertical stack integration of multilayer integrated circuit chips or wafers.
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