CN115863164B - Etching processing method and device and semiconductor device - Google Patents
Etching processing method and device and semiconductor device Download PDFInfo
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- CN115863164B CN115863164B CN202310190899.7A CN202310190899A CN115863164B CN 115863164 B CN115863164 B CN 115863164B CN 202310190899 A CN202310190899 A CN 202310190899A CN 115863164 B CN115863164 B CN 115863164B
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Abstract
The present disclosure relates to an etching processing method and apparatus, and a semiconductor device. The etching processing method comprises the following steps: forming a first mask layer covering the region to be etched, wherein the first mask layer has different equivalent etching thicknesses along the positions parallel to the first direction of the region to be etched; etching the region to be etched through the first mask layer, and etching the first mask layer, wherein the etching step comprises the following steps: and continuously adjusting the etching selection ratio of the first mask layer to the region to be etched by continuously adjusting etching parameters, wherein the etching parameters comprise the concentration ratio of the first etching gas to the second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the region to be etched. The etching processing method can realize the etching processing surface with accurate appearance.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an etching processing method and apparatus, and a semiconductor device.
Background
The power semiconductor device is a core element in the power electronic technology, and the main working state of the power semiconductor device can be divided into a conducting state and a blocking state, wherein in the blocking state, the two ends of the device bear higher voltage, and higher electric field intensity exists inside the device. Since the main junction device of the device is terminated abruptly at the edge, an electric field concentration phenomenon is easily generated in a blocking state, resulting in higher electric field strength at the edge than inside the device. Higher electric field strengths tend to lead to premature breakdown of the device at the edges of the device, resulting in reduced device withstand voltage, and therefore power devices require terminal structures arranged around the main junction to relax the electric field. Common termination structures include Field Plate (FP), field limiting ring (Field Limited Rings, FLR), junction termination extension (Junction Termination Edge, JTE), ramp termination (Bevel Termination), and the like. The field plate, the field limiting ring and other terminals have simple structures and small influence by process bias voltage, but have large occupied areas, so the field plate, the field limiting ring and other terminals are suitable for medium-low voltage-resistant devices; the junction terminal expansion structure occupies smaller area under the same voltage resistance, so that the junction terminal expansion structure is more suitable for high voltage resistance devices.
The junction termination extension structure is one or more lightly doped regions of the same conductivity type extending outward from the device main junction. When the device bears the withstand voltage, the lightly doped junction terminal extension region is completely depleted, and a high-resistance region which allows potential lines to pass through and can support voltage is formed, so that the electric field is relieved. Because the electric field distribution is strongly dependent on the distribution of the fixed charges in the junction termination extension structure, it is desirable to precisely control the dopant dose distribution inside. The amount of dopant that is generally desired varies continuously and gradually decreases from the main junction to the outside of the termination.
This ideal state is far from being achieved in practical production processes. In some production processes, a step etching process is adopted to form multi-region junction terminal extension, a layer of region with single doping concentration can be formed first, then steps are formed in the region, the steps are deeper the farther the steps are from the main junction, and then the total doping amount of the reserved portion is smaller. The process needs cyclic etching, each etching process needs to independently manufacture a photoetching plate, independently manufacture a mask and independently carry out etching process operation, and is long in time consumption and high in cost; when terminals with different designs need to be compared, a plurality of sets of different photoetching plates need to be designed, which is not beneficial to rapid iterative optimization design.
Disclosure of Invention
Based on this, it is necessary to provide an etching processing method and apparatus, and a semiconductor device, aiming at the problem of doping concentration distribution of the junction termination extension structure.
The embodiment of the disclosure provides an etching processing method, which comprises the following steps: forming a first mask layer covering the region to be etched, wherein the first mask layer has different equivalent etching thicknesses along the positions parallel to the first direction of the region to be etched; etching the region to be etched through the first mask layer, and etching the first mask layer, wherein the etching step comprises the following steps: and continuously adjusting the etching selection ratio of the first mask layer to the region to be etched by continuously adjusting etching parameters, wherein the etching parameters comprise the concentration ratio of the first etching gas to the second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the region to be etched.
According to the etching processing method provided by the embodiment of the disclosure, the etching surface with the morphology controllable and adjustable in multiple dimensions can be obtained by continuously adjusting the etching parameters in the etching step, and the adjusting mode is sensitive, direct and easy to control, so that the processing precision of the etching processing method is high and the implementation is easy. In addition, the method can get rid of from the design limit of the photoetching plate, if the shape of the etched surface is required to be optimized, a brand new layout is not required to be redesigned, photoetching parameters are not required to be readjusted, the etched surface can be changed under the condition that the design of the photoetching plate or the shape of the photoresist is not required to be changed, the steps are few, the iteration speed is high, and the research and development efficiency is high.
In the manufacturing process of the junction termination extension structure, the etching processing method provided by the embodiment of the disclosure can prepare the junction termination extension structure which is more similar to ideal dopant quantity distribution. The semiconductor device manufactured by the embodiment of the disclosure can fully improve the effect of relieving the electric field of the terminal, reduce the concentration effect of the electric field at the edge of the device and improve the overall withstand voltage of the device. The invention can rapidly verify the design of the doping amount of the expansion of various junction terminals on the same set of photoetching plate design, thereby being beneficial to reducing the development cost and improving the development efficiency.
In some embodiments, the equivalent etch thickness is proportional to the geometric thickness of the first mask layer. For example, the equivalent etch thickness may be equal to the geometric thickness.
By this arrangement, the variation of the equivalent etching thickness can be controlled relatively simply.
In some embodiments, the equivalent etch thickness is proportional to the density of the first mask layer.
By the arrangement, the etching processing method can be combined into various processes, and different processes can be utilized to realize more dimensional changes of equivalent etching thickness.
In some embodiments, the step of forming the first mask layer includes: forming a photoresist mask with uniform geometric thickness; and baking the photoresist mask in different modes at different positions to form a first mask layer with uneven geometric thickness.
The first mask layer can be realized relatively simply in a baking mode, so that the use of the layout is reduced, and the manufacturing cost is reduced.
In some embodiments, the step of forming the first mask layer includes: forming a photoresist mask with uniform geometric thickness; photoetching the photoresist mask through a photoetching plate with a gradual change pattern, wherein the light-transmitting parts and the light-non-transmitting parts at different positions of the gradual change pattern along the first direction have different proportions; and developing the photoresist mask subjected to photolithography.
So arranged, the first mask layer can be formed by one common photolithography process.
In some embodiments, the step of forming the first mask layer includes: forming a photoresist mask with uniform geometric thickness; performing a laser direct writing exposure process on the photoresist mask, wherein laser with different exposure doses is irradiated at different positions corresponding to the photoresist mask; and developing the photoresist mask subjected to the laser direct writing exposure process.
The first mask layer can be conveniently realized through a laser direct writing exposure process.
In some embodiments, the region to be etched is a pre-doped region, the material of the pre-doped region comprising silicon carbide, the pre-doped region being etched in the first direction to a length of greater than or equal to 100 μm.
By the arrangement, the semiconductor structure with better performance can be realized by using the wide forbidden band material. In addition, the etching processing method can be used for accurately processing the large-scale structure.
In some embodiments, the step of adjusting the etch parameters includes: at least one of gas composition, flow rate, chamber pressure, chamber temperature, electrode bias, and electrode power is adjusted.
By organically adjusting the etching parameters, the etching selection ratio can be precisely controlled, and thus the etched surface of the desired morphology can be more precisely realized.
In some embodiments, the region to be etched and the main junction are arranged along the first direction, and the position of the first mask layer, which is far away from the main junction, has smaller equivalent etching thickness.
By the arrangement, a junction terminal expansion structure with ideal dopant quantity distribution is formed on the main junction edge, and the distribution of equivalent etching thickness of the first mask layer is limited, so that the process is simplified, and the process difficulty is reduced.
In some embodiments, the etched surface of the region to be etched includes a curved surface.
The etching processing method provided by the embodiment of the disclosure can accurately process the etching surface with the expected morphology, and the processed curved surface or plane shape is controllable and the gesture is accurate.
In some embodiments, the etching processing method further comprises: forming a second mask layer covering the prefabricated doped region, wherein the second mask layer is a region to be etched, and the doped region is made of silicon carbide; the step of forming a first mask layer covering the area to be etched comprises the following steps: a first mask layer is formed overlying the second mask layer.
In some embodiments, the etching processing method further comprises: forming a second mask layer covering the region to be doped, wherein the second mask layer is the region to be etched, and the material of the region to be doped comprises silicon carbide; taking the etched second mask layer as an implantation mask, and performing ion implantation on the region to be doped; the step of forming a first mask layer covering the area to be etched comprises the following steps: a first mask layer is formed overlying the second mask layer.
The etching processing method provided by the embodiment of the disclosure can be used for etching different structures, for example, the prefabricated doped region can be processed through the first mask layer, and the second mask layer can also be processed through the first mask layer, so that the morphology formed by the second mask layer is utilized in the subsequent process step to realize a new effect.
The embodiment of the present disclosure further provides, in another aspect, an etching processing apparatus, including: a first processing unit configured to: the first mask layer is used for forming a first mask layer covering the area to be etched, and the first mask layer has different equivalent etching thicknesses along the position parallel to the first direction of the area to be etched; a second processing unit configured to: the etching device is used for etching the area to be etched through the first mask layer and etching the first mask layer; and a control unit configured to: and continuously adjusting the etching selection ratio of the first mask layer to the region to be etched by continuously adjusting etching parameters, wherein the etching parameters comprise the concentration ratio of the first etching gas to the second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the region to be etched.
The etching processing device provided by the embodiment of the disclosure can accurately perform etching processing on the area to be etched according to the requirement and can be used for accurately forming the etching surface in a desired form.
In another aspect, the disclosed embodiments provide a semiconductor device including: a main junction; and the junction terminal expansion structure is arranged with the main junction along the first direction, and the junction terminal expansion structure is formed by the etching processing method.
The semiconductor device has better use performance. The dopant amount of the junction termination extension structure may approach an ideal state, and the withstand voltage value may approach an ideal value. In addition, it can be manufactured more easily at a lower process cost.
Drawings
FIG. 1 is a schematic flow diagram of an etching processing method provided by an embodiment of the present disclosure;
fig. 2 is a schematic structural view of a prefabricated semiconductor structure provided in an embodiment of the present disclosure;
FIG. 3 is a theoretical plot of the dopant amount of a junction termination structure provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a lithographic step provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an etching step provided by an embodiment of the present disclosure;
FIG. 6 is a finite element analysis initial schematic of an etching step provided by an embodiment of the present disclosure;
FIG. 7 is a first step schematic diagram of finite element analysis of an etching step provided by an embodiment of the present disclosure;
FIG. 8 is a second step schematic diagram of finite element analysis of an etching step provided by an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an etching step in progress provided by an embodiment of the present disclosure;
FIG. 10 is a schematic diagram of an etching step at the end provided by an embodiment of the present disclosure;
FIG. 11 is a schematic diagram of an etching step at the end of an embodiment of the present disclosure;
FIG. 12 is a graph showing the variation of the etching selectivity in an etching step according to an embodiment of the present disclosure;
FIG. 13 is a graph showing the variation of gas flow in an etching step provided by embodiments of the present disclosure;
FIG. 14 is a schematic diagram of another structure to be etched according to an embodiment of the present disclosure;
fig. 15 is a schematic structural diagram of another structure to be etched according to an embodiment of the present disclosure;
fig. 16 is a schematic view of a semiconductor structure after a step of etching a second mask layer according to an embodiment of the present disclosure;
fig. 17 is a schematic view of a semiconductor structure after an ion implantation step according to an embodiment of the present disclosure;
fig. 18 is a block diagram of an etching apparatus according to an embodiment of the present disclosure.
Reference numerals illustrate: 1. prefabricating a semiconductor structure; 2. an epitaxial layer; 3. a main junction; 301. a first surface; 4. junction termination extension structure; 40. prefabricating a doping area; 401. a second surface; 402. an origin; 41. a first doping section; 42. a second doping section; 50. a photoresist mask; 5. a first mask layer; 51. a first mask part; 52. a second step of masking the part; 6. a photolithography plate; 7. irradiating light; 8. an etchant; 9. a second mask layer; 90. the etched second mask layer; 100. etching processing device; 101. a first processing unit; 102. a second processing unit; 103. and a control unit.
Detailed Description
In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, a detailed description of specific embodiments of the present disclosure is provided below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. The disclosed embodiments may be embodied in many other forms other than described herein and similar modifications may be made by those skilled in the art without departing from the spirit of the disclosed embodiments, so that the disclosed embodiments are not limited to the specific examples of embodiments described below.
In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the embodiments of the present disclosure and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present disclosure.
In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. For example, the first surface may also be referred to as a second surface, and the second surface may also be referred to as a first surface. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
In the presently disclosed embodiments, the terms "connected," "connected," and the like are to be construed broadly and, unless otherwise specifically indicated and defined, as being either fixedly connected, detachably connected, or integrally formed, for example; can be flexible connection or rigid connection along at least one direction; can be mechanically or electrically connected; either directly, indirectly, through intermediaries, or both, or in which case the intermediaries are present, or in which case the two elements are in communication or in which case they interact, unless explicitly stated otherwise. The terms "mounted," "disposed," "secured," and the like may be construed broadly as connected. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.
As used herein, the terms "layer," "region" and "regions" refer to portions of material that include regions having a certain thickness. The layers can extend horizontally, vertically and/or along a tapered surface. The layer can be a region of uniform or non-uniform continuous structure, whose thickness perpendicular to the direction of extension may be no greater than the thickness of the continuous structure. The layer can include multiple layers. The various regions in the figures, the shapes of the layers and their relative sizes and positional relationships are exemplary only, as may be subject to variations due to manufacturing tolerances or technical limitations, and may be adjusted to actual requirements.
Referring to fig. 1, fig. 1 shows a flow of an etching processing method in an embodiment of the present disclosure. The etching processing method 1000 provided in the embodiment of the present disclosure includes the following steps S101 to S102.
In step S101, a first mask layer is formed. The first mask layer can be positioned on one side of the region to be etched and covers the region to be etched. The first mask layer has different equivalent etching thicknesses everywhere along a first direction parallel to the region to be etched.
Step S102, etching the area to be etched through the first mask layer, and etching the first mask layer. In the etching step, the etching selection ratio of the first mask layer to the region to be etched is continuously adjusted by continuously adjusting etching parameters. The etching process may be dry etching, and the etching gas may be a mixed gas, and may include a first etching gas and a second etching gas, where the first etching gas is mainly used to etch the first mask layer, and the second etching gas is mainly used to etch the region to be etched. The etching selection ratio of the first mask layer to the region to be etched can be adjusted in real time by controlling the concentration ratio of the first etching gas and the second etching gas.
According to the etching processing method provided by the embodiment of the disclosure, the etching selection ratio of the first mask layer to the area to be etched can be continuously adjusted during etching by continuously adjusting the concentrations of the first etching gas and the second etching gas, so that the shape of the etched surface can be accurately controlled.
Next, an etching processing method provided in an embodiment of the present disclosure is described in detail with reference to fig. 2 to 10.
As shown in fig. 2, fig. 2 shows a prefabricated semiconductor structure 1 in an embodiment of the present disclosure. In some embodiments, the prefabricated semiconductor structure 1 comprises an epitaxial layer 2, a main junction 3 and a prefabricated doped region 40. The main junction 3 extending into the epitaxial layer 2 in the Y-axis direction may be formed by a semiconductor manufacturing process. The pre-doped region 40 may be formed by an epitaxial growth process or an ion implantation process.
The pre-doped regions 40 and the main junction 3 may be aligned in the X-axis direction. Illustratively, the pre-doped region 40 may interface with the main junction 3. The main junction 3 has a first surface 301 and the pre-doped region 40 has a second surface 401. In the cross-section shown in fig. 2, the junction of the first surface 301 and the second surface 401 has an origin 402.
The material of the prefabricated semiconductor structure 1 comprises at least one of silicon carbide, silicon germanium, a group iii-v compound such as gallium nitride and gallium arsenide. Illustratively, the material of the prefabricated semiconductor structure 1 comprises silicon carbide and the material of the prefabricated doped region 40 comprises a wide bandgap semiconductor material such as silicon carbide.
Illustratively, the pre-doped region 40 is a region to be etched. Junction termination extension structures 4 (fig. 10) may be formed with respect to the main junction 3 based on the pre-doped regions 40. The doping concentration in the pre-doped region 40 may be uniform.
Fig. 3 shows a theoretical plot of the dopant amount of a junction termination structure provided by an embodiment of the present disclosure. Taking the direction away from the main junction 3 as the positive direction of the X axis and taking the origin 402 as the origin of the coordinate system, according to the theoretical curve shown in FIG. 3, the larger the doping amount of the junction termination extension structure 4 is, the smaller the doping amount is at the position away from the origin 402. The variation of the dopant amount of the junction termination extension structure 4 may be a continuously varying curve.
Based on the pre-doped region 40 having a uniform doping concentration, the pre-doped region 40 may be processed to have different thicknesses throughout in order to have the amount of doping throughout in the X-axis direction satisfy a theoretical value. The line shape of the machined surface in a section parallel to the XY plane may be the same as the theoretical curve.
FIG. 4 illustrates the principle of a lithographic step provided by embodiments of the present disclosure. Referring to fig. 4, an etching processing method provided in an embodiment of the present disclosure includes a step of forming a photoresist mask 50. The photoresist mask 50 covers at least the pre-doped region 40. The geometric thickness of the photoresist mask 50, i.e., the dimension of the photoresist mask 50 along the Y-axis in fig. 4, may be substantially uniform.
The photoresist mask 50 may be subjected to photolithography by a photolithography plate 6 having a graded pattern. As shown in fig. 4, the irradiation light 7 irradiates the photolithography plate 6, and then a part of the light is blocked by the photolithography plate 6, and a part of the light may irradiate the photoresist mask 50 through the photolithography plate 6. The light transmitting portions and the light impermeable portions of the graded pattern of the reticle 6 at different positions along the first direction have different ratios. In some embodiments, the greater the ratio of the size of the light-transmitting portion to the size of the light-opaque portion in the gradation pattern at a position further from the main junction 3 in the X-axis direction means that the greater the exposure dose to which the photoresist mask 50 is exposed at a position further from the main junction 3.
The photoresist mask 50 may be positive photoresist, and then after the photoresist mask 50 is developed, the larger the thickness of the photoresist is washed out, the smaller the thickness of the photoresist is washed out. Referring to fig. 5, the first mask layer 5 obtained after development may correspond to the pre-doped region 40, and the portion of the first mask layer 5 farther from the main junction 3 is thinner. The equivalent etching thickness of the first mask layer 5 is proportional to the geometric thickness of the first mask layer 5, for example, may be 1:1.
it will be appreciated that the surface topography of the first mask layer 5 formed by embodiments of the present disclosure may be formed into other morphologies as desired.
In other embodiments, the step of forming the first mask layer 5 may include: forming a photoresist mask 50 having a uniform geometric thickness; different positions of the photoresist mask 50 are then baked in different ways to form a first mask layer 5 having a non-uniform geometric thickness. The photoresist mask 50 is baked to shrink, and different positions of the photoresist mask 50 shrink to different degrees by baking, so that the part with lighter shrinkage is thicker and the part with heavier shrinkage is thinner.
In other embodiments, the step of forming the first mask layer 5 includes: forming a photoresist mask 50 having a uniform geometric thickness; performing a laser direct writing exposure process on the photoresist mask 50, and irradiating lasers with different exposure doses at different positions corresponding to the photoresist mask 50; the photoresist mask 50 after the laser direct write exposure process is then developed. The locations with large exposure dose can be more material removed during development.
Fig. 5 schematically illustrates an etching step provided by an embodiment of the present disclosure. The pre-doped region 40 may be etched through the first mask layer 5, the first mask layer 5 and the pre-doped region 40 having an etch selectivity with respect to the etchant 8, i.e. the first mask layer 5 and the pre-doped region 40 having different etch rates under the same etch process parameters.
Fig. 6 shows a finite element analysis initial schematic of an etching step provided by an embodiment of the present disclosure. In the XY coordinate system shown in FIG. 6, the intersection of the X-axis and the Y-axis may be the origin 402, a straight lineyBelow =0 is a semiconductor structure, fig. 6 shows a pre-doped region 40; the first mask layer 5 above this line is located in the interval 0,x N ]inside, willThe interval is divided intoNBetween cells: (0,x 1 )、(x 1 ，x 2 )、……、(x N-2 ，x N-1 )、(x N-1 ，x N ) The method comprises the steps of carrying out a first treatment on the surface of the Provision for provision ofx 0 =0. Within each cell, the photoresist thickness is assumed to be uniform, wherex i-1 ，x i ) The thickness of the photoresist in the interior isf(x i )，i=1、2……NPrescribingf(x N )=0。
Fig. 7 is a first step schematic diagram of finite element analysis of an etching step provided by an embodiment of the present disclosure. In the etching step, the etching parameters of each step can be adjusted as required, for example, the etching selectivity ratio of the first mask layer 5 to the pre-doped region 40 in the first step is controlled to bek(x N ). The structure shown in fig. 7 is obtained by a first etching step, in which the first mask layer 5 is etched to form a first mask portion 51 and the pre-doped region 40 is etched to form a first doped portion 41. As shown in fig. 7, the rightmost inter-cell spacex N-1 ，x N ) The inner photoresist is initially zero in thickness so that the underlying semiconductor material is etched away first. Right count second inter-cell x N-2 ，x N-1 ) The thickness of the photoresist in the interior is as follows in the initial statef(x N-1 ) When the photoresist in the cells is etched, the thickness of the photoresist in each cell isf(x N-1 ) While the original pre-doped region 40 corresponds to the rightmost cellx N-1 ，x N ) Is etched to a depth ofk(x N )f(x N-1 ). As shown in fig. 7, the first doping part 41 corresponds to the second cell of the right numberx N-2 ，x N-1 ) Is exposed. The first step mask portion 51 corresponds to the third cell of the right numberx N-3 ，x N-2 ) Is of the thickness off(x N-2 )-f(x N-1 )。
Fig. 8 is a second step schematic diagram of finite element analysis of an etching step provided by an embodiment of the present disclosure. In the second step, the etching parameters are adjusted, and the etching selection ratio of the first mask portion 51 to the first doped portion 41 in the second step is controlled to bek(x N-1 ). The structure shown in fig. 8 is obtained by the second etching step, the first mask portion 51 is etched to form a second mask portion 52, and the first doped portion 41 is etched to form a second doped portion 42. As shown in fig. 8, the two rightmost cells are [ ]x N-1 ，x N ) And%x N-2 ，x N-1 ) The thickness of the photoresist in the interior is zero at the beginning of the second step, so that the underlying semiconductor material is etched away. Right third inter-cellx N-3 ，x N-2 ) The thickness of the photoresist in the interior is as follows in the initial statef(x N-2 )-f(x N-1 ) When the photoresist in the cells is etched in the second step, the total thickness of the photoresist in each cell is f(x N-1 )+f(x N-2 )-f(x N-1 )=f(x N-2 ) For example, right number of fourth cellsx N-4 ，x N-3 ) The thickness of the inner photoresist isf(x N-3 )-f(x N-2 ) The method comprises the steps of carrying out a first treatment on the surface of the And the second doped portion 42 is compared with the original doped region 40, and the second doped portion is arranged between the second cells corresponding to the right numberx N-2 ，x N-1 ) Is etched to a depth ofk(x N-1 )[f(x N-2 )-f(x N-1 )]The rightmost cellx N-1 ，x N ) The total depth of the etched part isk(x N-1 )[f(x N-2 )-f(x N-1 )]+k(x N )f(x N-1 ). As shown in fig. 8, the second doped portion 42 corresponds to the third cell of the right numberx N-3 ，x N-2 ) Is exposed.
Analogize to the above rule, in the etching stepkIn the stage, the etching selectivity of the etching process becomesk(x N-k+1 ) Inter-cell [ ]x N-k ，x N-k+1 ) The photoresist thickness is zero inside and thus the semiconductor material underneath it begins to be etched away.
Inter-cell [ ]x N-k-1 ，x N-k ) The thickness of the photoresist in the interior isf(x N-k )-f(x N-k+1 ) When the photoresist inside the cell is etched, the cell is divided into two partsx N-k ，x N-k+1 ) The semiconductor material is etched to a depth ofk(x N-k+1 )[f(x N-k )-f(x N-k+1 )]Inter-cell [ ]x N-k+1 ，x N-k+2 ) The total depth of the etched semiconductor material isk(x N-k+1 )[f(x N-k )-f(x N-k+1 )]+k(x N-k+2 )[f(x N-k+1 )-f(x N-k+2 )]Inter-cell [ ]x N-1 ，x N ) The total depth of the etched semiconductor material isk(x N-k+1 )[f(x N-k )-f(x N-k+1 )]+k(x N-k+2 )[f(x N-k+1 )-f(x N-k+2 )]+…+k(x N )f(x N-1 )。
The photoresist thickness in all other cells is correspondingly reducedf(x N-k )-f(x N-k+1 ) I.e. (0,x 1 )、(x 1 ，x 2 )、……、(x N-k-2 ，x N-k-1 ) The photoresist thickness in each cell is respectivelyf(x 1 )-f(x N-k )、f(x 2 )-f(x N-k )、……、f(x N-k-1 )-f(x N-k )。
Analogize to the above rule, at the etched firstN-1In the stage, the etching selectivity of the etching process becomes k(x 2 ) The cell-to-cell (0,x 1 ) Photoresist at the position is etched, and the area between cells isx n-1 ，x n ) The total thickness of the etched semiconductor material isk(x 2 )[f(x 1 )-f(x 2 )]+…+k(x n )[f(x n-1 )-f(x n )]. Assuming that after etching is finished, the etching is performed between cellsx n-1 ，x n ) The ordinate of the inner semiconductor material surface isg(x n ) There is
。
The derivation process is limited, namelyNIn the case of etching the region to be etched when the surface of the first mask layer 5 is smooth, see fig. 9 to 10, there are
，
Wherein delta isx i =x i -x i-1 ，. Considering the definition of the definite integral, there are
，
g(x) I.e. a function describing the surface topography of the etched structure such as the junction termination extension structure 4,k(x) That is, description when etchingxThe etching selectivity ratio corresponding to the semiconductor material.g(x) Two pairs of sidesxDerivative is provided with
（1）。
The surface morphology of the etched structure can be obtained according to the simulation designg(x) The requirement of (2) can be obtained according to formula (1) to the etch selectivity during the entire etching processk(x) Is not limited.
Illustratively, during the etching, the rate at which the first mask layer 5 is etched is constantrI.e. the thickness of the photoresist consumed per unit time isr. When the machine is in the area to be etchedxThe photoresist thickness at the point is as follows when the semiconductor material is etchedf(x) Thus, the thickness of the photoresist etched and removed is f(x) As shown in fig. 9. Etching process time experienced by the structure in this statetSatisfy the following requirementst=f(x)/rThen there isx=f -1 (tr) Then the formula (1) describing the etching selectivity can be converted into a process timetExpression being variable, i.e.
（2）。
Illustratively, the first mask layer 5 presents a triangle in the XY plane before etching begins, the first mask layer 5 having a height ofHWidth ofLAs shown in fig. 10. The function describing the surface morphology of the first mask layer 5 isf(x)=-(H/L)x+HThere isf '(x)=-H/L，f -1 (y)=L- (L/H)y. According to (2) has
（3）。
Namely, setting the change rule of the etching selection ratio of the etching process program along with time according to the step (3) to obtain the surface morphology functiong(x) The etched structure is described as junction termination extension structure 4.
Illustratively, the regions to be etched are aligned with the main junction 3 in the first direction, and the further the first mask layer 5 is from the main junction 3, the smaller the equivalent etching thickness is. Optionally, a first mask layer 5 of other topography may be provided, which in turn may be provided according to the actual topographyk（t). The etched surface of the region to be etched may, for example, comprise a curved surface or a plane which does not coincide with the surface of the main junction 3. The method provided by the embodiment of the disclosure can realize various surface morphologies more accurately, and has wide adaptability.
Fig. 11 is a schematic diagram of an etching step at the end of the embodiment of the present disclosure. Illustratively, the initial photoresist exhibits a sloped shape with a length ofL=100 μm, height ofH=2.5 μm, the equation describing the shape of the ramp is:
。
the surface of the junction termination extension structure 4 after etching is expected to take on a parabolic shape with a depth ofh=2.5 μm, the equation describing the surface shape of the junction termination extension structure 4 is:
；
thus, there are:
。
illustratively, the law of variation of the etching selectivity is:
。
a typical etching procedure can be selected, and the etching rate of the photoresist is as followsrThe variation rule of the etching selectivity is, therefore, 90 nm/min=0.0015 μm/sk(t)=0.00096tWhereintIn seconds(s). The change law of the etching selectivity can be expressed as a change curve of the etching selectivity shown in fig. 12. As shown in figure 12 of the drawings,k(t) May be diagonal.
The specific implementation of the etch selectivity depends on the type of specific equipment, the etching gas configured, the electrical parameters applied, etc. In an exemplary embodiment, the step of adjusting the etching parameter includes: at least one of gas composition, flow rate, chamber pressure, chamber temperature, electrode bias, and electrode power is adjusted.
Illustratively, the etching is performed using an inductively coupled plasma etching apparatus (ICP) with silicon as the semiconductor material to be etched and photoresist as the material of the first mask layer. The kind of etching gas to be disposed includes Cl 2 、O 2 The electrical parameters that need to be set include ICP power, RF power. Specifically, cl 2 The target etching material of (2) is silicon, and can be used as second etching gas; o (O) 2 The target etching material of (2) is photoresist, and can be used as a first etching gas. By continuously adjusting the flow of the etching gas, the etching rate of the target etching material of the etching gas can be continuously adjusted, and the etching selection ratio can be continuously changed. Taking the change rule of the etching selection ratio set in fig. 12 as an example, the ICP power and the RF power are fixed to typical values, for example, the ICP power is set to 100w to 300w, and the RF power is set to 40w to 80w. FIG. 13 shows a graph of the variation of the gas flow, cl being set according to the law of FIG. 13 2 And O 2 The change rule of the flow can realize the continuously-changed etching selection ratio set in fig. 12.
In some embodimentsIn the first embodiment, the region to be etched may be a pre-doped region 40, and the pre-doped region 40 is etched along the first directionLGreater than or equal to 100 μm.
In other embodiments, the material of the first mask layer may be of another kind having etching selectivity with the material of the area to be etched. When the first mask layer is formed, the first mask layer with variable density can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition and can be matched with other semiconductor processing modes. The equivalent etching thickness of the part with higher density in the first mask layer is larger, and the equivalent etching thickness of the part with lower density is smaller. Illustratively, the equivalent etch thickness of the first mask layer is proportional to the density of the first mask layer.
During etching, the less dense portions will be depleted more quickly, while the more dense portions will be depleted more slowly. The etching morphology of the region to be etched can be further controlled by calculating and controlling the density change.
Fig. 14 illustrates another structure to be etched provided by embodiments of the present disclosure. Illustratively, the etching processing method provided in the embodiment of the present disclosure further includes: a second mask layer 9 is formed covering the pre-doped region 40, the second mask layer 9 being the region to be etched. The step of forming the first mask layer 5 covering the region to be etched includes: a first mask layer 5 is formed overlying the second mask layer 9. The step of etching the region to be etched is then etching the second mask layer 9 through the first mask layer 5.
Illustratively, the step of forming the first mask layer 5 covering the region to be etched comprises: forming a photoresist mask 50 covering the second mask layer 9; the first mask layer 5 is formed based on the photoresist mask 50. The second mask layer 9 may be a hard mask. The material of the second mask layer 9 may comprise silicon oxide.
In the method provided by the embodiment of the disclosure, the etching step of the region to be etched can be applied to etching the second mask layer 9; it may also be used to etch the pre-doped region 40, in which case the etching of the second mask layer 9 may be an etching step performed by means of the first mask layer 5 in a manner such that the etching selectivity is fixed, for example. The etch selectivity may be maintained at a fixed etch rate by maintaining the etch parameters. Illustratively, the material of the pre-doped region 40 comprises silicon carbide.
In some embodiments, the morphology of the second mask layer 9 may be precisely modified by using the etching method provided in the embodiments of the present disclosure, and then passed through SiO 2 The hard mask of material etches the areas of the SiC material to be etched. For example, the working pressure of the etching equipment chamber can be set to be 10mTorr, the bias power is fixed to be 0.5kW, the ICP power can be 2kW, the working temperature can be 5 ℃, and the CF 4 /O 2 The flow rate of the Ar mixture was fixed at 30/30/40sccm. SiC/SiO 2 The etch selectivity of (c) may be 3.5.
In some embodiments, the second mask layer 9 having different equivalent etching thicknesses may be formed first, and then the etching processing method provided in the embodiments of the present disclosure may be used to form the second mask layer by SiO 2 The hard mask of material etches the areas of the SiC material to be etched. By way of example, the operating pressure of the etching apparatus chamber may be set to 10mTorr, the bias power may be 0.5kW, the ICP power may be 2kW, and the operating temperature may be 5 ℃. The etching gas is a mixed gas and can comprise CF 4 、O 2 And Ar. During the etching process, CF may be used 4 Continuously reducing the flow rate from 50sccm to 30sccm, and simultaneously reducing the O 2 The flow rate was continuously reduced from 50sccm to 30sccm. The concentration ratio of the etching gas is continuously changed by adjusting the flow of the etching gas, thereby the SiC/SiO is realized 2 The etch selectivity increases continuously from 2.5 to 3.5. Illustratively, the second etchant gas is other than CF 4 SF may also be selected 6 、C 4 H 8 、CHF 3 Or CF (CF) 4 At least one of them. The variation of the flow rate can be adjusted according to the composition of the etching gas.
Fig. 15 illustrates another structure to be etched provided by an embodiment of the present disclosure. The prefabricated semiconductor structure 1 comprises a main junction 3 and a region to be doped outside the main junction 3. Illustratively, the etching processing method provided in the embodiment of the present disclosure further includes: a second mask layer 9 is formed to cover the region to be doped, the second mask layer 9 being the region to be etched. The step of forming the first mask layer 5 covering the region to be etched includes: a first mask layer 5 is formed overlying the second mask layer 9. The step of etching the region to be etched is then etching the second mask layer 9 through the first mask layer 5. As shown in fig. 15, the portion of the first mask layer 5 closer to the main junction 3 in the X-axis direction may be thinner, and the portion farther from the main junction 3 may be thicker.
Fig. 16 illustrates the semiconductor structure after etching the second mask layer in an embodiment of the present disclosure. As shown in fig. 15, by controlling the etching selectivity of the first mask layer 5 and the second mask layer 9, the top surface of the etched second mask layer 90 has a desired morphology. The overall thickness of the etched second mask layer 90 may be controlled according to parameters of a subsequent ion implantation process, such as implantation depth.
Fig. 17 shows a semiconductor structure after ion implantation in an embodiment of the disclosure. The junction termination extension structure 4 is obtained after ion implantation using the etched second mask layer 90 as an implantation mask. The etched second mask layer 90 may then be removed. The portion of the junction termination extension structure 4 closer to the main junction 3 may have a higher doping concentration due to the blocking of the implantation mask, the portion farther from the main junction 3 may have a lower doping concentration, and the concentration variation of the junction termination extension structure 4 approaches an ideal state.
Illustratively, the presently disclosed embodiments provide a method for fabricating a semiconductor device, the method comprising performing the foregoing etching of the second mask layer 9; then, ion implantation is carried out by taking the etched second mask layer 90 as an implantation mask; illustratively, the mask is removed through the implantation process. The method can realize the semiconductor device with complete shape and ideal doping concentration distribution. The method etches the implantation mask layer, so that damage to the semiconductor structure can be reduced, and meanwhile, the cleaning step when the mask layer is removed can be reduced.
In some embodiments, the step of forming the second mask layer 9 may include forming a hard mask having varying density. Taking a hard mask made of a silicon oxide material as an example, in the growth process of the silicon oxide, the bonding mode of the silicon oxide can be influenced by controlling the components of the growth gas, so that the density of the silicon oxide after the growth is controlled. When the densities of the silicon oxides are different, the etching rates of the silicon oxides under the same etching parameters are also different. Illustratively, with such a hard mask ultimately serving as a mask, the etch selectivity to the region to be etched is also different during etching.
Alternatively, the flow of the controllable silane may be 120sccm, N, in growing the hard mask of silicon oxide material 2 The O flow rate may be 70sccm and the Ar flow rate may be 100sccm. The hard mask formed in this step may have an etch rate of 0.35nm/s under the etching conditions described below, including: the etching equipment chamber has an operating pressure of 10mTorr, a bias power of 0.5kW, an ICP power of 2kW, an operating temperature of 5 ℃, and a CF 4 /O 2 The flow rate of the Ar mixture was fixed at 30/30/40sccm.
Alternatively, the flow of controllable silane may be 100sccm, N, in growing a hard mask of silicon oxide material 2 The O flow rate may be 90sccm and the Ar flow rate may be 100sccm. The second mask layer 9 formed in this step may have an etching rate of 0.3nm/s under the etching conditions described in the previous paragraph.
In some embodiments, a hardmask of varying density may be formed by adjusting the ratio of the different components in the growth gas. The ratio can be continuously adjusted to form a hard mask with continuously graded density. The concentration ratio of the component gases can be changed by adjusting the flow rates of the different component gases.
Illustratively, the silane gas flow may be continuously adjusted from 120sccm to 100sccm during the hard mask growth process, e.g., may be linearly adjusted; simultaneously, the gas flow of nitrogen dioxide can be continuously adjusted from 70sccm to 90sccm; for example, the flow rate of Ar may be kept stable. The hard mask thus formed may exhibit a continuous gradual change in etch rate from 0.35nm/s to 0.3nm/s from bottom to top at various locations thereof as it is etched. The hard mask, when applied to the method provided by the embodiments of the present disclosure, exhibits an etch selectivity that varies depending on the depth position to which it is exposed.
Illustratively, when etching a hard mask with a gradual change in density, or when etching with a hard mask with a gradual change in density, component concentration adjustment of etching gas is approved to achieve a precise and sensitive etching effect.
The embodiment of the disclosure also provides a semiconductor device. In some embodiments, a semiconductor device includes: main junction and junction termination extension structure. The junction termination extension structures are aligned with the main junction along a first direction. The junction termination extension structure may be formed by the aforementioned etching process.
Fig. 18 shows an etching processing apparatus provided by an embodiment of the present disclosure. In some embodiments, the etching processing apparatus 100 may include: a first processing unit 101, a second processing unit 102, and a control unit 103.
The first processing unit 101 may be configured to: the first mask layer is used for forming a first mask layer covering the area to be etched, and the first mask layer has different equivalent etching thicknesses along the position parallel to the first direction of the area to be etched. Illustratively, the first processing unit 101 may be used to form a graded hard mask that may control the flow of different components of the growth gas.
The second processing unit 102 may be configured to: and the etching device is used for etching the region to be etched through the first mask layer and etching the first mask layer. For example, the second processing unit 102 may utilize a mixed etching gas and may control the flow rate of each gas component.
The control unit 103 may be configured to: and continuously adjusting the etching selection ratio of the first mask layer and the region to be etched by continuously adjusting the etching parameters. The etching parameters comprise the concentration ratio of the first etching gas to the second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the area to be etched.
In other embodiments, the control unit 103 may be further configured to: the etching parameters are maintained to maintain the etching selectivity.
The technical features of the embodiments disclosed above may be combined in any way, and for brevity, all of the possible combinations of the technical features of the embodiments described above are not described, however, they should be considered as the scope of the description provided in this specification as long as there is no contradiction between the combinations of the technical features.
In the embodiments disclosed above, the order of execution of the steps is not limited, and may be performed in parallel, or performed in a different order, unless explicitly stated and defined otherwise. The sub-steps of the steps may also be performed in an interleaved manner. Various forms of procedures described above may be used, and steps may be reordered, added, or deleted as long as the desired results of the technical solutions provided by the embodiments of the present disclosure are achieved, which are not limited herein.
The above disclosed examples represent only a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the invention as claimed. The scope of the invention should, therefore, be determined with reference to the appended claims.
Claims (10)
1. The etching processing method comprises the following steps:
forming a first mask layer covering a region to be etched, wherein the first mask layer has different equivalent etching thicknesses along the first direction parallel to the region to be etched; a kind of electronic device with high-pressure air-conditioning system
Etching the region to be etched through the first mask layer, and etching the first mask layer,
the method is characterized in that the etching step comprises the following steps: continuously adjusting etching parameters to continuously adjust the etching selection ratio of the first mask layer to the region to be etched so that the surface of the region to be etched formed by the etching comprises a curved surface,
the etching parameters comprise the concentration ratio of a first etching gas to a second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the area to be etched.
2. The etch processing method of claim 1, wherein the equivalent etch thickness is proportional to a geometric thickness of the first mask layer or is proportional to a density of the first mask layer.
3. The etching processing method according to claim 1, wherein the step of forming the first mask layer comprises:
forming a photoresist mask with uniform geometric thickness; a kind of electronic device with high-pressure air-conditioning system
And baking the different positions of the photoresist mask in different modes to form the first mask layer with uneven geometric thickness.
4. The etching processing method according to claim 1, wherein the step of forming the first mask layer comprises:
forming a photoresist mask with uniform geometric thickness;
photoetching the photoresist mask through a photoetching plate with a gradual change pattern, wherein the light-transmitting parts and the light-non-transmitting parts at different positions of the gradual change pattern along the first direction have different proportions; a kind of electronic device with high-pressure air-conditioning system
And developing the photoresist mask subjected to the photoetching.
5. The etching processing method according to claim 1, wherein the step of forming the first mask layer comprises:
forming a photoresist mask with uniform geometric thickness;
performing a laser direct writing exposure process on the photoresist mask, wherein laser with different exposure doses is irradiated at different positions corresponding to the photoresist mask; a kind of electronic device with high-pressure air-conditioning system
And developing the photoresist mask subjected to the laser direct-write exposure process.
6. The etching processing method according to any one of claims 1 to 5, wherein the region to be etched is a pre-doped region, a material of the pre-doped region including silicon carbide, a length of the pre-doped region etched in the first direction being greater than or equal to 100 μm;
the step of adjusting the etching parameters comprises the following steps: adjusting at least one of gas composition, flow rate, chamber pressure, chamber temperature, electrode bias, and electrode power;
the region to be etched and the main junction are arranged along the first direction, and the position of the first mask layer, which is far away from the main junction, is provided with smaller equivalent etching thickness.
7. The etching processing method according to any one of claims 1 to 5, further comprising: forming a second mask layer covering the prefabricated doped region, wherein the second mask layer is the region to be etched, and the doped region comprises silicon carbide;
the step of forming the first mask layer covering the area to be etched comprises the following steps: a first mask layer is formed overlying the second mask layer.
8. The etching processing method according to any one of claims 1 to 5, further comprising: forming a second mask layer covering a region to be doped, wherein the second mask layer is the region to be etched, and the material of the region to be doped comprises silicon carbide; a kind of electronic device with high-pressure air-conditioning system
Taking the etched second mask layer as an implantation mask, and performing ion implantation on the region to be doped;
the step of forming the first mask layer covering the area to be etched comprises the following steps: a first mask layer is formed overlying the second mask layer.
9. An etching processing apparatus comprising:
a first processing unit configured to: the method comprises the steps of forming a first mask layer for covering a region to be etched, wherein the first mask layer has different equivalent etching thicknesses along a first direction parallel to the region to be etched;
a second processing unit configured to: the etching device is used for etching the region to be etched through the first mask layer and etching the first mask layer; and
it is characterized in that the method comprises the steps of,
a control unit configured to: and continuously adjusting the etching selection ratio of the first mask layer to the region to be etched by continuously adjusting etching parameters so that the surface formed by the region to be etched through etching comprises a curved surface, wherein the etching parameters comprise the concentration ratio of first etching gas to second etching gas, the first etching gas is used for etching the first mask layer, and the second etching gas is used for etching the region to be etched.
10. A semiconductor device, comprising:
a main junction; a kind of electronic device with high-pressure air-conditioning system
A junction termination extension structure aligned with the main junction along a first direction,
characterized in that the junction termination extension is formed by the etching processing method according to any one of claims 1 to 8.
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