CN115862513A - Shift register and driving method thereof, scanning driving circuit and display panel - Google Patents
Shift register and driving method thereof, scanning driving circuit and display panel Download PDFInfo
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Abstract
The embodiment of the application provides a shift register, a driving method thereof, a scanning driving circuit and a display panel, and relates to the technical field of display panels. The shift register includes: the first output module responds to the conduction level of the first node and transmits a first level voltage signal to the output end of the shift register; the second output module responds to the conduction level of the second node and transmits a second level voltage signal to the output end of the shift register; when the first level voltage signal output stage is switched to the second level voltage signal output stage, the third output module responds to the conducting level of the third node and transmits the second level voltage signal to the output end of the shift register. According to the embodiment of the application, the tailing problem of the output level of the shift register can be effectively improved, so that the performance of the display panel is better improved, and the display effect and the competitiveness of the display panel are improved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a shift register, a driving method thereof, a scanning driving circuit and a display panel.
Background
In the field of display panel technology, in order to implement a scan display or other functions, it is often necessary to provide a level signal to a pixel circuit by using a shift register. However, when the shift register works, the corresponding switch module is often not completely turned on, so that the level transmitted to the output end of the shift register does not reach the target voltage, a tailing phenomenon is generated, and the display effect of the display panel is further affected.
Disclosure of Invention
The embodiment of the application provides a shift register, a driving method thereof, a scanning driving circuit and a display panel, and can effectively improve the trailing problem of the output level of the shift register.
In a first aspect, an embodiment of the present application provides a shift register, including:
the first output module is electrically connected with the first node at a control end, electrically connected with the first level voltage end at a first end and electrically connected with the output end of the shift register at a second end, and used for responding to the conduction level of the first node and transmitting a first level voltage signal of the first level voltage end to the output end of the shift register;
the control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the output end of the shift register, and the second end of the second output module is electrically connected with the second level voltage end and used for responding to the conduction level of the second node and transmitting a second level voltage signal of the second level voltage end to the output end of the shift register;
a control end of the third output module is electrically connected with the third node, a first end of the third output module is electrically connected with the output end of the shift register, and a second end of the third output module is electrically connected with the second level voltage end;
the first end of the first coupling module is electrically connected with the third node, and the second end of the first coupling module is electrically connected with the first end of the third output module;
when the first level voltage signal output stage is switched to the second level voltage signal output stage, the third output module responds to the conducting level of the third node and transmits a second level voltage signal of the second level voltage end to the output end of the shift register.
In a second aspect, an embodiment of the present application provides a driving method of a shift register, which is applied to the shift register provided in the implementation manner of the first aspect of the present application, and the driving method includes:
when the first level voltage signal output stage is switched to the second level voltage signal output stage, a conduction level is provided for the third node, so that the third output module responds to the conduction level of the third node and transmits a second level voltage signal of the second level voltage end to the output end of the shift register.
In a third aspect, embodiments of the present application provide a scan driving circuit, where the scan driving circuit includes a plurality of cascaded shift registers as provided in the embodiments of the first aspect of the present application.
In a fourth aspect, the present application provides a display panel, which is characterized by including the scan driving circuit as provided in the third aspect of the present application.
In a fifth aspect, embodiments of the present application provide a display device including a display panel as provided in the fourth aspect of the present application.
The embodiment of the application provides a shift register and a driving method thereof, a scanning driving circuit and a display panel, and aims to solve the problem of output tailing generated due to the fact that a second output module cannot be completely conducted in the existing shift register. Therefore, the output tailing phenomenon caused by the fact that the second output module cannot be completely conducted can be avoided, the tailing problem of the output level of the shift register can be effectively improved, the performance of the display panel is better improved, and the display effect and the competitiveness of the display panel are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
fig. 2 is another circuit schematic diagram of a shift register according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a shift register according to an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
fig. 6 is a schematic circuit diagram of a shift register according to an embodiment of the present application;
FIG. 7 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
FIG. 8 is a timing diagram of the shift register of FIG. 7;
fig. 9 is a schematic flowchart of a driving method of a shift register according to an embodiment of the present application;
fig. 10 is a schematic flowchart of another driving method of a shift register according to an embodiment of the present application;
fig. 11 is a schematic flowchart of a driving method of a shift register according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The transistors in the embodiments of the present application may be N-type transistors or P-type transistors. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.
In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.
In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience of describing a circuit structure, and the first node, the second node, and the third node are not an actual circuit unit.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.
Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the related art:
as described above, the inventors of the present application have found that, during the operation of the shift register, the threshold voltages of the transistors for controlling the output are different due to the circuit characteristics of the conventional shift register. Therefore, the output transistor cannot be completely turned on, so that the level transmitted to the output end of the shift register cannot reach the target voltage, and the output level of the shift register is trailing.
In view of the above research of the inventor, the embodiments of the present application provide a shift register, a driving method thereof, a scan driving circuit, and a display panel, which can effectively solve the technical problem of shift register output level tailing existing in the related art. First, a shift register provided in an embodiment of the present application will be described.
Fig. 1 is a circuit schematic diagram of a shift register according to an embodiment of the present disclosure. As shown in fig. 1, the shift register 10 may specifically include a first output module 101, a second output module 102, a third output module 103, and a first coupling module 104. The first output module 101 has a control terminal electrically connected to the first node N1, a first terminal electrically connected to the first level voltage terminal VGH, and a second terminal electrically connected to the output terminal OUT of the shift register. The second output module 102 has a control terminal electrically connected to the second node N2, a first terminal electrically connected to the output terminal OUT of the shift register, and a second terminal electrically connected to the second level voltage terminal VGL. The control terminal of the third output module 103 is electrically connected to the third node N3, the first terminal thereof is electrically connected to the output terminal OUT of the shift register, and the second terminal thereof is electrically connected to the second level voltage terminal VGL. A first coupling module 104, wherein a first end of the first coupling module 104 is electrically connected to the third node N3, and a second end of the first coupling module 104 is electrically connected to a first end of the third output module 103. The second terminal of the digital driving module 103 may be understood as an output terminal of the driving current of the digital driving module 103. For example, the first output module 101, the second output module 102, and the third output module 103 may be transistors, and the control terminals thereof may be gates of the transistors.
During the specific operation of the shift register 10, the first output module 101 may transmit the first level voltage signal of the first level voltage terminal VGH to the shift register output terminal OUT in response to the on level of the first node N1. The second output module 102 may transmit the second level voltage signal of the second level voltage terminal VGL to the shift register output terminal OUT in response to the on level of the second node N2.
When the first level voltage signal output stage is switched to the second level voltage signal output stage, the first coupling module 104 couples and pulls down the node potential of the third node N3 under the influence of the second level voltage signal output by the output end OUT of the shift register. In this way, the third output module 103 is turned on in response to the turn-on level of the third node N3, thereby transmitting the second level voltage signal of the second level voltage terminal VGL to the shift register output terminal OUT, so that the shift register output terminal OUT outputs the stable second level voltage signal without tailing.
It should be noted that, in the present application, the first level voltage signal of the first level voltage terminal VHG is at an off level, and the second level voltage signal provided by the second level voltage terminal VGL is at an on level.
The embodiment of the application provides a shift register 10, and aims at the problem of output tailing caused by the fact that a second output module 102 cannot be completely conducted in the existing shift register, a first coupling module 104 and a third output module 103 are additionally arranged in the shift register, when a first level voltage signal output stage is switched to a second level voltage signal output stage, the potential of a third node N3 is coupled and pulled down through the first coupling module 104, the third output module 103 is conducted in response to the conduction level of the third node N3 with lower potential, a second level voltage signal of a second level voltage end VGL can be well transmitted to an output end OUT of the shift register, and the tailing problem when the second level voltage signal is output is effectively improved. Therefore, the output tailing phenomenon caused by the fact that the second output module 102 cannot be completely conducted can be avoided, the tailing problem of the output level of the shift register can be effectively solved, the performance of the display panel is better improved, and the display effect and the competitiveness of the display panel are improved.
Referring to fig. 2, fig. 2 is another circuit schematic diagram of a shift register according to an embodiment of the present disclosure. In some more specific embodiments, as shown in fig. 2, optionally, in order to ensure that the respective node potentials of the second node N2 and the third node N3 are stable, the shift register 10 may further include:
the control terminal of the first switch module 105 is electrically connected to the second level voltage terminal VGL, the first terminal thereof is electrically connected to the second node N2, and the second terminal thereof is electrically connected to the third node N3.
In this embodiment, the first switch module 104 is disposed between the second node N2 and the third node N3, and the first switch module 104 is continuously turned on under the action of the second level voltage signal of the second level voltage terminal VGL, so as to maintain the normally-open state. The normally-open first switch module 104 plays a role of blocking the potential between the second node N2 and the third node N3, so that it can be ensured that the respective node potentials of the second node N2 and the third node N3 are kept unchanged in a low-voltage state.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure. As shown in fig. 3, in some more specific embodiments, optionally, the shift register 10 may further include:
in the first memory module 106, a first terminal of the first memory module 106 may be electrically connected to the second node N2, and a second terminal of the first memory module 106 may be electrically connected to the first clock signal terminal XCK.
Specifically, the first clock signal terminal XCK outputs a high level voltage signal when the first level voltage signal output stage is switched to the second level voltage signal output stage. At this time, for the bootstrap coupling of the second output module 102, since the second node is connected to the first storage module 106 at the same time, the second node N2 is not pulled down to the second level voltage signal lower than the second level voltage terminal VGL, there is no voltage difference between the control terminal and the first terminal of the second output module 102, and the second output module 102 is not turned on finally.
Additionally, in the subsequent second level voltage signal output stage, when the second output module 102 needs to be turned on to transmit the second level voltage signal of the second level voltage terminal VGL to the output terminal OUT of the shift register, the first clock signal terminal XCK goes low to output a low level voltage signal. At this time, the first memory module 106 will pull down the node potential of the second node N2 under the influence of the output level of the first clock signal terminal XCK, so that the second output module 102 is turned on under the control of the on level of the second node N2, and transmits the second level voltage signal of the second level voltage terminal VGL to the output terminal OUT of the shift register.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a shift register according to another embodiment of the present disclosure. In some more specific embodiments, as shown in fig. 4, optionally, in order to more reasonably realize the control of the output level of the shift register, the shift register 10 may further include:
the control terminal of the first input module 107 is electrically connected to the second clock signal terminal CK, the first terminal thereof is electrically connected to the shift register input terminal IN, and the second terminal thereof is electrically connected to the second node N2.
Specifically, when the first level voltage signal output stage is switched to the second level voltage signal output stage, the second clock signal terminal CK provides a conducting level, the first input module 107 is conducted under the control of the second clock signal terminal CK, so that the low level voltage signal at the input terminal IN of the shift register is written into the second node N2, and the first switch module 105 transmits the low level voltage signal at the second node N2 to the third node N3.
Since the shift register output end OUT outputs the first level voltage signal at the time before the first level voltage signal output stage is switched to the second level voltage signal output stage, the first level voltage signal is at the cut-off level, that is, the first ends of the second output module 102 and the third output module 103 are at the cut-off level. Therefore, at this time, a voltage difference exists between the control terminal and the first terminal of the second output module 102, a voltage difference exists between the control terminal and the first terminal of the third output module 103, the second output module 102 and the third output module 103 are turned on for a short time, the second level voltage signal of the second level voltage terminal VGL is transmitted to the output terminal OUT of the shift register, and the level signal output by the output terminal OUT of the shift register is switched from the first level voltage signal to the second level voltage signal.
After the level signal output by the output terminal OUT of the shift register is switched from the first level voltage signal to the second level voltage signal, the second terminal of the first coupling module 104 is influenced by the potential of the first terminal of the third output module 103 (the output level of the output terminal OUT of the shift register), and the potential coupling of the third node N3 is pulled down. Finally, the node of the third node N3 is pulled down to be lower than the second level voltage signal, the third output module 103 is turned on under the control of the on level of the third node N3, and transmits the second level voltage signal of the second level voltage terminal VGL to the output terminal OUT of the shift register, so that the output terminal OUT of the shift register outputs the stable second level voltage signal without tailing.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure. As shown in fig. 5, in some more specific embodiments, optionally, the first output module 101 may include a first transistor T1, the second output module 102 may include a second transistor T2, the third output module 103 may include a third transistor T3, the first coupling module 104 may include a first coupling capacitor C1, and the first switch module 105 may include a fourth transistor T4, where:
the gate of the first transistor T1 is electrically connected to the first node N1, the first pole of the first transistor T1 is electrically connected to the first level voltage terminal VGH, and the second pole of the first transistor T1 is electrically connected to the shift register output terminal OUT.
The gate of the second transistor T2 is electrically connected to the second node N2, the first pole of the second transistor T2 is electrically connected to the output terminal OUT of the shift register, and the second pole of the second transistor T2 is electrically connected to the second level voltage terminal VGL.
A gate electrode of the third transistor T3 is electrically connected to the third node N3, a first electrode of the third transistor T3 is electrically connected to the shift register output terminal OUT, and a second electrode of the third transistor T3 is electrically connected to the second level voltage terminal VGL.
A first plate of the first coupling capacitor C1 is electrically connected to the third node N3, and a second plate of the first coupling capacitor C1 is electrically connected to a first electrode of the third transistor T3.
A gate of the fourth transistor T4 is electrically connected to the second level voltage terminal VGL, a first pole of the fourth transistor T4 is electrically connected to the second node N2, and a second pole of the fourth transistor T4 is electrically connected to the third node N3.
In a specific implementation, during the operation of the shift register 10, the first transistor T1 responds to the conducting level of the first node N1 to transmit the first level voltage signal of the first level voltage terminal VGH to the output terminal OUT of the shift register. The second transistor T2 transmits the second level voltage signal of the second level voltage terminal VGL to the shift register output terminal OUT in response to the turn-on level of the second node N2.
When the first level voltage signal output stage is switched to the second level voltage signal output stage, the first plate of the first coupling capacitor C1 is affected by the second level voltage signal output by the output end OUT of the shift register, and the node potential of the third node N3 electrically connected with the second plate of the first coupling capacitor C1 is coupled and pulled down to the second level voltage signal. Thus, the third transistor T3 is turned on under the control of the on level of the third node N3, and transmits the second level voltage signal of the second level voltage terminal VGL to the shift register output terminal OUT. Meanwhile, the fourth transistor T4, as a normally-on transistor, plays a role in blocking voltage between the second node N2 and the third node N3, and separates the low potential connection between the second node N2 and the third node N3, so that the potential of the third node N3 is not affected by the potential of the second node N2, and is kept in a state lower than the second level voltage signal under the bootstrap coupling effect of the first coupling capacitor C1.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure. In some more specific embodiments, as shown in fig. 6, the shift register 10 may further include a second output module 108, a third input module 109, a second storage module 110, and a second switch module 111.
Specifically, a first control terminal of the second input module 108 is electrically connected to the first clock signal terminal XCK, a second control terminal of the second input module 108 is electrically connected to the fourth node N4, a first terminal of the second input module 108 is electrically connected to the second node N2, and a second terminal of the second input module 108 is electrically connected to the first voltage level terminal.
The third input module 109 is electrically connected to the first node N1, the second node N2, the fourth node N4, the first voltage level terminal, the second voltage level terminal, the first clock signal terminal XCK, and the second clock signal terminal CK, and is configured to adjust potentials of the first node N1 and the fourth node N4.
And a second memory module 110, wherein a first end of the second memory module 110 is electrically connected to the fourth node N4.
A control terminal of the second switch module 111 is electrically connected to the first clock signal terminal XCK, a first terminal of the second switch module 111 is electrically connected to a second terminal of the second storage module 110, and a second terminal of the second switch module 111 is electrically connected to the first node N1.
Referring to fig. 7, fig. 7 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure. As shown in fig. 7, in some more specific embodiments, optionally, in some possible embodiments, the second input module 108 may further include a fifth transistor T5 and a sixth transistor T6, the third input module 109 may further include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10, the second storage module 110 may include a second storage capacitor C3, and the second switch module 111 may include an eleventh transistor T11.
Specifically, the gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first pole of the fifth transistor T5 is electrically connected to the first level voltage terminal VGH, and the second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. A gate of the sixth transistor T6 is electrically connected to the first clock signal terminal XCK, and a second pole of the sixth transistor T6 is electrically connected to the second node N2. A gate of the seventh transistor T7 is electrically connected to the second node N2, a first electrode of the seventh transistor T7 is electrically connected to the first voltage level terminal, and a second electrode of the seventh transistor T7 is electrically connected to the first node N1. A gate of the eighth transistor T8 is electrically connected to the fourth node N4, a first electrode of the eighth transistor T8 is electrically connected to the second electrode of the second storage capacitor C3, and a second electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal XCK. A gate of the ninth transistor T9 is electrically connected to the second node N2, a first pole of the ninth transistor T9 is electrically connected to the fourth node N4, and a second pole of the ninth transistor T9 is electrically connected to the second clock signal terminal CK. A gate of the tenth transistor T10 is electrically connected to the second clock signal terminal CK, a first pole of the tenth transistor T10 is electrically connected to the fourth node N4, and a second pole of the tenth transistor T10 is electrically connected to the second level voltage terminal VGL. A first plate of the second storage capacitor C3 is electrically connected to the fourth node N4, and a second plate of the second storage capacitor C3 is electrically connected to a first electrode of the eleventh transistor T11. A gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal XCK, and a second pole of the eleventh transistor T11 is electrically connected to the first node N1.
In order to facilitate understanding of the shift register provided in the present application, the following description is made in conjunction with some specific application embodiments.
With continued reference to fig. 9, according to some embodiments of the present application, optionally, in the shift register 10 provided in this embodiment, in addition to the fifth transistor T5 and the sixth transistor T6 included in the second input module 108 and the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 included in the third input module 109 in the above embodiments, the second storage capacitor C3 included in the second storage module 110, and the eleventh transistor T11 included in the second switch module 111, in the shift register 10 of the present application, the first output module 101 may include the first transistor T1, the second output module 102 includes the second transistor T2, the third output module 103 includes the third transistor T3, the first coupling module 104 includes the first coupling capacitor C1, the first switch module 105 includes the fourth transistor T4, the first storage module 106 includes the first storage capacitor C2, and the first input module 107 includes the twelfth transistor T12. The specific connection relationship between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first coupling capacitor C1 can be similar to the connection relationship shown in fig. 5, which is not described in detail herein.
The first plate of the first storage capacitor C2 is electrically connected to the second node N2, and the second plate of the first storage capacitor C2 is electrically connected to the first clock signal terminal XCK. The gate of the twelfth transistor T12 is electrically connected to the second clock signal terminal CK, the first pole of the twelfth transistor T12 is electrically connected to the second node N2, and the second pole of the twelfth transistor T12 is electrically connected to the shift register output terminal IN. In the present embodiment, the transistors may be P-type transistors, but in other embodiments, the channel types of the transistors may be flexibly adjusted according to actual requirements, and the present application does not specifically limit the channel types.
It should be added that, in order to better maintain the node potential of the first node N1 stable, so as to further ensure the stable output of the shift register output terminal OUT, as shown in fig. 7, a third memory module C4 may be further included in fig. 7, a first plate of the third memory module C4 is electrically connected to the first level voltage terminal VGH, and a second plate of the third memory module C4 is electrically connected to the first node N1.
FIG. 8 is a timing diagram of the shift register shown in FIG. 7. The shift register shown in fig. 7 will be described with reference to the timing shown in fig. 8. It should be noted that the driving timing sequence given in the embodiment of the present application is only one possible example, and in other embodiments, the operation timing sequence of the shift register may also be flexibly adjusted according to practical situations and requirements, which is not specifically limited herein.
The operation of the shift register of fig. 11 as a whole can be divided into a first level voltage signal output stage and a second level voltage signal output stage. In this example, in a case where the transistors are all P-type transistors, the first level voltage signal may be at an off level, specifically, a high level, and the second level voltage signal may be at an on level, specifically, a low level.
The following description focuses on the main periods in the high level output stage and the low level output stage shown in fig. 8, respectively.
In the T2 period, the second clock signal terminal CK is hopped low, the tenth transistor T10, the twelfth transistor T12 are turned on under the control of the second clock signal terminal CK, the low level of the second level voltage terminal VGL is transmitted to the fourth node N4 through the tenth transistor T10, and the fifth transistor T5 and the eighth transistor T8 are turned on under the control of the fourth node N4. The input terminal IN of the shift register outputs a high level, the high level provided by the input terminal IN of the shift register is transmitted to the second node N2 through the turned-on twelfth transistor T12, and is transmitted to the third node N3 by the normally-on fourth transistor T4, and the second transistor T2 and the third transistor T3 are turned off. The first clock signal terminal XCK outputs a high level at this stage, the eleventh transistor T11 is turned off, the first node N1 maintains the high level at the previous time, the first transistor T1 is turned off, and the output terminal OUT of the shift register maintains the low level at the previous time.
In the T3 period, the second clock signal terminal CK outputs a high level, and the tenth and twelfth transistors T10 and T12 are turned off under the control of the second clock signal terminal CK. The fourth node N4 maintains a low level and the fifth and eighth transistors T5 and T8 are turned on. The first clock signal terminal XCK is turned off, the sixth transistor T6 and the eleventh transistor T11 are turned on, the high level of the first level voltage terminal VGH is transmitted to the second node N2 by the turned-on fifth transistor T5 and the turned-on sixth transistor T6, and is transmitted to the third node N3 by the normally-on fourth transistor T4, and the second transistor T2 and the third transistor T3 are turned off. The low level of the first clock signal terminal XCK is transmitted to the first node N1 through the turned-on eighth transistor T8 and the turned-on eleventh transistor T11, the first transistor T1 is turned on, the high level of the first level voltage terminal VGH is transmitted to the shift register output terminal OUT, and the shift register output terminal OUT outputs the high level.
In the T4 period, the second clock signal terminal CK is hopped low, the tenth transistor T10 and the twelfth transistor T12 are turned on under the control of the second clock signal terminal CK, the low level of the second level voltage terminal VGL is transmitted to the fourth node N4 through the tenth transistor T10, and the fifth transistor T5 and the eighth transistor T8 are turned on under the control of the fourth node N4. The input terminal IN of the shift register outputs a high level, the high level provided by the input terminal IN of the shift register is transmitted to the second node N2 through the turned-on twelfth transistor T12, and is transmitted to the third node N3 by the normally-on fourth transistor T4, and the second transistor T2 and the third transistor T3 are turned off. The first clock signal terminal XCK outputs a high level at this stage, the eleventh transistor T11 is turned off, the first node N1 maintains a low level at the previous time, the first transistor T1 is turned off, and the output terminal OUT of the shift register maintains a high level at the previous time.
IN the T5 period, the shift register input terminal IN outputs a low level, the second clock signal terminal CK outputs a high level, and the tenth and twelfth transistors T10 and T12 are turned off under the control of the second clock signal terminal CK. The fourth node N4 maintains a low level and the fifth and eighth transistors T5 and T8 are turned on. The first clock signal terminal XCK goes low, and the sixth transistor T6 and the eleventh transistor T11 are turned on. The high level of the first level voltage terminal VGH is transmitted to the second node N2 by the turned-on fifth transistor T5 and the turned-on sixth transistor T6, and is transmitted to the third node N3 by the normally-on fourth transistor T4, and the second transistor T2 and the third transistor T3 are turned off. The low level of the first clock signal terminal XCK is transmitted to the first node N1 through the turned-on eighth transistor T8 and the turned-on eleventh transistor T11, the first transistor T1 is turned on, the high level of the first level voltage terminal VGH is transmitted to the shift register output terminal OUT, and the shift register output terminal OUT outputs the high level.
IN the period T6, the shift register input terminal IN outputs a low level, the second clock signal terminal CK is stepped low, the tenth transistor T10 and the twelfth transistor T12 are turned on under the control of the second clock signal terminal CK, a low level of the second level voltage terminal VGL is transmitted to the fourth node N4 through the tenth transistor T10, and the fifth transistor T5 and the eighth transistor T8 are turned on under the control of the fourth node N4. The low level outputted from the input terminal IN of the shift register is transmitted to the second node N2 through the turned-on twelfth transistor T12, and is transmitted to the third node N3 through the normally-on fourth transistor T4. At this time, since the output of the output terminal OUT of the shift register is at the high level at the previous time, a voltage difference exists between the gates and the first poles of the second transistor T2 and the third transistor T3 at this time, the second transistor T2 and the third transistor T3 are turned on for a short time, the low level of the second level voltage terminal VGL is transmitted to the output terminal OUT of the shift register, and the potential of the output terminal OUT of the shift register is reduced. The potential of the output end OUT of the shift register is reduced, the first polar plate of the first coupling capacitor C1 pulls down the node potential of a third node N3 electrically connected with the second polar plate of the first coupling capacitor C1 to a low level lower than the second level voltage end VGL under the influence of the potential of the output end OUT of the shift register, finally the third transistor T3 is conducted, the low level of the second level voltage end VGL is transmitted to the input end OUT of the shift register, and the output end OUT of the shift register outputs a stable low level signal without tailing.
For the influence of the bootstrap coupling of the second transistor T2 on the second node N2, IN this embodiment, the second node N2 is simultaneously connected to the first storage capacitor C2, and the first clock signal terminal XCK electrically connected to the second electrode of the first storage capacitor C2 outputs a high level, so that the node potential of the first node N1 maintains the low level output by the input terminal IN of the shift register under the action of the first storage capacitor C1, and there is no voltage difference between the gate and the first electrode of the second transistor T2, so that the second transistor T2 is turned off IN this period, and a low level with tailing is not output, thereby affecting the display effect of the display panel.
IN the period T7, the shift register input terminal IN outputs a low level, the second clock signal terminal CK outputs a high level, and the tenth and twelfth transistors T10 and T12 are turned off under the control of the second clock signal terminal CK. The fourth node N4 maintains a low level and the fifth and eighth transistors T5 and T8 are turned on. The first clock signal terminal XCK goes low, and the sixth transistor T6 and the eleventh transistor T11 are turned on. The second plate of the first storage capacitor C2 pulls down the node potential coupling of the second node N2 electrically connected to the first plate under the influence of the first clock signal terminal XCK jumping low, the node potential of the second node N2 is much lower than the low level output by the shift register output terminal OUT (the first storage capacitor C1 may be a large capacitor), at this time, the second transistor T2 is turned on, the low level output by the second level voltage terminal VGL is transmitted to the shift register output terminal OUT, and the shift register output terminal OUT outputs the low level.
Meanwhile, the third transistor T3 continues to be turned on under the coupling effect of the first coupling capacitor C1, but the first coupling capacitor C1 is continuously discharged, so that the coupling pull-down effect of the first coupling capacitor C1 on the node potential of the third node N3 is gradually weakened, the node potential of the third node N3 gradually rises, and the voltage difference between the node potential of the third node N3 and the low level output by the output terminal OUT of the shift register is gradually reduced thereafter. However, in the low level output stage after the time period T6, the second transistor T2 is mainly responsible for transmitting the low level of the second level voltage terminal VGL to the shift register output terminal OUT, and therefore, the change of the node potential of the third node N3 does not affect the low level output of the shift register output terminal OUT after the time period T6.
In this embodiment, compared to the conventional shift register, the shift register 10 has a first coupling capacitor C1 and a third transistor T3 additionally disposed at the second node N2. Thus, when the high level output stage is switched to the low level output stage, the first coupling capacitor C1 can pull down the potential coupling of the third node N3. The third transistor T3 is turned on in response to the turn-on level of the third node N3, and transmits the low level of the second level voltage terminal VGL to the shift register output terminal OUT.
The shift register 10 of the embodiment of the application avoids the output tailing phenomenon caused by the fact that the second transistor T2 cannot be completely conducted at the initial output stage of the falling edge in the existing shift register, and can effectively improve the tailing problem of the output level of the shift register, thereby better improving the performance of a display panel and promoting the display effect and competitiveness of the display panel.
It should be noted that, besides the transistors listed above, the shift register 10 of the present application may also include other transistors, which together form a plurality of types of shift registers, and the present application does not specifically limit this.
Based on the same inventive concept, correspondingly, the application also provides a driving method of the shift register, which is applied to the shift register provided by any of the above embodiments of the application. Referring to fig. 9, fig. 9 is a schematic flowchart illustrating a driving method of a shift register according to an embodiment of the present disclosure.
As shown in fig. 9, the driving method of the shift register includes:
s910, when the first level voltage signal output stage is switched to the second level voltage signal output stage, providing a conducting level to the third node, so that the third output module responds to the conducting level of the third node and transmits the second level voltage signal of the second level voltage end to the output end of the shift register.
For example, when the first level voltage signal output stage is switched to the second level voltage signal output stage, a switch module electrically connected to the third node may be controlled by a corresponding clock signal, so that the transfer of the on level may be realized by the switch module. Alternatively, in combination with the description of the shift register of the present application in the foregoing embodiment, the node potential of the third node may be controlled in combination with the coupling capacitor, so that the on level is provided to the third node.
In this way, the third output module is enabled to transmit the second level voltage signal of the second level voltage terminal to the shift register output terminal in response to the on level of the third node.
The embodiment of the application provides a driving method of a shift register, when a first level voltage signal output stage is switched to a second level voltage signal output stage, a third output module is enabled to respond to the conduction level conduction of a third node by providing a conduction level for the third node, and a second level voltage signal of a second level voltage end is transmitted to an output end of the shift register.
Therefore, in the driving method of the shift register according to the embodiment of the present application, the on level is provided to the third node in the original tailing stage, so that the third output module is turned on, and the second level voltage signal at the second level voltage end is transmitted to the output end of the shift register, thereby avoiding the output tailing phenomenon caused by the fact that the second output module cannot be completely turned on in the existing shift register. Therefore, the tailing problem of the output level of the shift register is effectively improved, the performance of the display panel is effectively improved, and the display effect and the competitiveness of the display panel are improved.
In some more specific embodiments, optionally, in order to better implement output control of the second output module and the third output module in the shift register for the second level voltage signal, the shift register may further include a first storage module, and the method for driving the shift register may further include the step, see fig. 10 in particular.
Fig. 10 is a schematic flowchart of another driving method of a shift register according to an embodiment of the present disclosure. As shown in fig. 10, according to some embodiments of the present application, optionally, the driving method of the shift register may further include step S1010.
S1010, when the first level voltage signal output stage is switched to the second level voltage signal output stage, a high level voltage signal is provided for the first clock signal terminal.
Therefore, when the first level voltage signal output stage is switched to the second level voltage signal output stage, the first clock signal end outputs a high level voltage signal, the first storage capacitor plays a role in maintaining the potential of the second node, and the second output module is cut off under the control of the second node. Thus, the tailing phenomenon of the output level of the shift register is further improved.
In some more specific embodiments, optionally, in order to further ensure stable output of the second level voltage signal, the driving method of the shift register may further include a step, see fig. 11 in particular.
Fig. 11 is a schematic flowchart of another driving method of a shift register according to an embodiment of the present application. As shown in fig. 11, according to some embodiments of the present application, optionally, the driving method of the shift register may further include step S1110.
S1110, in a stable output stage after the second level voltage signal output stage, providing a conducting level to the second node, so that the second output module is conducted in response to the conducting level of the second node, and transmits the second level voltage signal of the second level voltage terminal to the output terminal of the shift register.
During specific implementation, the second output module is switched on under the control of the second node by providing the switching-on level for the second node, so that a second level voltage signal of a second level voltage end is transmitted to the output end of the shift register, and continuous and stable output of the output end of the shift register to the second level voltage signal is effectively guaranteed.
It should be understood that, in consideration of the diversity of the means for potential control of the node, the present application is not strictly limited as to how the potential control of the second node is specifically achieved.
Based on the shift register provided in any of the above embodiments, correspondingly, the present application further provides a scan driving circuit, where the scan driving circuit includes a plurality of cascaded shift registers 10 as provided in the above embodiments of the present application.
Based on the shift register provided in any of the above embodiments, correspondingly, the present application further provides a display panel, including the shift register 10 provided in the present application. Referring to fig. 12, fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 12, the display panel 100 provided in the embodiment of the present application may include the shift register described in any of the embodiments above. The display panel shown in fig. 12 may be an Organic Light-Emitting Diode (OLED) display panel.
It should be understood by those skilled in the art that in other implementations of the present application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.
The display panel provided in the embodiment of the present application has the beneficial effects of the shift register 10 provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the shift register 10 in each of the above embodiments, which is not repeated herein.
Based on the display panel that the embodiment provided, correspondingly, this application still provides a display device, includes the display panel that this application provided. Referring to fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 13 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 13, for example, taking a mobile phone as an example, it is understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel 100 in the foregoing embodiments, which is not repeated herein.
It should be understood that the specific structures of the circuits and the structures of the display panels provided in the drawings of the embodiments of the present application are only examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.
It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts in the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first" and "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims (12)
1. A shift register, comprising:
a first output module, a control terminal of which is electrically connected to a first node, a first terminal of which is electrically connected to a first level voltage terminal, and a second terminal of which is electrically connected to an output terminal of a shift register, for transmitting a first level voltage signal of the first level voltage terminal to the output terminal of the shift register in response to a conduction level of the first node;
a second output module, a control terminal of which is electrically connected to a second node, a first terminal of which is electrically connected to the output terminal of the shift register, and a second terminal of which is electrically connected to a second level voltage terminal, for transmitting a second level voltage signal of the second level voltage terminal to the output terminal of the shift register in response to a conduction level of the second node;
a control end of the third output module is electrically connected with the third node, a first end of the third output module is electrically connected with the output end of the shift register, and a second end of the third output module is electrically connected with the second level voltage end;
a first coupling module, a first end of which is electrically connected to the third node, and a second end of which is electrically connected to a first end of the third output module;
when the first level voltage signal output stage is switched to the second level voltage signal output stage, the third output module responds to the conducting level of the third node and transmits the second level voltage signal of the second level voltage end to the output end of the shift register.
2. The shift register of claim 1, further comprising:
and the control end of the first switch module is electrically connected with the second level voltage end, the first end of the first switch module is electrically connected with the second node, and the second end of the first switch module is electrically connected with the third node.
3. The shift register of claim 2, further comprising:
a first end of the first storage module is electrically connected with the second node, and a second end of the first storage module is electrically connected with a first clock signal end;
when the first level voltage signal output stage is switched to the second level voltage signal output stage, the first clock signal end outputs a high level voltage signal.
4. The shift register of claim 2, further comprising:
the control end of the first input module is electrically connected with the second clock signal end, the first end of the first input module is electrically connected with the input end of the shift register, and the second end of the first input module is electrically connected with the second node;
when the first level voltage signal output stage is switched to the second level voltage signal output stage, the first input module responds to the conducting level of the second clock signal end, writes the low level voltage signal of the input end of the shift register into the second node, and the first switch module transmits the low level voltage signal of the second node to the third node.
5. The shift register of claim 2, wherein the first output module comprises a first transistor, the second output module comprises a second transistor, the third output module comprises a third transistor, the first coupling module comprises a first coupling capacitor, and the first switch module comprises a fourth transistor, wherein:
a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to the first level voltage terminal, and a second electrode of the first transistor is electrically connected to the output terminal of the shift register;
a grid electrode of the second transistor is electrically connected with the second node, a first electrode of the second transistor is electrically connected with the output end of the shift register, and a second electrode of the second transistor is electrically connected with the second level voltage end;
a gate of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the output terminal of the shift register, and a second electrode of the third transistor is electrically connected to the second level voltage terminal;
a first electrode plate of the first coupling capacitor is electrically connected with the third node, and a second electrode plate of the first coupling capacitor is electrically connected with a first electrode of the third transistor;
a gate of the fourth transistor is electrically connected to the second level voltage terminal, a first electrode of the fourth transistor is electrically connected to the second node, and a second electrode of the fourth transistor is electrically connected to the third node.
6. The shift register of claim 1, further comprising:
a first control end of the second input module is electrically connected with the first clock signal end, a second control end of the second input module is electrically connected with a fourth node, a first end of the second input module is electrically connected with the second node, and a second end of the second input module is electrically connected with the first voltage level end;
a third input module, electrically connected to the first node, the second node, the fourth node, the first voltage level terminal, the second voltage level terminal, a first clock signal terminal, and a second clock signal terminal, for adjusting potentials of the first node and the fourth node;
a second memory module, a first end of the second memory module being electrically connected to the fourth node;
and the control end of the second switch module is electrically connected with the first clock signal end, the first end of the second switch module is electrically connected with the second end of the second storage module, and the second end of the second switch module is electrically connected with the first node.
7. The shift register of claim 6, wherein the second input block further comprises a fifth transistor and a sixth transistor, the third input block further comprises a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, the second storage block comprises a second storage capacitor, and the second switch block comprises an eleventh transistor;
a gate of the fifth transistor is electrically connected to the fourth node, a first electrode of the fifth transistor is electrically connected to the first level voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;
a gate of the sixth transistor is electrically connected to the first clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the second node;
a gate of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the first voltage level terminal, and a second electrode of the seventh transistor is electrically connected to the first node;
a gate of the eighth transistor is electrically connected to the fourth node, a first electrode of the eighth transistor is electrically connected to the second plate of the second storage capacitor, and a second electrode of the eighth transistor is electrically connected to the first clock signal terminal;
a gate of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the fourth node, and a second electrode of the ninth transistor is electrically connected to the second clock signal terminal;
a gate of the tenth transistor is electrically connected to the second clock signal terminal, a first electrode of the tenth transistor is electrically connected to the fourth node, and a second electrode of the tenth transistor is electrically connected to the second level voltage terminal;
a first plate of the second storage capacitor is electrically connected with the fourth node, and a second plate of the second storage capacitor is electrically connected with a first electrode of the eleventh transistor;
a gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.
8. A driving method applied to the shift register according to any one of claims 1 to 7, the driving method comprising:
when the first level voltage signal output stage is switched to the second level voltage signal output stage, a conducting level is provided for the third node, so that the third output module responds to the conducting level of the third node and transmits a second level voltage signal of the second level voltage end to the output end of the shift register.
9. The driving method according to claim 8, wherein the shift register further includes the first storage module, the driving method further comprising:
and when the first level voltage signal output stage is switched to the second level voltage signal output stage, providing a high level voltage signal to the first clock signal terminal.
10. The driving method according to claim 8, further comprising:
and in a stable output stage after the second level voltage signal output stage, providing a conduction level to the second node so that the second output module is conducted in response to the conduction level of the second node and transmits a second level voltage signal of the second level voltage end to the output end of the shift register.
11. A scan driver circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 7.
12. A display panel comprising the scan driver circuit according to claim 11.
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| CN202211620051.5A CN115862513A (en) | 2022-12-15 | 2022-12-15 | Shift register and driving method thereof, scanning driving circuit and display panel |
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