CN115833798A - High-linearity multi-bit phase interpolator - Google Patents
High-linearity multi-bit phase interpolator Download PDFInfo
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- CN115833798A CN115833798A CN202310115106.5A CN202310115106A CN115833798A CN 115833798 A CN115833798 A CN 115833798A CN 202310115106 A CN202310115106 A CN 202310115106A CN 115833798 A CN115833798 A CN 115833798A
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Abstract
The invention discloses a high-linearity multi-bit phase interpolator, which comprises an orthogonal phase generator and two included angle generators; the quadrature phase generator comprises a first output end and a second output end, two paths of adjacent quadrature signals are output respectively, the two output ends are connected to two input ends of the two kinds of included angle generators respectively, the output ends of the first kind of included angle generator and the second kind of included angle generator are directly connected or connected with a final included angle generator after being cascaded, and the final included angle generator is one of the two kinds of included angle generators and outputs a phase shift signal. The invention has the 360-degree phase shifting function, accurately realizes phase shifting, has high linearity, high precision, simple circuit structure, flexible and controllable phase shifting stepping and digit, can effectively reduce phase noise and jitter of a system, increases the jitter tolerance of a serdes communication system, and effectively improves the stability and the data transmission efficiency of the system.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a high-linearity multi-bit phase interpolator.
Background
At present, electrical information is interacted in a high-speed serial transmission mode in most cases. In the process of using high-speed serial transmission, a Clock and Data Recovery (CDR) circuit is used to perform Clock and Clock calibration on the received Data, which requires a large number of clocks with different phases to sample the Data at an optimal position. In the case of using a common Charge Pump (CP) Phase Locked Loop (PLL), a Phase interpolation circuit is generally used to generate clocks of a plurality of different phases.
The phase interpolation circuit needs to adjust the phase specifically and in real time according to the received data and clock. The traditional phase interpolation circuit adopts an approximate method of phase vector synthesis to realize 360-degree phase shift in a whole plane, the method divides an input signal into an I path and a Q path, and the weight of the I path and the Q path is changed through the magnitude of tail current so as to realize the function of phase shift in the whole plane. However, for a high-bit phase interpolator with a small phase shift step, the control of the current weights of the I path and the Q path becomes more complex and is formed by combining approximate values, which greatly affects the phase shift precision and the linearity of the phase interpolator, thereby increasing the system jitter, reducing the jitter tolerance of a communication system, and restricting the stability of the whole system and the accuracy of transmitted data.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a high-linearity multi-bit phase interpolator, aiming at solving the problem that a phase interpolation circuit in the prior art is poor in phase shifting precision and linearity.
The technical scheme is as follows: a high-linearity multi-bit phase interpolator comprises a quadrature phase generator, a first type included angle generator and a second type included angle generator, wherein the first type included angle generator is used for generating a first output signal or an included angle signal, and the second type included angle generator is used for generating an included angle signal or a second output signal; the amplitude of the included angle signal is the same as the amplitudes of the first output signal and the second output signal, and the phase of the included angle signal is the average value of the phases of the first output signal and the second output signal; the quadrature phase generator comprises a first output end and a second output end, two paths of adjacent quadrature signals are output respectively, the first output end is connected with one input end of one type of included angle generator and two types of included angle generators, the second output end is connected with the other input end of one type of included angle generator and two types of included angle generators, the output ends of one type of included angle generator and two types of included angle generators are directly connected or connected with a final-stage included angle generator after cascading, the final-stage included angle generator is one of one type of included angle generator and two types of included angle generators, and the final-stage included angle generator outputs a phase shifting signal.
Furthermore, the output end of the first-class included angle generator of the previous stage is connected with one input end of the first-class included angle generator of the next stage and one input end of the second-class included angle generator of the previous stage, and the output end of the second-class included angle generator of the previous stage is connected with the other input end of the first-class included angle generator of the next stage and the other input end of the second-class included angle generator of the next stage.
Further, the two signals output by the quadrature phase generator are quadrature signals of two adjacent phases in the phase signals of 0 °, 90 °, 180 °, and 270 °.
Furthermore, the number of the first type of included angle generator is different from that of the second type of included angle generator by one.
Furthermore, the first-class included angle generator comprises an input buffer unit, a first-class phase synthesis unit and an output buffer unit, wherein two paths of input signals are input from the input buffer unit, a control signal is input from the first-class phase synthesis unit, the output buffer unit outputs a first output signal when the control signal is 0, and the output buffer unit outputs an included angle signal when the control signal is 1.
Furthermore, the second type included angle generator includes an input buffer unit, a second type phase synthesis unit and an output buffer unit, wherein two paths of input signals are input from the input buffer unit, a control signal is input from the second type phase synthesis unit, the output buffer unit outputs an included angle signal when the control signal is 0, and the output buffer unit outputs a second output signal when the control signal is 1.
Furthermore, the first-class phase synthesis unit comprises a first differential path and a second differential path, wherein a differential input end of the first differential path inputs a first input signal, a differential input end of the second differential path inputs a second input signal, a differential output end of the first differential path is connected with a differential output end of the second differential path, the first differential path is always conducted when working, the second differential path comprises a first switch S1, when a control signal is 0, the switch S1 is disconnected, and the second differential path does not work; when the control signal is 1, the switch S1 is turned on, and the second differential path operates normally.
Furthermore, the second-class phase synthesis unit comprises a first differential path and a second differential path, a first input signal is input to a differential input end of the first differential path, a second input signal is input to a differential input end of the second differential path, a differential output end of the first differential path is connected with a differential output end of the second differential path, the second differential path is always conducted when the second differential path works, the first differential path comprises a second switch S2, when the control signal is 0, the switch S2 is conducted, and the first differential path works normally; when the control signal is 1, the switch S2 is turned off, and the first differential path does not operate.
Further, the input buffer unit has a low-pass characteristic, and the output buffer unit is configured to amplify the signal to saturation.
The invention provides a high-linearity multi-bit phase interpolator, which has the following beneficial effects compared with the prior art: the high linearity and the high performance are realized; the circuit structure is simple, and the phase shift stepping and the digit are flexible and controllable; the phase noise and the jitter of the system can be effectively reduced, the jitter tolerance of a serdes communication system is increased, and the stability and the data transmission efficiency of the whole system are effectively improved.
Drawings
FIG. 1 is a block diagram of a high linearity multi-bit phase interpolator;
FIG. 2 is a block diagram of a class of angle generators;
FIG. 3 is a block diagram of a second type of angle generator;
FIG. 4 is a schematic circuit diagram of one type of phase synthesizing unit;
FIG. 5 is a schematic circuit diagram of a class two phase synthesizer unit;
fig. 6 shows simulation experiment results of a 6-bit high linearity phase interpolator.
Detailed description of the preferred embodiments
The invention is further explained below with reference to the figures and the specific embodiments.
A high linearity multi-bit phase interpolator, as shown in FIG. 1, includes a quadrature phase generator, a first type angle generator, and a second type angle generator. Taking this embodiment as an example, there are N-1 class-one angle generators and N-2 class-two angle generators.
The input signals of the quadrature phase generator are Vin _ I and Vin _ Q, when the phase needs to move within a range of 360 degrees, the quadrature phase generator needs to be capable of outputting four quadrature phases, namely a 2-bit quadrature phase generator, that is, two paths of output signals are quadrature signals of two adjacent phases in phase signals of 0 degrees, 90 degrees, 180 degrees and 270 degrees, such as 0 degrees and 90 degrees; 90 degrees and 180 degrees; 180 degrees and 270 degrees; 270 deg. and 0 deg. controlled by the most significant 2bit signal vc < N: N-1> and the corresponding relation between the bit and the output phase is shown in Table 1.
TABLE 1 Quadrature phase Generator bit and output phase correspondences
| vc<N:N=1> | Vo _0 phase (°) | Vo _1 phase (°) |
| 00 | 0 | 90 |
| 01 | 90 | 180 |
| 10 | 180 | 270 |
| 11 | 270 | 0 |
The quadrature phase generator comprises a first output end and a second output end, two paths of adjacent quadrature signals are output respectively, the first output end is connected with one input end of the first-class included angle generator and one input end of the second-class included angle generator, the second output end is connected with the other input end of the first-class included angle generator and the other input end of the second-class included angle generator, output ends of the first-class included angle generator and the second-class included angle generator are connected with a final-stage included angle generator after being cascaded, in the embodiment, the first-class included angle generator is one more than the second-class included angle generator, so the final-stage included angle generator is the first-class included angle generator, and the second-class included angle generator can be selected to be used, and the second-class included angle generator is one more than the first-class included angle generator. And the final-stage included angle generator outputs a final phase shift signal. Therefore, the number of the first type of angle generators and the second type of angle generators in the whole high-linearity multi-bit phase interpolator is different by one, and the extra angle generator is used as the final angle generator.
The first type of included angle generator outputs a first output signal or an included angle signal according to a first input signal Vin _0 and a second input signal Vin _1, the second type of included angle generator outputs an included angle signal or a second output signal according to a first input signal Vin _0 and a second input signal Vin _1, the amplitude of the included angle signal is the same as the amplitude of the first output signal and the amplitude of the second output signal, the phase of the included angle signal is the average value of the phase of the first output signal and the phase of the second output signal, and if the phase of the first output signal is 0 degrees and the phase of the second output signal is 45 degrees, the phase of the included angle signal is 22.5 degrees.
The cascade connection refers to that the output end of the first class included angle generator of the previous stage is connected with one input end of the first class included angle generator of the next stage and one input end of the second class included angle generator, and the output end of the second class included angle generator of the previous stage is connected with the other input end of the first class included angle generator of the next stage and the other input end of the second class included angle generator. The cascade stage number of the included angle generator can select a proper stage number according to the precision requirement. Even under the condition of meeting the precision requirement, the device can be directly connected with a final-stage included angle generator after the first-stage included angle generator, and cascade connection of multiple stages is not needed.
To sum up, for the two types of angle generators of the kth stage, two vector signals with a phase angle of θ/2 (where θ is the angle between the two signals generated by the previous stage) are generated respectively and serve as secondary input signals, and so on, the phase interpolator can be extended to multiple bits until the final-stage angle generator is connected. Each stage can divide the vector signal with the angle theta at the previous stage into two parts strictly and accurately through a proportional current mirror, and the divided signal is used as a secondary input signal.
Referring to fig. 2, the first-class angle generator includes an input buffer unit, a first-class phase synthesis unit, and an output buffer unit, wherein a first input signal Vin _0 and a second input signal Vin _1 are input from the input buffer unit, a control signal is input from the first-class phase synthesis unit, the output buffer unit outputs a first output signal when a control signal vc < k > is 0, and the output buffer unit outputs an angle signal when the control signal vc < k > is 1, and the corresponding relationship between the bit and the output phase is shown in table 2.
TABLE 2 corresponding relationship between bit and output phase of angle generator
| vc<k> | Vout phase (°) |
| 0 | 0 |
| 1 | θ/2 |
As shown in fig. 3, the second-class angle generator includes an input buffer unit, a second-class phase synthesis unit, and an output buffer unit, wherein the first input signal Vin _0 and the second input signal Vin _1 are input from the input buffer unit, the control signal is input from the second-class phase synthesis unit, the output buffer unit outputs the angle signal when the control signal vc < k > is 0, and the output buffer unit outputs the second output signal when the control signal vc < k > is 1. The corresponding relationship between the bit and the output phase is shown in table 3.
TABLE 3 corresponding relationship between bits and output phases of two kinds of angle generators
| vc<k> | Vout phase (°) |
| 0 | θ/2 |
| 1 | θ |
The input buffer unit has a low-pass characteristic and can convert the received full-swing square wave into a sine wave with a small swing. The output buffer unit is used for amplifying the signal to saturation and outputting the signal by a full-swing square wave.
In terms of the circuit implementation of a particular phase synthesis unit, one implementation is given as shown in fig. 4 and 5, but other phase synthesis circuit configurations are not excluded. As shown in fig. 4, the first-type phase combining unit includes a first differential path and a second differential path, tail currents of the first differential path and the second differential path are the same, and sizes of transistors corresponding to the first differential path and the second differential path are also completely the same. A first input signal Vin _0+/-, a second input signal Vin _1+/-, which is input to a differential input end of a first differential path, a differential output end of the first differential path is connected with a differential output end of a second differential path, the first differential path is always kept on during work, the second differential path comprises a first switch S1, when a control signal vc < k > =0, the first switch S1 is disconnected, only the first differential path works normally, the second differential path does not work, and therefore, an output signal is a first output signal at the moment; when the control signal vc < k > =1, the first switch S1 is closed, and the first differential path and the second differential path operate simultaneously, so that the angle signal is output at this time.
As shown in fig. 5, the second-type phase synthesizer unit includes a first differential path and a second differential path, a first input signal Vin _0 +/-is input to a differential input terminal of the first differential path, a second input signal Vin _1 +/-is input to a differential input terminal of the second differential path, a differential output terminal of the first differential path is connected to a differential output terminal of the second differential path, the second differential path is always turned on during operation, the first differential path includes a second switch S2, when a control signal vc < k > =0, the second switch S2 is closed, the first differential path and the second differential path operate simultaneously, and therefore, an included angle signal is output at this time; when the control signal vc < k > =1, the second switch S2 is turned off, only the second differential path operates normally, and the first differential path does not operate, so that the output signal at this time is the second output signal.
The amplitude of the included angle signal is the same as the amplitudes of the first output signal and the second output signal, and the phase of the included angle signal is the average value of the phases of the first output signal and the second output signal.
Taking a 6-bit high-linearity phase interpolator as an example, fig. 6 shows that the Difference Nonlinearity (DNL) of the phase interpolator varies with control words (0-63) under simulation conditions, and it is shown that the maximum DNL value is 0.25, so that it can be seen that the high-linearity multi-bit phase interpolator provided by the present embodiment has good linearity.
Claims (10)
1. A high linearity multi-bit phase interpolator is characterized by comprising an orthogonal phase generator, a first class included angle generator and a second class included angle generator, wherein the first class included angle generator is used for generating a first output signal or an included angle signal, and the second class included angle generator is used for generating an included angle signal or a second output signal; the amplitude of the included angle signal is the same as the amplitudes of the first output signal and the second output signal, and the phase of the included angle signal is the average value of the phases of the first output signal and the second output signal; the quadrature phase generator comprises a first output end and a second output end, two paths of adjacent quadrature signals are output respectively, the first output end is connected with one input end of one type of included angle generator and two types of included angle generators, the second output end is connected with the other input end of one type of included angle generator and two types of included angle generators, the output ends of one type of included angle generator and two types of included angle generators are directly connected or connected with a final-stage included angle generator after cascading, the final-stage included angle generator is one of one type of included angle generator and two types of included angle generators, and the final-stage included angle generator outputs a phase shifting signal.
2. The high linearity multi-bit phase interpolator of claim 1, wherein the output terminal of the first type of angle generator of the previous stage is connected to one input terminal of the first type of angle generator and the second type of angle generator of the next stage, and the output terminal of the second type of angle generator of the previous stage is connected to the other input terminal of the first type of angle generator and the second type of angle generator of the next stage.
3. The high linearity multi-bit phase interpolator of claim 1 or 2, wherein the two signals outputted by the quadrature phase generator are quadrature signals of two adjacent phases of the 0 °, 90 °, 180 °, 270 ° phase signals.
4. The high linearity multi-bit phase interpolator of claim 1 or 2, wherein the number of the angle generators of one type differs from the number of the angle generators of two types by one.
5. The high linearity multi-bit phase interpolator of claim 1 or 2, wherein the first class of angle generator comprises an input buffer unit, a first class of phase synthesis unit, and an output buffer unit, two input signals are input from the input buffer unit, a control signal is input from the first class of phase synthesis unit, the output buffer unit outputs a first output signal when the control signal is 0, and the output buffer unit outputs an angle signal when the control signal is 1.
6. The high linearity multi-bit phase interpolator of claim 1 or 2, wherein the class two angle generator comprises an input buffer unit, a class two phase synthesis unit, and an output buffer unit, two input signals are input from the input buffer unit, a control signal is input from the class two phase synthesis unit, the output buffer unit outputs the angle signal when the control signal is 0, and the output buffer unit outputs the second output signal when the control signal is 1.
7. The high linearity multi-bit phase interpolator of claim 5, wherein one type of phase synthesis unit comprises a first differential path and a second differential path, a first input signal is input to a differential input terminal of the first differential path, a second input signal is input to a differential input terminal of the second differential path, a differential output terminal of the first differential path is connected to a differential output terminal of the second differential path, the first differential path is always on when operating, the second differential path comprises a first switch S1, when a control signal is 0, the switch S1 is off, and the second differential path is not operating; when the control signal is 1, the switch S1 is turned on, and the second differential path operates normally.
8. The high linearity multi-bit phase interpolator of claim 6, wherein the second-type phase synthesis unit comprises a first differential path and a second differential path, a differential input terminal of the first differential path inputs the first input signal, a differential input terminal of the second differential path inputs the second input signal, a differential output terminal of the first differential path is connected to a differential output terminal of the second differential path, the second differential path is always conducted during operation, the first differential path comprises a second switch S2, when the control signal is 0, the switch S2 is conducted, and the first differential path is normally operated; when the control signal is 1, the switch S2 is turned off, and the first differential path does not operate.
9. The high linearity multi-bit phase interpolator of claim 5, wherein said input buffer unit has a low pass characteristic, and said output buffer unit is configured to amplify a signal to saturation.
10. The high linearity multi-bit phase interpolator of claim 6, wherein said input buffer unit has a low pass characteristic, and said output buffer unit is configured to amplify a signal to saturation.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050147194A1 (en) * | 2003-12-31 | 2005-07-07 | Intel Corporation | Programmable phase interpolator adjustment for ideal data eye sampling |
| US20130285727A1 (en) * | 2012-01-31 | 2013-10-31 | Texas Instruments Incorporated | Octal clock phase interpolator architecture |
| CN105207644A (en) * | 2015-09-16 | 2015-12-30 | 电子科技大学 | On-chip active phase shifter based on vector synthesis |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| CN108092649A (en) * | 2018-01-03 | 2018-05-29 | 龙迅半导体（合肥）股份有限公司 | A kind of control method of phase interpolator and phase interpolator |
| CN109964404A (en) * | 2016-11-08 | 2019-07-02 | 德州仪器公司 | High linearity phase interpolator |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050147194A1 (en) * | 2003-12-31 | 2005-07-07 | Intel Corporation | Programmable phase interpolator adjustment for ideal data eye sampling |
| US20130285727A1 (en) * | 2012-01-31 | 2013-10-31 | Texas Instruments Incorporated | Octal clock phase interpolator architecture |
| CN105207644A (en) * | 2015-09-16 | 2015-12-30 | 电子科技大学 | On-chip active phase shifter based on vector synthesis |
| CN109964404A (en) * | 2016-11-08 | 2019-07-02 | 德州仪器公司 | High linearity phase interpolator |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| CN108092649A (en) * | 2018-01-03 | 2018-05-29 | 龙迅半导体（合肥）股份有限公司 | A kind of control method of phase interpolator and phase interpolator |
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