CN115833761A - Method for adjusting and calibrating offset voltage of operational amplifier by adjustable current source - Google Patents
Method for adjusting and calibrating offset voltage of operational amplifier by adjustable current source Download PDFInfo
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- CN115833761A CN115833761A CN202211475158.5A CN202211475158A CN115833761A CN 115833761 A CN115833761 A CN 115833761A CN 202211475158 A CN202211475158 A CN 202211475158A CN 115833761 A CN115833761 A CN 115833761A
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Abstract
The invention discloses a method for trimming and calibrating offset voltage of an operational amplifier by using a trimmable current source. The invention does not need to add extra devices or masks, is compatible with the standard CMOS process, does not need a complex dynamic control unit of the traditional digital dynamic trimming and calibrating circuit, and has trimming precision far higher than the scheme of trimming the fuse fusing resistor.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for adjusting and calibrating offset voltage of an operational amplifier by using an adjustable current source.
Background
In the field of analog chips, operational amplifiers (operational amplifiers for short) are very important components. In addition to the existence of a large number of general operational amplifier products, operational amplifiers are also very important functional units in various complex analog chips or digital-analog hybrid chips.
A classical operational amplifier block diagram is shown IN fig. 1, and comprises two input terminals (non-inverting input terminal IN +, inverting input terminal IN-) and one OUTPUT terminal (OUTPUT). The operational amplifier has the main functions of suppressing a common-mode input signal and amplifying an input differential-mode signal.
For an ideal operational amplifier, the potentials of the non-inverting input and the inverting input are completely consistent. Theoretically, an ideal operational amplifier can amplify any small signal. However, in actual engineering products, due to the inherent processing accuracy and defects of the semiconductor process, the accuracy of the operational amplifier is affected by the mismatch of the operational amplifier input stage device, the mismatch of the resistor, or the mismatch of the bias current source.
The accuracy of the operational amplifier is mainly characterized by the input offset voltage. The input offset voltage is the difference between the dc voltages applied to the two input terminals in the differential input operational amplifier in order to obtain a constant zero voltage output at the output terminal. In FIG. 1, V is used OS Identifying offset voltage of operational amplifier if amplitude of signal to be amplified is less than V OS Then the signal will not be accurately amplified.
Furthermore, different application scenarios are aimed at. Parameters such as the input bias current, input current offset or noise of the operational amplifier also affect the system accuracy.
Therefore, in the fields of high-precision sensors, precision instruments, and the like, it is desirable that the offset voltage of the operational amplifier be as small as possible. Although the inherent offset voltage level of the operational amplifier can be improved through excellent circuit design and layout design, the inherent defects of semiconductor basic process processing cause the offset voltage of the operational amplifier to have random variation, and the precision can be further ensured only through trimming and calibration in a chip testing stage.
Early operational amplifiers were typically designed and fabricated based on Bipolar (Bipolar) technology. Although the bipolar process is not compatible with the CMOS process used by the current lsi chip, it is still an important process for a general discrete operational amplifier due to the better transconductance, gain and matching level of the bipolar device. In the operational amplifier of the bipolar or bipolar compatible JFET, the early scheme is to carry out input offset voltage zero adjustment through an external potentiometer; however, this solution increases the complexity of the application and is less used at present.
A more common calibration scheme is to trim the collector resistance of the differential input pair or the resistance of the emitter of the current source. A fused zener diode or a narrower metal wire scheme may be used. Some semiconductor processes are compatible with high-precision metal film resistors, and can be adjusted and calibrated by cutting the resistors through online laser.
Operational amplifiers another technology path is the use of CMOS processes. With the improvement of the process machining precision, compared with a bipolar operational amplifier, the integration level of the CMOS operational amplifier is higher, and because the grid electrode of the CMOS transistor has no current, the input impedance can reach infinity theoretically, and the CMOS operational amplifier is more suitable for amplifying weak signals. In a CMOS operational amplifier without trimming and calibration, the input offset voltage is usually more than 2mV, so that the requirements of higher-precision application occasions cannot be met, and the trimming and calibration are required if the precision is further improved. In CMOS operational amplifiers, less resistive trimming schemes are used, and the currently published technologies include EEPROM or schemes using digital trimming calibration.
In the production of operational amplifier, several conventional schemes for trimming and calibrating the input offset voltage are mentioned, each having its advantages and disadvantages.
The resistor fuse trimming scheme has the advantages that no additional process flow is needed, but the resistor can be trimmed in a single direction, and the trimming precision is influenced by the minimum step; the trimming part occupies more chip area, and the trimming position is limited, so that the trimming precision and the trimming range are influenced.
The laser on-line trimming of the metal film resistor is to perform trimming and cutting on the metal film resistor by using laser trimming equipment, and by controlling the stepping of laser trimming, the trimming precision can be greatly improved, and the linear trimming calibration of precision indexes is approximately realized. However, the preparation of the metal thin film resistor requires a special process, which is usually combined with an early Bipolar (Bipolar) process, and the current CMOS process has less support for the preparation flow of the metal thin film resistor.
In CMOS operational amplifiers, EEPROMs require additional devices or process steps and are now less used in common operational amplifier products.
The digital dynamic trimming calibration has higher flexibility, can dynamically monitor the offset voltage change of the operational amplifier in the using process of the circuit, and dynamically calibrate the output precision by changing the mode of serially input control codes. This solution has a high flexibility but requires the addition of additional internal or external control circuitry; for some applications that only require one-time calibration, the additional control circuit increases the complexity of the system, resulting in a limitation in the use of this trimming scheme.
Disclosure of Invention
The invention aims to solve the technical problem that the defect in the prior art can be effectively overcome by adding a trimmable current source in a circuit and realizing the trimming calibration in a sealing test stage.
The invention is realized by the following technical scheme: a method for trimming and calibrating offset voltage of operational amplifier by using trimmable current source can be used for trimming operational amplifiers with various structures. The differential input stage is composed of a differential pair composed of PMOS transistors MP1 and MP2 and used for realizing differential signal amplification and converting an input voltage signal into a current signal;
the NMOS transistors MN7 and MN8 are intermediate gain stages, and the intermediate gain stages are current amplifiers; PMOS transistors MP9, MP10, MP11 and MP12 form a cascode current mirror as an active load to realize the conversion from differential to single-ended output and the conversion from current signals to voltage signals;
the drain terminals of the input stage differential pair transistors MP1 and MP2 are provided with adjustable current sources I B1 、I B2 By adjusting the current source I B1 、I B2 The current is finely adjusted to realize the offset voltage V OS Compensation of (2);
specifically, a current source I B1 、I B2 Current source I designed to be fixed bias B01 、I B02 Respectively connected with a trimmable current source I T1 、I T2 Parallel mode, the formula is as follows:
I B1 ＝I B01 +I T1 ；
I B2 ＝I B02 +I T2 ；
wherein，I B01 And I B02 Current source for fixed bias, I T1 And I T2 To adjust the current source.
As a preferred technical scheme, the trimming method is as follows:
s1, firstly testing the initial offset voltage V of the operational amplifier without trimming OS0 ；
S2, modifying I according to the difference between the offset voltage and the ideal value T1 Or I T2 Thereby correcting the offset voltage;
since the direction (i.e. positive and negative) of the offset voltage is random, I T1 Or I T2 Respectively corresponding to trimming in the same direction or in the reverse direction; according to the requirement of system precision, I T1 Or I T2 Different current source combinations are set to realize the control of the trimming precision of the operational amplifier.
As a preferred technical scheme, a current source I is adopted T1 Or I T2 Set in parallel with 2-ary weighted current sources, in particular, set I T1 Or I T2 N groups of current sources are connected in parallel, and the minimum weight current is I 0 Then, I T1 And I T2 Can be represented by the following formula:
I T1 ＝I T2 ＝2 n-1 *I 0 +…+2 1 *I 0 +2 0 *I 0 ＝(1+2+…+2 n-1 )I 0
the minimum step precision of trimming is controlled by the minimum weight current position I 0 And (6) determining. The trimming voltage range is composed of a weight current bit number n and a minimum weight current bit I 0 And (4) jointly determining.
The invention has the beneficial effects that: the offset voltage index of the CMOS operational amplifier adopting the structure and the trimming and calibrating scheme is greatly optimized, and the input offset voltage of the CMOS operational amplifier which is not trimmed is more than 1 mV; after the structure is adopted for trimming, the offset voltage of the operational amplifier can be controlled within 20 muV.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an operational amplifier with offset voltage;
FIG. 2 is a classic two-stage CMOS operational amplifier;
FIG. 3 is a circuit diagram of a two-stage CMOS operational amplifier with an added trimmable current source;
fig. 4 is a schematic structural diagram of embodiment 1 of the present invention.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
As shown in fig. 2, the method for trimming and calibrating offset voltage of an operational amplifier by using a trimmable current source according to the present invention is suitable for trimming operational amplifiers with various structures, and the cited conventional CMOS operational amplifier includes a differential input stage and an intermediate gain stage;
the differential input stage is composed of a differential pair composed of PMOS transistors MP1 and MP2 and used for realizing differential signal amplification and converting an input voltage signal into a current signal;
the NMOS transistors MN7 and MN8 are intermediate gain stages, and the intermediate gain stages are current amplifiers; PMOS transistors MP9, MP10, MP11 and MP12 form a cascode current mirror as an active load to realize the conversion from differential to single-ended output and the conversion from current signals to voltage signals; the drain terminals of the input stage differential pair transistors MP1 and MP2 are provided with adjustable current sources I B1 、I B2 By adjusting the current source I B1 、I B2 The current of (2) is finely adjusted to realize the compensation of the offset voltage VOS.
Physical mismatch of the input stage transistors, wherein the mismatch of the input differential pair transistors MP1, MP2 has the greatest impact on the accuracy of the operational amplifier. In addition, I B1 、I B2 Are respectively provided withThe current sources of the differential input pair transistors MP1 and MP2 also affect the quiescent operating point of the input differential pair transistors, and the mismatch of the current sources also introduces an input voltage offset at the input terminal.
In engineering applications, if an offset voltage V is generated between the operational amplifier input terminals due to objective process deviation OS By adjusting the current source I B1 、I B2 The current of the voltage source is adjusted to be the offset voltage V OS And compensating to achieve the purposes of reducing input offset and improving the operational amplifier precision.
As shown in fig. 3, a current source I B1 、I B2 Designed in a mode in which a fixed-bias current source and a trimmable current source are connected in parallel, I B1 ＝I B01 +I T1 ，I B2 ＝I B02 +I T2 In which I B01 And I B02 A current source that is a fixed bias; i is T1 And I T2 To adjust the current source.
In engineering applications, the initial offset voltage V of the operational amplifier without trimming is firstly tested OS0 Then, according to the difference between the offset voltage and the ideal value, trimming I T1 Or I T2 Thereby calibrating the offset voltage. Since the direction (i.e. positive and negative) of the offset voltage is random, I T1 Or I T2 Corresponding to the same or opposite trimming, respectively.
According to the requirement of system precision, I T1 Or I T2 Different current source combinations are set, and the precision of the operational amplifier can be modified.
One conventional solution is to couple a current source I T1 Or I T2 And then the scheme of 2-system weighted current source parallel connection is set. Such as setting I T1 Or I T2 N groups of current sources are connected in parallel, and the minimum weight current is I 0 Then, I T1 And I T2 Can be represented by the following formula:
I T1 ＝I T2 ＝2 n-1 *I 0 +…+2 1 *I 0 +2 0 *I 0 ＝(1+2+…+2 n-1 )I 0。
n-bit2-system weighting adjustable current source I T1 Or I T2 The corresponding schematic diagram of the circuit structure is shown in fig. 4:
in fig. 4, only the 1 st, 2 nd and n th fuse cells are shown, and the 3 rd to n-1 th bits are omitted. Before the fuses Fuse _1 to Fuse _ n are not blown, each bit weight current source branch is switched on. Ir is the reference current, and NMOS transistors MT _ 1-MT _ n are the proportional current sources respectively composed of NMOS transistor MT0, wherein the aspect ratio and size of MT _1 and MT0 are completely the same. The proportional relationship of the aspect ratios of MT _1 to MT _ n is set as follows, and the 3 rd to the n-1 th bits are omitted.
MT_1：MT_2:…:MT_n＝2 0 :2 1 :…:2 n-1 。
The ratio of each bit weight current is determined by the ratio of the width to length ratios of the transistors. Let the drain currents of MT _ 1-MT _ n (i.e., the weight current of each bit) be I out1 -Ioutn, where Iout1= Ir, the current proportionality is as follows:
I out1 :I out2 :…:I outn ＝2 0 :2 1 :…:2 n-1 ；
adjustable current source I T Is the sum of the total per-weight circuits:
I T ＝I out1 +I out2 +…+I outn ＝(1+2+…+2 n-1 )I r 。
gate source voltage V of MOS transistor GS Is AND transistor bias current I D And width-to-length ratio (W/L), as shown in the following equation:
when the bias current of the input differential pair transistors MP1 and MP2 is changed through trimming, the gate-source voltage of the transistors MP1 and MP2 can be changed, so that the input offset voltage is influenced.
Taking fig. 3 and fig. 4 as an example, the trimmable current source IT1 in fig. 3 is equivalent to the structure shown in fig. 4. If trimming is performed at this time, the Fuse _1 is blown, and the current of the branch corresponding to the transistor MT _1 will flowIs disconnected. That is, the current of the adjustable current source is reduced to IT1-I out1 . In CMOS processes, fuses may be implemented with poly or metal layers.
As the bias current of MP1 decreases, the gate-source voltage V of MP1 GS1 And is reduced accordingly.
Similarly, if the gate-source voltage of the input stage transistor MP2 at the inverting input terminal of the operational amplifier needs to be reduced, the corresponding fuse unit in the programmable current source IT2 may be trimmed.
If the number of the current sources n =4 in fig. 4 is taken, the trimming range of the current sources is-15I 0 ～+15I 0 In the meantime.
If the adjustable voltage of the minimum weight current corresponding to the input terminal is 20 μ V, the adjustable offset voltage range of the four-bit weight current source is between-300 μ V and +300 μ V.
Obviously, the ratio of the minimum bit weight current to the bias current of the differential pair transistors MP1 and MP2 is reduced; the precision of trimming can be improved by increasing the number n of the weight current bits. Depending on the requirements of the operational amplifier design accuracy.
The operational amplifier is used for adjusting the offset voltage of the chip, namely, in the stage of testing the circuit chip, the calibration of the input offset voltage is completed by measuring, calculating and fusing the weight current bit corresponding to the programmable current source IT1 or IT2 and changing the chip current of the input stage transistor.
The trimming constant current source structure for calibrating the offset voltage of the operational amplifier mentioned in the present invention is not limited to the circuit structure shown in fig. 4, but can be implemented by other circuit schemes, for example, the company has a patent "a one-time trimming calibration structure of current source, application number: the current source structure of 202111171772.8 can also realize offset voltage calibration of the operational amplifier.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.
Claims (3)
1. A method for trimming and calibrating offset voltage of an operational amplifier by using a trimmable current source is suitable for trimming the operational amplifiers with various structures, wherein the cited conventional CMOS operational amplifier comprises a differential input stage and an intermediate gain stage;
the differential input stage is composed of a differential pair composed of PMOS transistors MP1 and MP2 and used for realizing differential signal amplification and converting an input voltage signal into a current signal;
the NMOS transistors MN7 and MN8 are middle gain stages which are current amplifiers; PMOS transistors MP9, MP10, MP11 and MP12 form a cascode current mirror as an active load to realize the conversion from differential to single-ended output and the conversion from current signals to voltage signals;
the method is characterized in that: the drain terminals of the input stage differential pair transistors MP1 and MP2 are provided with adjustable current sources I B1 、I B2 By adjusting the current source I B1 、I B2 The current is finely adjusted to realize the compensation of the offset voltage VOS;
specifically, a current source I B1 、I B2 Current source I designed for fixed bias B01 、I B02 Respectively connected with a trimmable current source I T1 、I T2 Parallel mode, the formula is as follows:
I B1 ＝I B01 +I T1 ；
I B2 ＝I B02 +I T2 ；
wherein, I B01 And I B02 For a fixed bias current source, I T1 And I T2 To adjust the current source.
2. The method of claim 1 for trimming calibration of an operational amplifier offset voltage with a trimmable current source is characterized by:
s1, firstly testing the initial offset voltage V of the operational amplifier without trimming OS0 ；
S2, modifying I according to the difference between the offset voltage and the ideal value T1 Or I T2 Thereby correcting the offset voltage;
s3, because the direction (namely positive and negative) of the offset voltage has randomness, I T1 Or I T2 Respectively corresponding to trimming in the same direction or the reverse direction;
s4, according to the requirement of system precision, processing I T1 Or I T2 Different current source combinations are set to realize the control of the trimming precision of the operational amplifier.
3. The method of claim 1, wherein the method further comprises the step of performing trimming calibration on the offset voltage of the operational amplifier with the trimmable current source, wherein: current source I T1 Or I T2 Setting weighting mode of current to set current source I T1 Or I T2 Setting a 2-system weighted current source in parallel: specifically, set I T1 Or I T2 N groups of current sources are connected in parallel, and the minimum weight current is I 0 Then, I T1 And I T2 Can be represented by the following formula:
I T1 ＝I T2 ＝2 n-1 *I 0 +…+2 1 *I 0 +2 0 *I 0 ＝(1+2+…+2 n-1 )I 0 ；
the minimum step precision of trimming is controlled by the minimum weight current position I 0 Determining that the trimming voltage range is composed of a weight current bit n and a minimum weight current bit I 0 And (4) jointly determining.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116805859A (en) * | 2023-08-28 | 2023-09-26 | 江苏润石科技有限公司 | Operational amplifier offset voltage regulation circuit and method |
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| CN116805859A (en) * | 2023-08-28 | 2023-09-26 | 江苏润石科技有限公司 | Operational amplifier offset voltage regulation circuit and method |
| CN116805859B (en) * | 2023-08-28 | 2023-11-07 | 江苏润石科技有限公司 | Operational amplifier offset voltage regulation circuit and method |
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