CN115826675A - Waveform synthesis system and chip - Google Patents
Waveform synthesis system and chip Download PDFInfo
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Abstract
The present disclosure relates to a waveform synthesis system and a chip, which can greatly reduce the occupied space of a wavetable without storing the whole amplitude value of a waveform in the waveform synthesis process. The waveform synthesis system includes: the differential control module, the accumulator, the digital-to-analog converter and the filter are sequentially in communication connection; the differential control module is used for outputting corresponding slope values according to the received clocks; the accumulator is used for respectively constructing segmented straight lines aiming at each slope value, sequentially accumulating the segmented straight lines and outputting initial waveforms corresponding to the wave table; the digital-to-analog converter is used for performing digital-to-analog conversion on the initial waveform and outputting a zero-order hold waveform corresponding to the wavetable; and the filter is used for filtering the zero-order hold waveform and outputting the target waveform after the wavetable is extended.
Description
Technical Field
The present disclosure relates to the field of frequency synthesis technologies, and in particular, to a waveform synthesis system and a chip.
Background
In the process of processing continuous waveforms, an accumulator of a Direct Digital Frequency Synthesizer (DDFS) generates continuously accumulated phases, a waveform lookup table converts the phases into digitized waveform amplitudes, a Digital-to-analog converter (DAC) stores the whole amplitude of the continuous waveforms due to the need, and redundant information exists in a wave table, so that a storage unit is large and storage efficiency is low.
Disclosure of Invention
The purpose of the present disclosure is to provide a waveform synthesis system and a chip, which do not need to store the whole amplitude value of the waveform in the waveform synthesis process, thereby greatly reducing the occupied space of the wave table.
To achieve the above object, in a first aspect, the present disclosure provides a waveform synthesis system including: the differential control module, the accumulator, the digital-to-analog converter and the filter are sequentially in communication connection;
the differential control module is used for outputting corresponding slope values according to a plurality of received clocks, and each clock is obtained according to a wave table;
the accumulator is used for respectively constructing segmented straight lines aiming at each slope value, sequentially accumulating the segmented straight lines and outputting initial waveforms corresponding to the wave table;
the digital-to-analog converter is used for performing digital-to-analog conversion on the initial waveform and outputting a zero-order hold waveform corresponding to the wavetable;
and the filter is used for filtering the zero-order hold waveform and outputting the target waveform after the wavetable is extended.
Optionally, the accumulator is configured to obtain the piecewise straight line by piecewise linear interpolation according to the slope value.
Optionally, the differential control module includes a differential wave table address controller and a differential wave table, which are sequentially in communication connection, and the differential wave table is in communication connection with the accumulator;
the differential wave table address controller is used for carrying out counting according to the accumulation or the subtraction of the received clock;
and the differential wave table is used for outputting a corresponding slope value according to the accumulation or the subtraction of the differential wave table address controller.
Optionally, the differential wave table is further configured to store a plurality of slope values corresponding to the wave table in a differential manner.
Optionally, the depth and the width of each wave table in the differential wave table are both an integral power of two.
Optionally, the wave table includes a compression multiple, and the waveform synthesis system further includes a frequency dividing module, and the frequency dividing module is communicatively connected to the differential control module;
the frequency division module is used for acquiring clocks corresponding to the wavetable, dividing the frequency of each clock according to the compression multiple, and sending the plurality of divided clocks to the differential wavetable address controller.
Optionally, the wavetable includes a period value of the target waveform, and the frequency dividing module is configured to determine a plurality of clocks corresponding to the wavetable according to the period value, where one period corresponds to four clocks.
Optionally, the waveform synthesis system further includes an extraction module, where the extraction module is configured to intercept the high order of the initial waveform according to the width value of the digital-to-analog converter, and send the intercepted initial waveform to the digital-to-analog converter.
Optionally, the filter comprises a bessel filter.
In a second aspect, the present disclosure provides a chip comprising the waveform synthesis system according to the first aspect.
According to the technical scheme, the difference controller outputs a plurality of slope values of the waveform according to the wave table, the accumulator extends the wave table according to the slope values to obtain the initial waveform corresponding to the wave table, the digital-to-analog converter performs digital-to-analog conversion on the initial model to output a zero-order hold waveform, and the filter performs filtering on the zero-order hold waveform to output a target waveform. Only a plurality of slope values corresponding to the continuous waveform need to be stored, the whole amplitude value of the continuous waveform does not need to be stored, and the occupied space of the wave table is greatly reduced.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a schematic diagram of a waveform synthesis system shown in accordance with an exemplary embodiment of the present disclosure;
FIG. 2 is a synthesis schematic diagram of a waveform synthesis system shown in accordance with an exemplary embodiment of the present disclosure;
FIG. 3 is another schematic diagram of a waveform synthesis system according to an exemplary embodiment of the present disclosure;
FIG. 4 is a simulated wavetable comparison of 1/16 of a waveform synthesis system shown in accordance with an exemplary embodiment of the present disclosure;
FIG. 5 is a simulated synthesized spectrum of 1/16 of a waveform synthesis system according to an exemplary embodiment of the present disclosure;
FIG. 6 is a comparison of simulated wave tables for 1/32 of a waveform synthesis system shown in accordance with an exemplary embodiment of the present disclosure;
FIG. 7 is a simulated synthesized spectrum of 1/32 of a waveform synthesis system shown in accordance with an exemplary embodiment of the present disclosure.
Description of the reference numerals
10 a differential control module; 20 accumulators; 30 digital-to-analog converters; 40 a filter; a frequency division by 50 module; 101 a differential wavetable address controller; 102 differential wavetable.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
It should be noted that all actions of acquiring signals, information or data in the present disclosure are performed under the premise of complying with the corresponding data protection regulation policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
As background, the accumulator of DDFS generates continuously accumulated phases during the processing of continuous waveforms, the waveform lookup table converts the phases into digitized waveform amplitudes, the DAC programs the digital amplitudes into analog quantities, and finally the low-pass filter filters the spur spectrum and outputs the synthesized waveform, the output frequency of DDFS is obtained by the following equation (tuning formula):
wherein the content of the first and second substances,F r a frequency control word is represented that is,jwhich represents the width of the phase accumulator and,f clk which represents the frequency of the clock or clocks,f out indicating the synthesis frequency.
And the output period of the accumulatorp o Is obtained by the following formula:
wherein the content of the first and second substances,gcd（2 j ，F r ) Is shown to solve 2 j AndF r the greatest common divisor of (c).
It can be seen that the period of the accumulator changes as the frequency control word changes. And each unit in the wave table is the whole amplitude value of the waveform, and for most continuous waveforms, under a certain sampling frequency, compared with the data of the front unit and the rear unit, the data of a certain unit in the wave table has certain redundant information, so that the storage efficiency of the wave table is low.
In view of this, the present disclosure provides a waveform synthesis system and a chip, which do not need to store the whole amplitude value of the waveform, so as to greatly reduce the occupied space of the wave table, store more wave table contents under the same resource, and implement multi-channel waveform synthesis.
Fig. 1 is a schematic structural diagram illustrating a waveform synthesis system according to an exemplary embodiment of the present disclosure, referring to fig. 1, the waveform synthesis system including: a differential control module 10, an accumulator 20, a digital-to-analog converter 30 and a filter 40 which are sequentially connected in communication;
and the differential control module 10 is configured to output corresponding slope values according to a plurality of received clocks, where each of the clocks is obtained according to a wave table.
Wherein, W1 represents the data width of the wave table; fcw represents the frequency control word of the wave table output; w0 represents the data width of the waveform corresponding to the wave table; w0-d represent the width of the compressed waveform, corresponding to the width of the slope value of the corresponding wavetable.
And the accumulator 20 is used for respectively constructing segmented straight lines according to each slope value, sequentially accumulating the segmented straight lines and outputting initial waveforms corresponding to the wavetable.
Specifically, the accumulator 20 constructs a piecewise straight line:
wherein the content of the first and second substances,y 0 ~y i a line of the segment is represented as a straight line,k 0 ~k i-1 show sequential correspondencey 1 ~y i The value of the slope of (a) is,x 0 ~x i show sequential correspondencey 1 ~y i Linear interpolation of (2).
Accumulating all the segmentation straight lines in sequence:
a plurality of wires
Merging:
to pair
Taking a limit to obtain an initial waveform:
for example, referring to fig. 2, taking 1/4 period of sine wave as an example, the differential control module 10 acquires the wave table and outputs 5 slope values, which are respectivelyk 0 、k 1 、k 2 、k 3 、k 4 (ii) a The accumulator 20 for each slope valuek 0 、k 1 、k 2 、k 3 、k 4 Respectively constructing corresponding segmented straight linesl 0 、l 1 、l 2 、l 3 、l 4 And connecting each sectional straight line in turnl 0 、l 1 、l 2 、l 3 、l 4 To obtain a multi-segment line with a certain rulelTaking the limit of the multiple lines to obtain the initial waveformL。
The digital-to-analog converter 30 is configured to perform digital-to-analog conversion on the initial waveform and output a zero-order hold waveform corresponding to the waveform.
And the filter 40 is used for filtering the zero-order hold waveform and outputting the target waveform after the wavetable is extended.
Specifically, the target waveforms include variable edge waveforms such as sine waves, cosine waves, triangular plates, square waves, trapezoidal waves, and the like.
For example, the differential control module 10 outputs corresponding slope values according to a plurality of received clocks, and each clock is obtained according to a wave table; the accumulator 20 constructs corresponding segment straight lines for each slope value, and sequentially connects the segment straight lines to obtain a multi-segment line with a certain rule; the digital-to-analog converter 30 performs digital-to-analog conversion on the multi-segment line to obtain a zero-order hold waveform; the filter 40 filters the zero order hold waveform to obtain a sinusoidal waveform.
The differential control module acquires the wavetable and outputs a plurality of slope values, the accumulator constructs segmented straight lines according to the slope values, the segmented straight lines are sequentially accumulated, an initial waveform is output, the digital-to-analog converter performs digital-to-analog conversion on the initial model, a zero-order hold waveform is output, the filter filters the zero-order hold waveform, a target waveform is output, and the input of the accumulator is mainly controlled through the differential control module, so that the target waveform is synthesized. The whole waveform synthesis process does not need to store the whole amplitude value of the waveform, so that the occupied space of the wave table is greatly reduced, the utilization rate of the storage space is improved, the storage unit and the storage area are reduced, more wave table contents can be stored under the same resource, and multi-channel waveform synthesis is realized.
In order to make the waveform synthesis system provided by the present disclosure more understandable to those skilled in the art, the above-mentioned waveform synthesis system is exemplified in detail below.
In a possible embodiment, the accumulator 20 is arranged to use piecewise linear interpolation to derive piecewise linear lines based on the slope value.
Specifically, the accumulator accumulates the same frequency control word fcw in a certain number of steps, and piecewise linear interpolation is performed on the basis of the width W1 of the wave table according to the slope value to construct a piecewise straight line.
The accumulator simulates the sine wave based on the piecewise linearity principle, for example, the sine wave is simulated by 4, 8 or 16 straight lines, the wave table depth is reduced, the wave table width is reduced, the storage capacity of the wave table is greatly compressed, all amplitude values of the wave form do not need to be stored, the wave form can be rapidly synthesized, and the synthesis result is reliable.
In a possible embodiment, referring to fig. 3, the differential control module 10 includes a differential wave table address controller 101 and a differential wave table 102, which are in turn communicatively connected, the differential wave table 102 being communicatively connected to the accumulator 20;
a differential wave table address controller 101 for performing counting by accumulating or subtracting according to a received clock;
and the differential wave table 102 is used for outputting a corresponding slope value according to the accumulation or the subtraction of the differential wave table address controller 101.
Specifically, the differential wavetable address controller 101 controls the accumulation or subtraction of the accumulator through the state machine to change the change rule of the wavetable address, thereby realizing the synthesis of the waveform.
Specifically, accumulator 20 converts from accumulation to subtraction or vice versa as frequency control word fcw is shifted. That is, at each clock, when the accumulator 20 is in the accumulation state, the frequency control word fcw changes once, and the accumulator 20 is converted from accumulation to subtraction; at each clock, when the accumulator is in the accumulation state, the frequency control word fcw changes once and the accumulator 20 changes from accumulation to accumulation.
Specifically, the slope value stored in the differential wave table 102 corresponds to 1/4 cycle of the waveform.
According to the method, the slope value output by the differential wavetable is controlled through the counting of the differential wavetable address controller, so that the accumulator is controlled to construct an initial waveform according to the slope value output by the differential wavetable, and the whole process is simple and rapid.
For example, the differential wave table address controller 101 sequentially accumulates, decrements, and counts according to a received clock, the differential wave table 102 sequentially outputs a corresponding first slope value, a second slope value, and a first slope value, the subsequent accumulator 20 sequentially constructs a piecewise straight line for the first slope value, the second slope value, and the first slope value, and sequentially accumulates to obtain a multi-segment line, the digital-to-analog converter 30 performs digital-to-analog conversion on the multi-segment line, and the filter 40 performs filtering to obtain a sinusoidal waveform.
In a possible embodiment, the differential wave table 102 is further configured to store a plurality of slope values of the corresponding wave table in a differential manner.
Specifically, the redundancy of the front and rear data in the wavetable is utilized to store the data in a differential mode, so that the wavetable width is reduced.
For example, the range of data amplitudes at which current data is stored in a non-differential manner is 0-2 12 By a difference ofThe data amplitude azimuth of formula storage is 0-2 5 In the meantime. Therefore, the wave table width is reduced by storing data in a differential mode, and the utilization rate of the wave table is improved.
In a possible embodiment, the depth and width of each wave table in the differential wave table are both an integral power of two.
Specifically, the depth and the width of the wavetable are compressed while the wavetable is stored, and when the waveform is synthesized according to the wavetable, the waveform is synthesized according to the depth and the width of the wavetable.
Wherein, the wave table depth represents the width of the wave table address, represents the number of the data contained in the wave table, and is generally an integral power of two; the wavetable width represents the width of each element of the wavetable, representing the amplitude of each element of the wavetable, typically to the power of two.
In a possible embodiment, the wave form comprises compression multiples, and referring to fig. 3, the waveform synthesis system further comprises a frequency divider module 50, the frequency divider module 50 being communicatively connected to the differential control module 10;
and the frequency dividing module 50 is configured to obtain clocks corresponding to the wavetable, divide the frequencies of the clocks according to the compression multiple, and send the divided multiple clocks to the differential wavetable address controller 101.
Specifically, the frequency division module divides the frequency of the clock sent to the differential wave table address controller, so that a plurality of clocks share the same slope value.
Specifically, the target waveform is compressed according to the compression factor to obtain a wavetable, and the waveform synthesis according to the wavetable needs to be realized according to the compression factor.
Specifically, the frequency division module comprises 2 d Frequency division, d represents the compression bit number of the piecewise linearity, and the wavetable after the piecewise linearity is compressed to 1/(2) d ）。
In a possible embodiment, the wavetable includes a period value of the target waveform, and the frequency dividing module is configured to determine a plurality of clocks corresponding to the wavetable according to the period value, where one period corresponds to four clocks.
For example, when the target waveform includes two cycles, the frequency dividing module divides one cycle into four parts, each part corresponds to one clock, and eight clocks corresponding to the wave table are obtained.
In a possible embodiment, the waveform synthesis system further includes an extraction module, which is configured to intercept the upper bits of the initial waveform according to the width of the dac 30, and send the intercepted initial waveform to the dac 30.
Specifically, referring to fig. 3, the width of the data that can be converted by the dac 30 in an ideal state is generally less than 16 bits, and at 10-12 bits, W2 represents the width of the data that can be actually converted by the dac 30, so W2 is the upper W2 bits of the initial waveform output by the accumulator.
For example, if the data width corresponding to the initial waveform output by the accumulator is 20 bits, and the data width convertible by the digital-to-analog converter is 12 bits, the upper 12 bits of the data corresponding to the initial waveform output by the accumulator are used as the input of the digital-to-analog converter.
In one possible embodiment, the filter 40 comprises a Bessel filter.
In particular, the bessel filter has the flattest amplitude and phase response, and the phase response of the band-pass is nearly linear, so that the nonlinear phase distortion can be reduced. The method also has the characteristic of providing equal time delay for all frequencies below the cut-off frequency of the method, and can eliminate out-of-band noise on the premise of not damaging the phase relation of multiple signals in a frequency band. In addition, the step response of the bessel filter is fast and there is no overshoot or ringing.
Referring to fig. 4 to 7, the present disclosure provides a waveform synthesis system for linearly synthesizing waveforms according to two differential wavetables of 1/16 and 1/32, respectively, wherein the compression ratio of the wavetable of 1/32 reaches 128.
Based on the same inventive concept, the disclosure also provides a chip comprising the waveform synthesis system.
In the method, a difference control module acquires a wavetable and outputs a plurality of slope values, an accumulator constructs segmented straight lines according to the slope values, the segmented straight lines are sequentially accumulated, an initial waveform is output, a digital-to-analog converter performs digital-to-analog conversion on the initial model, a zero-order hold waveform is output, a filter filters the zero-order hold waveform, a target waveform is output, and the input of the accumulator is controlled mainly through the difference control module, so that the target waveform is synthesized. The whole waveform synthesis process does not need to store the whole amplitude value of the waveform, so that the occupied space of the wave table is greatly reduced, the utilization rate of the storage space is improved, the storage unit and the storage area are reduced, more wave table contents can be stored under the same resource, and multi-channel waveform synthesis is realized.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. A waveform synthesis system, comprising: the differential control module, the accumulator, the digital-to-analog converter and the filter are sequentially in communication connection;
the differential control module is used for outputting corresponding slope values according to a plurality of received clocks, and each clock is obtained according to a wave table;
the accumulator is used for respectively constructing segmented straight lines aiming at each slope value, sequentially accumulating the segmented straight lines and outputting initial waveforms corresponding to the wave table;
the digital-to-analog converter is used for performing digital-to-analog conversion on the initial waveform and outputting a zero-order hold waveform corresponding to the wavetable;
and the filter is used for filtering the zero-order hold waveform and outputting the target waveform after the wavetable is extended.
2. The waveform synthesis system of claim 1, wherein the accumulator is configured to derive the piecewise linear line using piecewise linear interpolation based on the slope value.
3. The waveform synthesis system according to claim 1, wherein the differential control module comprises a differential wavetable address controller and a differential wavetable, which are in communication connection in sequence, the differential wavetable being in communication connection with the accumulator;
the differential wave table address controller is used for carrying out counting according to the accumulation or the subtraction of the received clock;
and the differential wave table is used for outputting a corresponding slope value according to the accumulation or the subtraction of the differential wave table address controller.
4. The waveform synthesis system of claim 3, wherein the differential wavetable is further configured to differentially store a plurality of slope values corresponding to the wavetable.
5. The waveform synthesis system of claim 4, wherein the depth and width of each of the differential wavetables are an integral power of two.
6. The waveform synthesis system of claim 3, wherein the wavetable includes a compression multiple, the waveform synthesis system further comprising a frequency divider module communicatively coupled to the differential control module;
the frequency division module is used for acquiring clocks corresponding to the wavetable, dividing the frequency of each clock according to the compression multiple, and sending the divided clocks to the differential wavetable address controller.
7. The waveform synthesis system of claim 6, wherein the wavetable includes a period value of the target waveform, and the frequency division module is configured to determine a plurality of clocks corresponding to the wavetable according to the period value, wherein a period corresponds to four clocks.
8. The waveform synthesis system of claim 1, further comprising an extraction module configured to intercept the high order bits of the initial waveform according to the width of the dac, and send the intercepted initial waveform to the dac.
9. The waveform synthesis system of claim 1, wherein the filter comprises a Bezier filter.
10. A chip comprising the waveform synthesis system of any one of claims 1-9.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807089A (en) * | 2010-04-02 | 2010-08-18 | 广西大学 | Waveform signal generator with optionally adjustable output signal offset |
| CN108055042A (en) * | 2017-10-31 | 2018-05-18 | 华北电力大学（保定） | Discrete waveform data compression method based on slope distribution |
| CN110471038A (en) * | 2019-08-16 | 2019-11-19 | 上海英恒电子有限公司 | A kind of Waveform generating method and device of millimetre-wave radar |
| US20200195260A1 (en) * | 2018-12-18 | 2020-06-18 | Seiko Epson Corporation | Circuit device, oscillator, electronic apparatus and moving object |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807089A (en) * | 2010-04-02 | 2010-08-18 | 广西大学 | Waveform signal generator with optionally adjustable output signal offset |
| CN108055042A (en) * | 2017-10-31 | 2018-05-18 | 华北电力大学（保定） | Discrete waveform data compression method based on slope distribution |
| US20200195260A1 (en) * | 2018-12-18 | 2020-06-18 | Seiko Epson Corporation | Circuit device, oscillator, electronic apparatus and moving object |
| CN110471038A (en) * | 2019-08-16 | 2019-11-19 | 上海英恒电子有限公司 | A kind of Waveform generating method and device of millimetre-wave radar |
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