CN115811237A - Synchronous rectification control circuit and control method - Google Patents
Synchronous rectification control circuit and control method Download PDFInfo
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Abstract
A synchronous rectification control circuit and a control method are provided, and relate to the technical field of synchronous rectification. The control circuit includes: the current acquisition circuit is used for acquiring the working current of the transformer coil and outputting an alternating current signal according to the working current; the logic driving circuit is electrically connected with the current acquisition circuit and used for generating a first logic signal and a second logic signal according to the received alternating current signal and respectively outputting a first control signal and a second control signal based on the first logic signal and the second logic signal, wherein the first control signal and the second control signal are used for controlling the synchronous rectifier bridge to rectify the current output by the secondary coil of the transformer; and the self-locking circuit is electrically connected with the logic driving circuit and is used for locking the first logic signal and the second logic signal in the half-cycle of the operation of the synchronous rectifier bridge. And a hardware circuit is used for generating a driving signal of the synchronous rectifier bridge, so that accurate control is realized, and the design difficulty is reduced. The self-locking circuit can prevent the upper and lower switching tubes from being directly communicated due to external interference.
Description
Technical Field
The invention relates to the technical field of synchronous rectification, in particular to a synchronous rectification control current and a control method thereof.
Background
The synchronous rectification technology is a very common technology applied to the field of switching power supplies at present, and a metal oxide semiconductor field effect transistor (MOSFET tube, abbreviated as MOS tube) with extremely low on-state resistance is adopted to replace a diode so as to reduce the rectification loss.
When the forward current flows from the source electrode to the drain electrode of the MOS tube, the MOS tube is driven to be opened by a Pulse Width Modulation (PWM) signal, and the conduction internal resistance of the MOS tube is far smaller than the forward voltage drop of the diode. When reverse current flows from the source electrode to the drain electrode of the MOS tube, the MOS tube is driven by PWM to be switched off, and the reverse current is cut off.
The traditional synchronous rectification driving technology adopts a preset programming mode, and utilizes a program algorithm to generate a PWM signal to realize the control of a synchronous rectification bridge, but the mode has the problem of high early design difficulty. Or, an MOS tube voltage drop detection mode is adopted, the body diode conduction voltage drop of the MOS tube and the conduction voltage drop of the MOS tube in an on state are detected, and the body diode conduction voltage drop and the conduction voltage drop of the MOS tube in an on state are compared with a set threshold value to control the on-off of the MOS tube. This approach presents a significant challenge to the accuracy of the detection. Furthermore, a slope prediction mode can be adopted, and the turn-off time of the synchronous rectification in the current period is adjusted and controlled by a specific prediction algorithm according to the time sequence relation between the Vds slope and the relative Vgs of the MOS tube in the previous period. The synchronous rectification driving of the mode under the dynamic condition is insufficient, and the conversion efficiency is seriously influenced.
Therefore, a circuit and a method for controlling synchronous rectification precisely and reliably are needed, so as to be widely applicable to the field of switching power supplies.
Disclosure of Invention
The present application aims to provide a synchronous rectification control circuit and a control method to improve the control precision of synchronous rectification and realize accurate and reliable control of on and off of a switching tube during synchronous rectification, in order to overcome the disadvantages of high complexity of driver design, low detection precision of MOS transistor voltage, low driving conversion efficiency, etc. in synchronous rectification control in the prior art.
The application discloses synchronous rectification control circuit includes: the current acquisition circuit is used for acquiring the working current of the transformer coil and outputting an alternating current signal according to the working current; the logic driving circuit is electrically connected with the current acquisition circuit and is used for generating a first logic signal and a second logic signal according to the received alternating current signal and respectively outputting a first control signal and a second control signal based on the first logic signal and the second logic signal, wherein the first control signal and the second control signal are used for controlling a synchronous rectifier bridge, and the synchronous rectifier bridge is connected with a transformer secondary coil of a transformer so that the synchronous rectifier bridge rectifies current output by the transformer secondary coil; and the self-locking circuit is electrically connected with the logic driving circuit and is used for locking the first logic signal and the second logic signal in the half-cycle of the operation of the synchronous rectifier bridge.
Further, the synchronous rectification control circuit further includes: an interlock circuit electrically connected to the logic driving circuit; the interlock circuit includes: the first interlocking circuit is used for outputting a first interlocking signal according to the first logic signal so as to lock the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge; and a second interlock circuit for outputting a second interlock signal according to the second logic signal to latch the first logic signal during a half-cycle of the operation of the synchronous rectifier bridge.
Further, the current collecting circuit comprises a current transformer, a primary coil of the current transformer is connected with the transformer coil in series, a secondary coil of the current transformer is electrically connected with the logic driving circuit, and the transformer coil is a transformer primary coil or a transformer secondary coil.
Further, the logic driving circuit comprises a rectifying unit electrically connected with the current collecting circuit and used for outputting a first voltage signal and a second voltage signal according to the alternating current signal; the first logic unit is electrically connected with the rectifying unit and used for outputting a first logic signal according to the first voltage signal; the second logic unit is electrically connected with the rectifying unit and used for outputting a second logic signal according to the second voltage signal; and the driving unit is respectively electrically connected with the first logic unit and the second logic unit and is used for outputting a first control signal according to the first logic signal and outputting a second control signal according to the second logic signal.
Further, the rectifying unit includes a first diode, a second diode, a third diode, and a fourth diode; the first diode and the fourth diode are connected in series, the second diode and the third diode are connected in series, a common node of the first diode and the fourth diode is electrically connected with a first end of the current acquisition circuit and the first logic unit, a common node of the second diode and the third diode is electrically connected with a second end of the current acquisition circuit and the second logic unit, an anode of the fourth diode and an anode of the third diode are respectively connected with the ground, and a cathode of the first diode and a cathode of the second diode are electrically connected and are connected with the ground through a first resistor.
Further, the first logic unit comprises a first triode, a second resistor and a third resistor; the collector of the first triode is electrically connected with the rectifying unit, the base of the first triode is electrically connected with the base of the second triode, the emitter of the first triode is electrically connected with the self-locking circuit, the base and the collector of the second triode are respectively connected with the power supply through the second resistor and the third resistor, the base of the second triode is electrically connected with the emitter of the first triode, the emitter of the second triode is electrically connected with the ground, and the collector of the second triode is used for outputting a first logic signal.
Further, the second logic unit includes a fifth triode, a sixth triode, a seventh resistor and an eighth resistor; the collector of the fifth triode is electrically connected with the rectifying unit, the base of the fifth triode is electrically connected with the base of the sixth triode, the emitter of the fifth triode is electrically connected with the self-locking circuit, the base and the collector of the sixth triode are respectively connected with the power supply through the seventh resistor and the eighth resistor, the base of the sixth triode is electrically connected with the emitter of the fifth triode, the emitter of the sixth triode is electrically connected with the ground, and the collector of the sixth triode is used for outputting a second logic signal.
Further, the self-locking circuit comprises a first self-locking circuit and a second self-locking circuit, the first self-locking circuit comprises a fourth resistor and a fourth MOS (metal oxide semiconductor) transistor, the second self-locking circuit comprises a ninth resistor and an eighth MOS transistor, the fourth resistor and the fourth MOS transistor are connected between the first logic unit and the ground in series, the ninth resistor and the eighth MOS transistor are connected between the second logic unit and the ground in series, the grid electrode of the fourth MOS transistor is connected to the output end of the first logic unit, which outputs the first logic signal, and the grid electrode of the eighth MOS transistor is connected to the output end of the second logic unit, which outputs the second logic signal.
Further, the first interlock circuit comprises a third MOS transistor, a fifth resistor and a sixth resistor; the drain electrode of the third MOS tube is electrically connected with the logic driving circuit and used for outputting a first interlocking signal, the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is grounded through a sixth resistor and receives a second interlocking signal through a fifth resistor.
Further, the second interlock circuit comprises a seventh MOS transistor, a tenth resistor and an eleventh resistor; the drain electrode of the seventh MOS tube is electrically connected with the logic driving circuit and used for outputting a second interlocking signal, the source electrode of the seventh MOS tube is grounded, and the grid electrode of the seventh MOS tube is grounded through a tenth resistor and receives the first interlocking signal through an eleventh resistor.
Further, the drain of the third MOS transistor outputs a first interlock signal through a sixth diode.
Further, the drain of the seventh MOS transistor outputs a second interlock signal through an eighth diode.
Further, the driving unit includes a logic circuit, and the logic circuit is electrically connected to the first logic unit and the second logic unit, and is configured to output the first control signal after performing logic operation on the first logic signal, and output the second control signal after performing logic operation on the second logic signal.
Further, the first resistor is a current sampling resistor, and the current sampling resistor is used for collecting a current signal of the rectifying unit.
The application also discloses a synchronous rectification control method, which comprises the steps of collecting the working current of a transformer coil through a current collecting circuit, and outputting an alternating current signal according to the working current; receiving the alternating current signal through a rectifying unit to output a first voltage signal and a second voltage signal; receiving, by a logic unit, the first voltage signal and the second voltage signal to output a first logic signal and a second logic signal; outputting a first control signal and a second control signal based on the first logic signal and the second logic signal through a driving unit, wherein the first control signal and the second control signal are used for controlling a synchronous rectifier bridge to rectify current output by a secondary coil of a transformer; and locking the first logic signal and the second logic signal in the half-cycle of the operation of the synchronous rectifier bridge through a self-locking circuit.
Further, the method further comprises outputting, by a first interlock circuit, a first interlock signal according to the first logic signal to latch the second logic signal during a half-cycle of operation of the synchronous rectifier bridge; and outputting a second interlocking signal according to the second logic signal through a second interlocking circuit so as to lock the first logic signal in a half-cycle of the operation of the synchronous rectifier bridge.
Further, the method further includes receiving, by the rectifying unit, the alternating current signal to output a first current signal and a second current signal, and detecting the first current signal and the second current signal.
The application can realize at least one of the following beneficial effects: the application provides a synchronous rectification control circuit, it includes current acquisition circuit, logic drive circuit and self-locking circuit. And a control signal of the synchronous rectifier bridge is generated by means of a hardware circuit. In addition, the self-locking circuit can lock the driving signal generated by the logic driving circuit in the half-cycle of the synchronous rectifier bridge, prevent the switching tubes in the synchronous rectifier bridge from being conducted by mistake due to external interference (for example, the upper and lower switching tubes in the bridge arm of the rectifier bridge are conducted simultaneously to cause direct connection and short circuit of the bridge arm), and realize accurate control of the synchronous rectifier bridge. In addition, the logic driving circuit can also prevent the rectifier bridge from generating reverse current due to instantaneous electromotive force by closing a switching tube in the synchronous rectifier bridge.
The foregoing has outlined rather broadly the features and technical advantages of the present application in order that the detailed description of the application that follows may be better understood. Additional features and advantages of the application will be described hereinafter which form the subject of the claims of the application. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present application. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the application as set forth in the appended claims.
Drawings
For a more complete understanding of the present application and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
fig. 1 shows a block diagram of a synchronous rectification control circuit according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a synchronous rectification control circuit according to an embodiment of the present application;
FIG. 3 is a first schematic diagram illustrating a first partial circuit connection of a synchronous rectification control circuit according to an embodiment of the present application;
fig. 4 illustrates a second partial circuit connection diagram of the synchronous rectification control circuit according to an embodiment of the present application;
FIG. 5 is a first schematic diagram illustrating a first partial circuit connection of a synchronous rectification control circuit according to another embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a second circuit connection of a portion of a synchronous rectification control circuit according to another embodiment of the present application;
FIG. 7 illustrates a schematic diagram of a drive unit provided by an embodiment of the present application;
FIG. 8 is a schematic circuit diagram of a synchronous rectification system according to an embodiment of the present application;
FIG. 9 illustrates a runtime timing diagram of a synchronous rectification system provided by an embodiment of the present application;
fig. 10 shows a flowchart of a synchronous rectification control method according to an embodiment of the present application.
Corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn for clarity in illustrating relevant aspects of various embodiments and are not necessarily drawn to scale.
Description of the preferred embodiment
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a block diagram illustrating a synchronous rectification control circuit according to an embodiment of the present disclosure. As shown in fig. 1, the synchronous rectification control circuit 10 includes a current collection circuit 100, a logic driving circuit 200, and a self-locking circuit 300.
The current collection circuit 100 is electrically connected to the transformer 600 and the logic driving circuit 200, and the logic driving circuit 200 is electrically connected to the self-locking circuit 300 and the synchronous rectifier bridge 500.
Specifically, the current collection circuit 100 collects the working current of the coil of the transformer 600 and outputs an ac signal according to the working current. Then, the logic driving circuit 200 generates a first logic signal and a second logic signal according to the ac signal, and outputs a first control signal and a second control signal based on the first logic signal and the second logic signal, respectively, to control the synchronous rectifier bridge 500 to rectify the current output from the secondary winding of the transformer 600. The self-locking circuit 300 locks the first logic signal and the second logic signal during a half cycle of the synchronous rectifier bridge 500.
Compared with the traditional synchronous rectification driving technology, the synchronous rectification control circuit provided by the embodiment of the application does not need complex program design, and depends on a hardware circuit to generate the driving signals (the first control signal and the second control signal) of the synchronous rectification bridge 500 to realize accurate synchronous rectification control, so that the design difficulty of the synchronous rectification control technology is reduced. And moreover, the self-locking circuit can prevent the upper and lower switching tubes of the synchronous rectifier bridge from being directly connected to damage a power device due to external interference.
In one embodiment of the present application, the current collecting circuit 100 includes a current transformer CT, a primary coil of the current transformer CT is connected in series with a coil of a transformer 600, a secondary coil of the current transformer CT is electrically connected with the logic driving circuit 200, and the coil of the transformer 600 is a primary coil or a secondary coil of the transformer. Specifically, the current transformer CT may collect an operating current of a primary coil or a secondary coil of the transformer 600 and output an ac signal according to the operating current.
In addition, in one embodiment of the present application, the synchronous rectification control circuit 10 further includes an interlock circuit 400. The interlock circuit 400 is electrically connected to the logic driving circuit 200. Specifically, the interlock circuit 400 outputs a first interlock signal and a second interlock signal according to the first logic signal and the second logic signal, respectively. The first interlock signal locks the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge 500; the second interlock signal latches the first logic signal during a half-cycle of the synchronous rectifier bridge 500 operation. The first interlocking signal and the second interlocking signal are generated through the interlocking circuit, the synchronous rectification control circuit can achieve more accurate and reliable synchronous rectification control, and the anti-interference performance of the circuit and the error conduction prevention of the circuit are improved. The upper and lower switching tubes of the synchronous rectifier bridge are prevented from being directly conducted due to external signal interference, and therefore the switching tubes are prevented from being damaged.
Referring to fig. 2, fig. 2 is a circuit connection diagram of a synchronous rectification control circuit according to an embodiment of the present disclosure. As shown in fig. 2, the logic driving circuit 200 includes a rectifying unit 201, a first logic unit 202, a second logic unit 203, and a driving unit 204.
The rectifying unit 201 is electrically connected to the current collecting circuit 100, and since the current collecting circuit 100 outputs an alternating current signal, the rectifying unit 201 generates a first current signal and a second current signal according to the alternating current signal, wherein the current flow directions of the first current signal and the second current signal are different. The rectifying unit 201 outputs a first voltage signal and a second voltage signal at two nodes of the current loop.
The first logic unit 202 is electrically connected to the rectifying unit 201, and is configured to receive the first voltage signal output by the rectifying unit 201 and output a first logic signal according to the first voltage signal. The second logic unit 203 is electrically connected to the rectifying unit 201, and is configured to receive the second voltage signal output by the rectifying unit 201 and output a second logic signal according to the second voltage signal.
The driving unit 204 is electrically connected to the first logic unit 202 and the second logic unit 203, respectively, receives the first logic signal and the second logic signal, outputs a first control signal according to the first logic signal, and outputs a second control signal according to the second logic signal. The first control signal and the second control signal jointly control the synchronous rectifier bridge, so that the synchronous rectifier bridge can rectify the current output by the secondary coil of the transformer.
As shown in fig. 2, the latch circuit 300 includes a first latch circuit 301 and a second latch circuit 302. The first latch circuit 301 is electrically connected to the first logic circuit 202, and latches the first logic signal during the period when the rectifying unit 201 generates the first current and during the period when the rectifying unit generates the second current. The second latch circuit 302 is electrically connected to the second logic circuit 203, and latches the second logic signal during the period in which the rectifying unit 201 generates the first current and during the period in which the second current is generated.
In one embodiment, the synchronous rectification control circuit further comprises an interlock circuit 400 comprising a first interlock circuit 401 and a second interlock circuit 402.
Examples of circuit connections and operating principles of the first logic unit, the second logic unit, the self-locking circuit, and the interlock circuit will be described in detail below.
In one embodiment, as shown in fig. 2, the rectifying unit 201 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first resistor R1. The first diode D1 and the fourth diode D4 are connected in series between the bus and the ground line, the second diode D2 and the third diode D3 are connected in series between the bus and the ground line, and the first resistor R1 is connected between the bus and the ground line. The junction of the first resistor R1 and the bus can be used as a voltage detecting terminal to detect the voltage Vsns in the circuit loop of the rectifying unit 201. A common node CTA of the first diode D1 and the fourth diode D4 is electrically connected to the first terminal of the current collection circuit 100, and a common node CTB of the second diode D2 and the third diode D3 is electrically connected to the first terminal of the current collection circuit 100. The common node CTA and the common node CTB are electrically connected to the first logic unit 202 and the second logic unit 203, respectively, for outputting a first voltage signal and a second voltage signal.
Specifically, since the current collection circuit 100 (e.g., the current transformer CT) collects the operating current of the transformer 600 to output the ac signal, the rectification unit 201 periodically generates the first current signal and the second current signal according to the ac signal. When the rectifying unit 201 generates the first current signal, the generated first current signal gradually increases from zero to a peak current, and then gradually decreases from the peak current to zero. When the first current signal is decreased from the peak current to zero, the rectifying unit 201 starts to generate the second current signal, and the generated second current signal gradually increases from zero to the peak current and then gradually decreases from the peak current to zero. Thus, the rectifying unit 201 generates periodic first and second current signals from the alternating current signal, and outputs first and second voltage signals at the node CTA and the node CTB. The first voltage signal and the second voltage signal may control the first logic unit 202 and the second logic unit 203, respectively, so that the first logic unit 202 outputs the first logic signal and the second logic unit 203 outputs the second logic signal.
Illustratively, when the rectifying unit 201 generates the first current signal, the second diode D2, the first resistor R1, and the fourth diode D4 form a path. The first logic unit 202 receives the first voltage signal at a node CTA and outputs the first logic signal as a high level signal, and the second logic unit 203 receives the second voltage signal at a node CTB and outputs the second logic signal as a low level signal. When the rectifying unit 201 generates the second current signal, the first diode D1, the first resistor R1, and the third diode D3 form a path. The first logic unit 202 receives the first voltage signal at the node CTA and outputs the first logic signal as a low level signal, and the second logic unit 203 receives the second voltage signal at the node CTB and outputs the second logic signal as a high level signal.
The first resistor R1 may serve as a sampling resistor to detect a first current and a second current in the rectifying unit 201 for controlling the synchronous rectifying bridge.
Referring to fig. 3 and fig. 4, fig. 3 shows a first partial circuit connection diagram of the synchronous rectification control circuit provided in an embodiment of the present application, and fig. 4 shows a second partial circuit connection diagram of the synchronous rectification control circuit provided in an embodiment of the present application.
As shown in fig. 3, the first logic unit 202 includes a first transistor Q1, a second transistor Q2, a second resistor R2, and a third resistor R3. The collector of the first triode Q1 is electrically connected with the node CTA of the rectifying unit 201, the base of the first triode Q1 is electrically connected with the base of the second triode Q2, the emitter of the first triode Q1 is electrically connected with the first self-locking circuit 301, the base and the collector of the second triode Q2 are respectively connected with the power supply Vcc through the second resistor R2 and the third resistor R3, the base of the second triode Q2 is electrically connected with the emitter of the first triode Q1, the emitter of the second triode Q2 is electrically connected with the ground, the collector of the second triode Q2 is electrically connected with the driving unit, so as to output the first logic signal.
The first self-locking circuit 301 includes a fourth resistor R4 and a fourth MOS transistor Q4. As shown in fig. 3, the fourth resistor R4 and the fourth MOS transistor Q4 are connected in series between the emitter of the first transistor Q1 and the ground, and the gate of the fourth MOS transistor Q4 is connected to the collector of the second transistor Q2.
As shown in fig. 4, the second logic unit 203 includes a fifth transistor Q5, a sixth transistor Q6, a seventh resistor R7, and an eighth resistor R8. A collector of the fifth triode Q5 is electrically connected with the node CTB of the rectifying unit 201, a base of the fifth triode Q5 is electrically connected with a base of the sixth triode Q6, an emitter of the fifth triode Q5 is electrically connected with the second self-locking circuit 302, the base and the collector of the sixth triode Q6 are respectively connected with the power supply Vcc through a seventh resistor R7 and an eighth resistor R8, the base of the sixth triode Q6 is electrically connected with the emitter of the fifth triode Q5, the emitter of the sixth triode Q6 is electrically connected with the ground, and the collector of the sixth triode Q6 is electrically connected with the driving unit to output the second logic signal.
The second self-locking circuit 302 includes a ninth resistor R9 and an eighth MOS transistor Q8. As shown in fig. 4, a ninth resistor R9 and an eighth MOS transistor Q8 are connected in series between the emitter of the fifth transistor Q5 and ground, and a gate of the ninth MOS transistor Q9 is connected to a collector of the sixth transistor Q6.
Specifically, when the rectifying unit 201 generates the first current signal, the second diode D2, the first resistor R1, and the fourth diode D4 form a path. The first current signal gradually increases from zero to a peak current and then decreases from the peak current to zero. When the first current exceeds the first threshold current, due to the conduction voltage drop of the fourth diode D4, the first voltage signal at CTA becomes-0.7V with respect to ground, and the first transistor Q1 is turned on from base to collector, and the current loop is from + Vcc through base to collector. At this time, the base voltage of the first transistor Q1 is about 0V. Since the emitter of the second transistor Q2 is grounded, the collector of the second transistor Q2 is cut off from the emitter to the collector, and the collector of Q2 is at a high level, i.e., the first logic signal S _ SRDRVA output by the first logic unit 202 is a high level signal.
When the first logic signal S _ SRDRVA is a high level signal, and the gate of the fourth MOS transistor Q4 in the self-locking circuit 301 is also a high level, the transistor Q4 is turned on, so that the base potential of the second transistor Q2 is pulled low through the fourth resistor R4, and the second transistor Q2 is turned off to maintain the first logic signal S _ SRDRVA output as a high level, thereby forming self-locking.
When the first current signal is generated, the third diode D3 is turned off in the reverse direction so that the second voltage signal at CTB is at a high level with respect to ground, and the fifth transistor Q5 is turned off from the base to the collector. At this time, the base of the sixth triode Q6 is at a high level, and the collector to the emitter of the sixth triode Q6 are turned on, i.e. the second logic signal S _ SRDRVB output by the second logic unit 203 is a low level signal.
When the second logic signal S _ SRDRVB is output as a low level signal, and the gate of the eighth MOS transistor Q8 in the self-locking circuit 302 is also at a low level, the transistor Q8 is turned off, so that the base potential of the sixth transistor Q6 is maintained at a high level, and the transistor Q6 is turned on, so that the output of the second logic signal S _ SRDRVB is still at a low level, thereby forming self-locking.
Likewise, when the rectifying unit 201 generates the second current signal, the first diode D1, the first resistor R1, and the third diode D3 form a path. The second current signal gradually increases from zero to a peak current and then decreases from the peak current to zero. When the second current signal exceeds the second threshold current, the second voltage signal at CTB becomes-0.7V with respect to ground due to the conduction voltage drop of the third diode D3, and the fifth transistor Q5 is turned on from the base to the collector, and the current loop is from + Vcc to the collector through the base of Q5. At this time, the base voltage of the fifth transistor Q5 is about 0V. Since the emitter of the sixth transistor Q6 is grounded, the collector of the sixth transistor Q6 is cut off from the emitter to the collector, and the collector of Q6 is at a high level, i.e., the second logic signal S _ SRDRVB output by the second logic unit 203 is a high level signal.
When the second logic signal S _ SRDRVB is output as a high level signal, the gate of the eighth MOS transistor Q8 in the self-locking circuit 302 is also at a high level, and then Q8 is turned on, so that the base potential of the sixth transistor Q6 is pulled low through the ninth resistor R9, and the sixth transistor Q6 is turned off to maintain the output of the second logic signal S _ SRDRVB as a high level, thereby forming self-locking.
When the second current signal is generated, the fourth diode D4 is turned off in the reverse direction so that the first voltage signal at CTA is high with respect to ground, and the first transistor Q1 is turned off from the base to the collector. At this time, the base of the second transistor Q2 is at a high level, and the collector to the emitter of the second transistor Q2 are turned on, i.e. the first logic signal S _ SRDRVA output by the first logic unit 202 is a low level signal.
When the first logic signal S _ SRDRVA is a low level signal, and the gate of the fourth MOS transistor Q4 in the self-locking circuit 301 is also a low level, the gate of the fourth MOS transistor Q4 is turned off, so that the base potential of the second transistor Q2 is maintained at a high level, and the gate of the fourth MOS transistor Q4 is turned on, so that the first logic signal S _ SRDRVA is still a low level, thereby forming self-locking.
In one embodiment, as shown in fig. 3, a fifth diode D5 is disposed between the collector and the base of the second transistor Q2. When the fifth diode D5 is turned on, a part of the base current of the second triode Q2 is shunted to the collector to reduce the base current stress, and the base voltage VBE of the second triode Q2 is clamped at about 0.7V, so that the VBE of the second triode Q2 is prevented from continuously rising to cause the Q2 to enter a deep saturation region.
In one embodiment, as shown in fig. 4, a seventh diode D7 is disposed between the collector and the base of the sixth triode Q6. When the seventh diode D7 is turned on, a part of the base current of the sixth triode Q6 is shunted to the collector to reduce the base current stress, and the base voltage VBE of the sixth triode Q6 is clamped at about 0.7V, so that the situation that the Q6 enters a deep saturation region due to the continuous rise of VBE of the sixth triode Q6 is avoided.
Referring to fig. 5 and fig. 6, fig. 5 shows a first partial circuit connection diagram of a synchronous rectification control circuit provided in another embodiment of the present application, and fig. 6 shows a second partial circuit connection diagram of the synchronous rectification control circuit provided in another embodiment of the present application.
As shown in fig. 5, the synchronously rectified control current 10 further includes a first interlock circuit 401. The first interlock circuit 401 includes a third MOS transistor Q3, a fifth resistor R5, and a sixth resistor R6. The drain of the third MOS transistor Q3 is electrically connected to the collector of the second transistor Q2 in the first logic unit 202 to output the first interlock signal P _ DRVA having the same level as the first logic signal S _ SRDRVA. The source of the third MOS transistor Q3 is grounded, and the gate of the third MOS transistor Q3 is grounded via a sixth resistor R6 and receives the second interlock signal P _ DRVB via a fifth resistor R5.
As shown in fig. 6, the synchronously rectified control current 10 further includes a second interlock circuit 402. The second interlock circuit 402 includes a seventh MOS transistor Q7, a tenth resistor R10, and an eleventh resistor R11. The drain of the seventh MOS transistor Q7 is electrically connected to the collector of the sixth transistor Q6 in the second logic unit 203 to output the second interlock signal P _ DRVB which is the same level signal as the second logic signal S _ SRDRVB. The source of the seventh MOS transistor Q7 is grounded, and the gate of the seventh MOS transistor Q7 is grounded via an eleventh resistor R11 and receives the first interlock signal P _ DRVA via a tenth resistor R10.
The first interlock circuit is used for outputting a first interlock signal according to the first logic signal so as to lock the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge. The second interlocking circuit is used for outputting a second interlocking signal according to the second logic signal so as to lock the first logic signal in a half-cycle of the operation of the synchronous rectifier bridge. Specifically, when the first current signal generated by the rectifying unit 201 exceeds the first current threshold, the first logic unit 202 outputs the first logic signal S _ SRDRVA as a high level. At this time, the first interlock signal P _ DRVA output by the first interlock circuit 401 is also high level. The second interlock circuit 402 receives the high-level first interlock signal, so that the seventh MOS transistor Q7 is turned on, and the second logic signal S _ SRDRVB outputted by the second logic unit 203 is maintained at a low level. Likewise, when the first current signal generated by the rectifying unit 201 exceeds the first current threshold, the second logic unit 203 outputs the second logic signal S _ SRDRVB as a low level. At this time, the second interlock signal P _ DRVB output by the second interlock circuit 402 is also low. The first interlock circuit 401 receives the low-level second interlock signal, so that the fifth MOS transistor Q5 is turned off, and the first logic signal S _ SRDRVA output by the first logic unit 202 is maintained at a high level. Finally, the effect that the first logic signal and the second logic signal are locked with each other is achieved. When the second current signal generated by the rectifying unit 201 exceeds the second current threshold, the effect similar to the interlock can be achieved through the first interlock circuit and the second interlock circuit, which is not repeated herein.
In one embodiment, as shown in fig. 5, the first interlock circuit 401 further includes a sixth diode D6 electrically connected between the drain of the third MOS transistor Q3 and the output terminal of the first interlock signal P _ DRVA. When the first interlock signal P _ DRVA is not outputted, the sixth diode D6 can pull down the potential of the first logic signal S _ SRDRVA to prevent the first logic signal from being disturbed and being triggered by mistake.
In one embodiment, as shown in fig. 6, the second interlock circuit 402 further includes an eighth diode D8 electrically connected between the drain of the seventh MOS transistor Q7 and the output terminal of the second interlock signal P _ DRVB. When the second interlock signal P _ DRVB is not outputted, the eighth diode D8 can pull down the potential of the second logic signal S _ SRDRVB to prevent the second logic signal from being disturbed and being triggered by mistake.
Returning to fig. 2, in one embodiment of the present application, the drive unit 204 includes logic circuitry. Fig. 7 shows a schematic diagram of a driving unit provided in an embodiment of the present application. As shown in fig. 2 and 7, the driving unit 204 is electrically connected to the first logic unit 202 and the second logic unit 203, and is configured to output the first control signal SR _ PWMA after performing a logic operation on the first logic signal S _ SRDRVA, and output the second control signal SR _ PWMB after performing a logic operation on the second logic signal S _ SRDRVB.
Specifically, when the first logic signal S _ SRDRVA is at a low level, the first control signal SR _ PWMA output after the logic circuit operation is a low level signal; when the first logic signal S _ SRDRVA is a high level signal, the first control signal SR _ PWMA output after the logic circuit operation is a high level signal. When the second logic signal S _ SRDRVB is at a low level, the second control signal SR _ PWMB output after the logic circuit operation is a low level signal; when the second logic signal S _ SRDRVB is a high level signal, the second control signal SR _ PWMB output after the logic circuit operation is a high level signal.
Referring to fig. 8, fig. 8 is a circuit connection diagram of a synchronous rectification system according to an embodiment of the present disclosure. As shown in fig. 8, the synchronous rectification system includes a power supply circuit 700, a transformer 600, a current collection circuit 100, a logic driving circuit 200, a synchronous rectification bridge 500, a self-locking circuit 300, and an interlock circuit 400.
The power supply circuit 700 includes a power supply Vcc, a first switch tube S1, a second switch tube S2, a first inductor Lr, a second inductor Lm, and a first capacitor Cr. The drain electrode of the first switch tube S1 is connected to the power supply Vcc, and the source electrode of the first switch tube S1 is electrically connected to the first end of the first inductor Lr and the drain electrode of the second switch tube S2, respectively. A first end of the primary coil of the transformer 600 is electrically connected to a second end of the first inductor Lr and a first end of the second inductor Lm, respectively, and a second end of the primary coil of the transformer 600 is electrically connected to a second end of the second inductor Lm and a first end of the first capacitor Cr, respectively. The second end of the first capacitor Cr is electrically connected to the source and the ground of the second switch tube S2, respectively. In another embodiment, the power supply circuit 700 does not include the second inductor Lm and the first capacitor Cr described above. A first end of the primary coil of the transformer 600 is connected to a second end of the first inductor Lr, and a second end of the primary coil of the transformer 600 is electrically connected to a source and a ground of the second switching tube S2.
The current acquisition circuit 100 includes a current transformer CT that may be connected in series with the primary or secondary of the transformer 600, as shown in fig. 8, which shows the current transformer CT connected in series with the secondary of the transformer 600.
The synchronous rectifier bridge 500 includes a third switching tube S3, a fourth switching tube S4, a fifth switching tube S5, a sixth switching tube S6 and a second capacitor Co. The drain electrode of the third switching tube S3 is electrically connected with the drain electrode of the fourth switching tube S4 and the first end of the second capacitor Co, respectively, and the source electrode of the third switching tube S3 is electrically connected with the current transformer CT and the drain electrode of the sixth switching tube S6, respectively. The source electrode of the fourth switching tube S4 is electrically connected with the drain electrode of the fifth switching tube S5 and the secondary coil of the transformer T, respectively. The source of the fifth switching tube S5 is electrically connected to the source of the sixth switching tube S6 and the second end of the second capacitor Co, respectively.
The logic driving circuit 200 includes the rectifying unit 201, the first logic unit 202, the second logic unit 203, and the driving unit 204 described above. The logic driving circuit 200 is connected to the self-locking circuit 300 and the interlock circuit 400. A first output terminal of the logic driving circuit 200 is electrically connected to the gates of the third switching tube S3 and the fifth switching tube S5, respectively, for outputting the first control signal SR _ PWMA. A second output terminal of the logic driving circuit 200 is electrically connected to the gate of the fourth switching tube S4 and the gate of the sixth switching tube S6, respectively, for outputting the second control signal SR _ PWMB.
Referring to fig. 9, fig. 9 is a timing diagram illustrating operation of a synchronous rectification system according to an embodiment of the present application. In fig. 9, S1 and S2 are levels of control signals of the first switch tube S1 and the second switch tube S2, respectively, iLr is a current flowing through the first inductor Lr in the power supply circuit, im is a current flowing through the second inductor Lm, iP is a current flowing through the primary coil of the transformer, iSR is a current flowing through the synchronous rectifier bridge 400, SR _ PWMA is the first control signal, SR _ PWMB is the second control signal, id is a current flowing through the second capacitor Co, and Vsns is a voltage measured at the cathode of the second diode D2 in the rectifier unit.
In the period from t0 to t1, the first switching tube S1 is turned off and the second switching tube S2 is turned off, the current iSR of the secondary coil of the transformer 600 continues to flow in the forward direction, and the secondary coil of the transformer 600, the third switching tube S3, the second capacitor Co and the fifth switching tube S5 form a closed loop. The current iSR of the secondary coil of the transformer 600 flows through the primary coil of the current transformer CT, so that the secondary coil of the current transformer CT generates an induced voltage, and at this time, the secondary coil of the current transformer CT, the second diode D2, the first resistor R1, and the fourth diode D4 form a closed loop. The induced voltage of the secondary coil of the current transformer CT forms a first current iCT1= iSR/n in the closed loop, which is a first current signal induced and generated by the rectifying unit 201. The current iSR gradually increases from zero, and the ic t1 also increases proportionally. At this time, the control signals SR _ PWMA and SR _ PWMB output from the logic drive circuit 200 are both low. The third switching tube S3, the fourth switching tube S4, the fifth switching tube S5 and the sixth switching tube S6 are in an off state.
In a period t1-t2, the first switch tube S1 is turned on and the second switch tube S2 is turned off, the direction of the secondary coil current iSR of the transformer 600 remains unchanged, when iSR > = Ith + _ SR, the corresponding iCT1 > = Ith + _ SR/n (first current threshold), so that the potential at CTA of the rectifying unit 201 becomes-0.7V with respect to ground, the first logic signal S _ SRDRVA output by the first logic unit 202 is at a high level, after passing through the driving unit 204, the level of the first control signal SR _ PWMA changes from low to high, and the third switch tube S3 and the fifth switch tube S5 are in a conducting state. During this period, the first diode D1 and the third diode D3 are turned off by the reverse voltage, so that the potential at the CTB of the rectifying unit 201 is at a high level with respect to the ground, the second logic signal S _ SRDRVB output by the second logic unit 203 is at a low level, after passing through the driving unit 204, the level of the second control signal SR _ PWMB is at a low level, and the fourth switching tube S4 and the sixth switching tube S6 are in an off state. When the iSR gradually increases from Ith + _ SR to Ith + _ SR, the first control signal SR _ PWMA is maintained at a high level, the second control signal SR _ PWMB is maintained at a low level, the third switch tube S3 and the fifth switch tube S5 are maintained to be on, and the fourth switch tube S4 and the sixth switch tube S6 are maintained to be off.
In a period from t2 to t3, the first switch tube S1 is turned on and the second switch tube S2 is turned off, the direction of the current iSR of the secondary coil of the transformer 600 is maintained, the iSR is reduced to 0 from Ith + _ SR, the corresponding iCT1 is also reduced to 0, the first logic signal S _ SRDRVA is changed from high level to low level, after passing through the driving unit 204, the level of the first control signal SR _ PWMA is low level, the third switch tube S3 and the fifth switch tube S5 are changed to an off state, and the current iSR freewheels through the body diodes of the third switch tube S3 and the fifth switch tube S5.
In a period from t3 to t4, the first switching tube S1 is turned off and the second switching tube S2 is turned off, the current iSR of the secondary coil of the transformer 600 reversely flows, and the secondary coil of the transformer 600, the fourth switching tube S4, the second capacitor Co and the sixth switching tube S6 form a closed loop. The current iSR of the secondary coil of the transformer 600 flows through the primary coil of the current transformer CT, so that the secondary coil of the current transformer CT generates an induced voltage, and at this time, the secondary coil of the current transformer CT, the first diode D1, the first resistor R1, and the third diode D3 form a closed loop. The induced voltage of the secondary coil of the current transformer CT forms a second current iCT2= iSR/n in the closed loop, which is a second current signal induced and generated by the rectifying unit 201. The current iSR gradually increases from zero to zero, and the ic t2 also increases proportionally. At this time, the control signals SR _ PWMA and SR _ PWMB output from the logic drive circuit 200 are both low. The third switch tube S3, the fourth switch tube S4, the fifth switch tube S5 and the sixth switch tube S6 are in an off state.
In a period t4-t5, the second switch tube S2 is turned on and the first switch tube S1 is turned off, the direction of the secondary winding current iSR of the transformer 600 remains unchanged, when iSR > = Ith- _ SR, the corresponding iCT1 > = Ith- _ SR/n (second current threshold), so that the potential at the CTB of the rectifying unit 201 becomes-0.7V with respect to ground, the second logic signal S _ SRDRVB output by the second logic unit 203 is at a high level, after passing through the driving unit 204, the level of the second control signal SR _ PWMB is changed from low to high, and the fourth switch tube S4 and the sixth switch tube S6 are in a conducting state. During this period, the second diode D2 and the fourth diode D4 are turned off by receiving the reverse voltage, so that the potential at the CTA of the rectifying unit 201 is at a high level with respect to the ground, the first logic signal S _ SRDRVA output by the first logic unit 202 is at a low level, after passing through the driving unit 204, the level of the first control signal SR _ PWMA is at a low level, and the third switch tube S3 and the fifth switch tube S5 are in an off state. When the iSR gradually increases from Ith _ SR to Ith _ SR, the first control signal SR _ PWMA is maintained at a low level, the second control signal SR _ PWMB is maintained at a high level, the fourth switching tube S4 and the sixth switching tube S6 are maintained on, and the third switching tube S3 and the fifth switching tube S5 are maintained off.
In the period from t5 to t6, the second switch tube S2 is turned on and the first switch tube S1 is turned off, the direction of the current iSR of the secondary winding of the transformer 600 is kept unchanged, the iSR is reduced to 0 from Ith- _ SR, the corresponding iCT2 is also reduced to 0, the second logic signal S _ SRDRVB is changed from high level to low level, after passing through the driving unit 204, the level of the second control signal SR _ PWMA is low level, the fourth switch tube S4 and the sixth switch tube S6 are changed to an off state, and the current iSR freewheels through the body diodes of the fourth switch tube S4 and the sixth switch tube S6.
When the synchronous rectification system works, each stage is repeatedly and circularly executed, and accurate synchronous rectification can be realized.
The synchronous rectification system also has a function of preventing current backflow. Specifically, referring to fig. 2, 5, 6 and 8, when the secondary winding of the transformer 600, the third switch S3, the second capacitor Co and the fifth switch S5 form a closed loop, if a higher instantaneous electromotive force is reversely injected into the output terminal (Co) during the large dynamic unloading, the current will flow in a reverse direction, i.e. from point a to point B on the current transformer CT, and the current iCT generated by the secondary winding of the corresponding current transformer causes the potential at CTB in the rectifying unit 201 in fig. 2 to become-0.7V with respect to ground, so that the fifth transistor Q5 in fig. 6 is turned on from the base to the collector, so that the base level of the sixth transistor Q6 is about 0V, and the base and the emitter of the sixth transistor Q6 are turned off, so that the collector of the sixth transistor Q6 is at a high level, i.e. the second logic signal S _ drvb output by the second logic unit is at a high level, so that the third transistor Q3 in fig. 5 is turned on, so that the first logic signal S _ drva output becomes a low level, thereby preventing the reverse current flowing through the third switch S3 and the reverse current flowing through the fifth switch S5.
The application also discloses a rectifying device which comprises the synchronous rectification control circuit. The rectifying device provided by the embodiment realizes accurate synchronous rectification by utilizing a hardware circuit, and does not need to carry out complex programming design, thereby reducing the design difficulty in the early stage.
Referring to fig. 10, fig. 10 is a flowchart illustrating a synchronous rectification control method according to an embodiment of the present application.
In step 802, a current collecting circuit collects a working current of a transformer coil and outputs an ac signal according to the working current.
In step 804, the alternating current signal is received by a rectifying unit to output a first voltage signal and a second voltage signal.
In step 806, the first voltage signal and the second voltage signal are received by a logic unit to output a first logic signal and a second logic signal.
In step 808, outputting, by a driving unit, a first control signal and a second control signal based on the first logic signal and the second logic signal, where the first control signal and the second control signal are used to control a synchronous rectifier bridge to rectify a current output by a secondary coil of a transformer.
In step 810, the first logic signal and the second logic signal are locked in a half-cycle of the synchronous rectifier bridge operation through a self-locking circuit.
In an embodiment of the application, the synchronous rectification control method further includes outputting, by a first interlock circuit, a first interlock signal according to the first logic signal to lock the second logic signal in a half-cycle of the synchronous rectification bridge; and outputting a second interlocking signal according to the second logic signal through a second interlocking circuit so as to lock the first logic signal in the half-cycle of the operation of the synchronous rectifier bridge.
In an embodiment of the application, the synchronous rectification control method further includes receiving, by a rectification unit, the alternating current signal to output a first current signal and a second current signal, and detecting the first current signal and the second current signal.
Although embodiments of the present application and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present application, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present application. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (17)
1. A synchronous rectification control circuit, comprising:
the current acquisition circuit is used for acquiring the working current of the transformer coil and outputting an alternating current signal according to the working current;
the logic driving circuit is electrically connected with the current acquisition circuit and used for generating a first logic signal and a second logic signal according to the received alternating current signal and respectively outputting a first control signal and a second control signal based on the first logic signal and the second logic signal, wherein the first control signal and the second control signal are used for controlling a synchronous rectifier bridge, and the synchronous rectifier bridge is connected with a transformer secondary coil of a transformer so as to rectify the current output by the transformer secondary coil; and
and the self-locking circuit is electrically connected with the logic driving circuit and is used for locking the first logic signal and the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge.
2. The synchronous rectification control circuit of claim 1, further comprising:
an interlock circuit electrically connected to the logic driving circuit;
the interlock circuit includes:
the first interlocking circuit is used for outputting a first interlocking signal according to the first logic signal so as to lock the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge; and
and the second interlocking circuit is used for outputting a second interlocking signal according to the second logic signal so as to lock the first logic signal in the half cycle of the operation of the synchronous rectifier bridge.
3. The synchronous rectification control circuit of claim 1,
the current acquisition circuit comprises a current transformer, a primary coil of the current transformer is connected with a transformer coil in series, a secondary coil of the current transformer is electrically connected with the logic drive circuit, and the transformer coil is a transformer primary coil or a transformer secondary coil.
4. The synchronous rectification control circuit of claim 1,
the logic driving circuit includes:
the rectifying unit is electrically connected with the current acquisition circuit and used for outputting a first voltage signal and a second voltage signal according to the alternating current signal;
the first logic unit is electrically connected with the rectifying unit and used for outputting a first logic signal according to the first voltage signal;
the second logic unit is electrically connected with the rectifying unit and used for outputting a second logic signal according to the second voltage signal;
and the driving unit is respectively electrically connected with the first logic unit and the second logic unit and is used for outputting a first control signal according to the first logic signal and outputting a second control signal according to the second logic signal.
5. The synchronous rectification control circuit of claim 4,
the rectifying unit comprises a first diode, a second diode, a third diode and a fourth diode;
the first diode and the fourth diode are connected in series, the second diode and the third diode are connected in series, a common node of the first diode and the fourth diode is electrically connected with a first end of the current acquisition circuit and the first logic unit, a common node of the second diode and the third diode is electrically connected with a second end of the current acquisition circuit and the second logic unit, an anode of the fourth diode and an anode of the third diode are respectively connected with the ground, and a cathode of the first diode and a cathode of the second diode are electrically connected and are connected with the ground through a first resistor.
6. The synchronous rectification control circuit of claim 5,
the first logic unit comprises a first triode, a second resistor and a third resistor;
the collector of the first triode is electrically connected with the rectifying unit, the base of the first triode is electrically connected with the base of the second triode, the emitter of the first triode is electrically connected with the self-locking circuit, the base and the collector of the second triode are respectively connected with the power supply through the second resistor and the third resistor, the base of the second triode is electrically connected with the emitter of the first triode, the emitter of the second triode is electrically connected with the ground,
and the collector of the second triode is used for outputting a first logic signal.
7. The synchronous rectification control circuit of claim 5,
the second logic unit comprises a fifth triode, a sixth triode, a seventh resistor and an eighth resistor;
the collector electrode of the fifth triode is electrically connected with the rectifying unit, the base electrode of the fifth triode is electrically connected with the base electrode of the sixth triode, the emitter electrode of the fifth triode is electrically connected with the self-locking circuit, the base electrode and the collector electrode of the sixth triode are respectively connected with the power supply through the seventh resistor and the eighth resistor, the base electrode of the sixth triode is electrically connected with the emitter electrode of the fifth triode, the emitter electrode of the sixth triode is electrically connected with the ground,
and the collector of the sixth triode is used for outputting a second logic signal.
8. The synchronous rectification control circuit of claim 4,
the self-locking circuit comprises a first self-locking circuit and a second self-locking circuit, the first self-locking circuit comprises a fourth resistor and a fourth MOS (metal oxide semiconductor) tube, the second self-locking circuit comprises a ninth resistor and an eighth MOS tube, the fourth resistor and the fourth MOS tube are connected in series between the first logic unit and the ground, the ninth resistor and the eighth MOS tube are connected in series between the second logic unit and the ground, the grid electrode of the fourth MOS tube is connected to the output end of the first logic unit for outputting the first logic signal, and the grid electrode of the eighth MOS tube is connected to the output end of the second logic unit for outputting the second logic signal.
9. The synchronous rectification control circuit of claim 2,
the first interlocking circuit comprises a third MOS tube, a fifth resistor and a sixth resistor;
the drain electrode of the third MOS tube is electrically connected with the logic driving circuit and used for outputting a first interlocking signal, the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is grounded through a sixth resistor and receives a second interlocking signal through a fifth resistor.
10. The synchronous rectification control circuit of claim 2,
the second interlocking circuit comprises a seventh MOS transistor, a tenth resistor and an eleventh resistor;
the drain electrode of the seventh MOS tube is electrically connected with the logic driving circuit and used for outputting a second interlocking signal, the source electrode of the seventh MOS tube is grounded, and the grid electrode of the seventh MOS tube is grounded through a tenth resistor and receives the first interlocking signal through an eleventh resistor.
11. The synchronous rectification control circuit of claim 9,
and the drain electrode of the third MOS tube outputs a first interlocking signal through a sixth diode.
12. The synchronous rectification control circuit of claim 10,
and the drain electrode of the seventh MOS tube outputs a second interlocking signal through an eighth diode.
13. The synchronous rectification control circuit of claim 4,
the drive unit comprises a logic circuit which is provided with a logic circuit,
the logic circuit is electrically connected with the first logic unit and the second logic unit respectively, and is used for outputting the first control signal after performing logic operation on the first logic signal and outputting the second control signal after performing logic operation on the second logic signal.
14. The synchronous rectification control circuit of claim 5,
the first resistor is a current sampling resistor, and the current sampling resistor is used for collecting current signals of the rectifying unit.
15. A synchronous rectification control method, characterized in that the method comprises:
collecting the working current of a transformer coil through a current collecting circuit, and outputting an alternating current signal according to the working current;
receiving the alternating current signal through a rectifying unit to output a first voltage signal and a second voltage signal;
receiving, by a logic unit, the first voltage signal and the second voltage signal to output a first logic signal and a second logic signal;
outputting a first control signal and a second control signal based on the first logic signal and the second logic signal through a driving unit, wherein the first control signal and the second control signal are used for controlling a synchronous rectifier bridge to rectify current output by a secondary coil of a transformer;
and locking the first logic signal and the second logic signal in a half-cycle of the operation of the synchronous rectifier bridge through a self-locking circuit.
16. The synchronous rectification control method of claim 15,
the method further includes outputting, by a first interlock circuit, a first interlock signal based on the first logic signal to latch the second logic signal during a half-cycle of operation of the synchronous rectifier bridge; and outputting a second interlocking signal according to the second logic signal through a second interlocking circuit so as to lock the first logic signal in a half-cycle of the operation of the synchronous rectifier bridge.
17. The synchronous rectification control method of claim 16,
the method also includes receiving, by the rectifying unit, the alternating current signal to output a first current signal and a second current signal, and detecting the first current signal and the second current signal.
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