CN114977107A - Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC - Google Patents

Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC Download PDF

Info

Publication number
CN114977107A
CN114977107A CN202210554563.XA CN202210554563A CN114977107A CN 114977107 A CN114977107 A CN 114977107A CN 202210554563 A CN202210554563 A CN 202210554563A CN 114977107 A CN114977107 A CN 114977107A
Authority
CN
China
Prior art keywords
resistor
resistance
side driving
circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210554563.XA
Other languages
Chinese (zh)
Inventor
王邦兴
汪超
葛科勇
刘丽娟
史传洲
张丽
桂仁
张建琴
王辉
王中禹
宋志鹏
赵强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Institute of Space Power Sources
Original Assignee
Shanghai Institute of Space Power Sources
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Institute of Space Power Sources filed Critical Shanghai Institute of Space Power Sources
Priority to CN202210554563.XA priority Critical patent/CN114977107A/en
Publication of CN114977107A publication Critical patent/CN114977107A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/305—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M3/315—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A current backflow prevention time sequence synchronous control circuit for isolated DC-DC comprises a drive signal detection circuit K 1 Self-locking circuit K 2 And a drive control circuit K 3 . Drive signal detection circuit K 1 For transistor Q in each cycle 1 The level state of the collector is monitored, the state of a primary side driving signal output by a primary side PWM control chip is detected, and the purpose of measuring the C value is achieved 1 And controlling the level. Self-locking circuit K 2 To C 1 The level state is monitored, and C is realized by switching on and off the self-locking circuit 2 Flat shapeAnd controlling the state. Drive control circuit K 3 To C 2 The level state is monitored, and the control of the secondary side driving signal is realized by switching on and off the secondary side driving chip, so that the purpose of simultaneously outputting and controlling the primary side driving signal and the secondary side driving signal is achieved.

Description

Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC
Technical Field
The invention relates to a current backflow preventing time sequence synchronous control circuit for isolated DC-DC, and belongs to the field of electricity.
Background
The DC-DC converter based on the synchronous rectification control mode greatly improves the energy conversion efficiency, but also brings the phenomenon of current backflow, the phenomenon is particularly prominent in the application scene of large capacitive load, and the efficiency, the service life, the safety and the reliability of the secondary power supply system of the spacecraft are seriously influenced by the phenomenon. Due to the limitation of the selection range of components in the aerospace secondary power supply field and the higher requirement of the extreme complex application environment in the outer space on the reliability of the components, the current backflow prevention PWM control chip commonly used in the market cannot be applied to the aerospace secondary power supply field.
Disclosure of Invention
The technical problem solved by the invention is as follows: aiming at the problem that a common current backflow prevention PWM control chip cannot be applied to the field of aerospace secondary power sources in the prior art, a current backflow prevention time sequence synchronous control circuit for isolated DC-DC is provided.
The technical scheme for solving the technical problems is as follows:
a current backflow prevention time sequence synchronous control circuit for isolated DC-DC comprises a drive signal detection circuit K 1 Self-locking circuit K 2 And a drive control circuit K 3 Wherein:
drive control circuit K 3 Comprises a primary PWM control chip, a secondary drive chip, and a drive signal detection circuit K 1 In each period, according to the state of the primary side driving signal output by the primary side PWM control chip, the driving signal detection circuit K is detected 1 The level signal state of the output end of the circuit is controlled, and the circuit is self-locked 2 Detecting circuit K according to driving signal 1 Output level state of, via a self-locking circuit K 2 Self-switch control realizes pair self-locking circuit K 2 Control of the level state of the output, drive control circuit K 3 According to a self-locking circuit K 2 And the output control of the secondary driving signal is realized through the on-off control of the secondary driving chip in the level state of the output end, and the simultaneous output control of the primary driving signal and the secondary driving signal is completed.
Drive signal detection circuit K 1 Comprises a triode Q 1 Resistance R 1 Resistance R 2 And a resistor R 3 Resistance R 4 Resistance R 1 Resistance R 2 Parallel connection, after parallel connection, one end is connected with PWM of primary side PWM control chip 1 、PWM 2 One end of the transistor is connected with a triode Q 1 Base electrode of (3), resistor R 4 One end of the control circuit is connected with a CLOCK pin of the primary side PWM control chip, and the other end is connected with a triode Q 1 Collector electrode of (2), resistor R 3 One end is connected with a triode Q 1 The other end of the emitter of the triode (Q) 1 The base of (2).
Self-locking circuit K 2 Comprising a resistor R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 And a resistor R 11 Triode Q 2 IIIPolar tube Q 3 Diode D 1 Resistance R 5 Resistance R 6 And a triode Q 2 The emitter and the collector are connected in series, one end of the series-connected emitter-collector is connected with a +5V power supply, the other end of the series-connected emitter-collector is grounded, and a resistor R is connected with a resistor R 7 Resistance R 8 And a triode Q 3 The emitter and the collector of the resistor are connected in series, after the series connection, one end of the +5V power supply is connected in series, the other end of the +5V power supply is grounded, and the resistor R is connected in series 9 Resistance R 10 And a resistor R 11 A triode Q connected in series with one end connected with a +5V power supply and the other end grounded 2 Base electrode of the resistor is connected with a resistor R 7 Resistance R 8 Connection point, triode Q 3 Base electrode of the resistor is connected with a resistor R 5 And a resistor R 6 Connection point, diode D 1 Anode connected to resistor R 9 Resistance R 10 A connection point, a cathode connected to the transistor Q 2 Base electrode of the triode Q 1 The collector of the transistor is connected with a triode Q 3 The base of (1).
Drive signal detection circuit K 1 In, R 4 And Q 1 Collector connecting point C 1 As an output, when the primary side drive signal disappears, C 1 The level state is high level, when the primary side driving signal is normal, C 1 The level state is low.
Self-locking circuit K 2 In, C 1 Is linked to R 5 、R 6 And Q 3 As the input terminal of the self-locking circuit, the resistor R 10 Resistance R 11 Connecting point C of 2 As an output terminal, when C 1 In the high level state, the primary side drive signal disappears, C 2 The electric level is clamped to a low-level state until a primary side driving signal is generated; when C is present 1 In the low level state, the primary side drive signal is normal, C 2 The level is clamped to a high state.
Drive control circuit K 3 In (C) 2 A control pin connected to the secondary side drive chip according to C 2 When C is the level state of the secondary side drive signal 2 When the level state of the secondary side driving chip is high level, the primary side driving signal is normal, the secondary side driving chip normally sends out a secondary side driving signal, and when the level state of the secondary side driving chip is high level, the secondary side driving chip normally sends out a secondary side driving signal 2 Electricity (D) fromWhen the flat state is a low level, the primary side driving signal disappears, and the secondary side driving chip stops sending the secondary side driving signal, so that the primary side driving signal and the secondary side driving signal are simultaneously output and controlled.
The primary side PWM control chip adopts a UC1825ALQMLV chip, the secondary side drive chip adopts a UC1715W-SP chip, and a control pin is an ENBL pin of the UC1715W-SP chip.
Compared with the prior art, the invention has the advantages that:
(1) the invention provides a current-back-flow-preventing time sequence synchronous control circuit for an isolated DC-DC (direct current-direct current). by utilizing the working characteristic that when a PWM (pulse-width modulation) control chip works normally, the phase of a CLOCK signal in each period is ahead of a primary side PWM (pulse-width modulation) signal, the CLOCK signal is generated before the primary side PWM signal in the starting process, and the CLOCK signal is later than the disappearance of the primary side PWM signal in the shutdown process, whether a primary side driving signal is output or not is detected cycle by cycle, and then the switch of a secondary side driving signal is controlled, the logic control function of driving the primary side and the secondary side to be simultaneously switched is realized, so that the back flow of capacitor array energy to a secondary side MOS (metal oxide semiconductor) tube in the starting and shutting process is inhibited;
(2) the circuit level simulation and verification are carried out through Saber, and the fact that the timing sequence synchronous control circuit does not influence the normal work of the main power circuit is shown. The time sequence synchronous control circuit carries out cycle-by-cycle detection on a primary side PWM control signal of the DC-DC converter, once the PWM control signal disappears, the secondary side MOS tube is immediately turned off, and the effect that the primary side and the secondary side drive the same switch is achieved;
(3) the invention takes a half-bridge-full-wave rectification converter based on discrete components as an example to carry out the real object verification of a time sequence synchronous control circuit. And under the condition that a load end is provided with a large capacitor array, the on-off test is carried out on the output voltage and the output current of the main power circuit. And starting the device under the condition that the capacitor array has residual voltage, and keeping the output voltage to be monotonically increased. When the power supply is shut down under light load under the condition that the output end is provided with the capacitor array, the output current slowly drops to zero, and the phenomenon of reverse flow of the current does not occur. The reverse flow of the current at the load end to the secondary side MOS tube can be effectively inhibited by the time sequence synchronous control circuit in the synchronous rectification mode.
Drawings
FIG. 1 is a schematic diagram of a current backflow prevention timing synchronization control circuit provided in the present invention;
FIG. 2 shows PWM provided by the present invention 1 Signal, PWM 2 A signal, a CLOCK signal and a control signal C starting process sequence diagram;
FIG. 3 shows PWM provided by the present invention 1 Signal, PWM 2 A signal, a CLOCK signal and a control signal C are used for controlling a timing chart of a shutdown process;
FIG. 4 shows PWM provided by the present invention 1 Signal, PWM 2 A signal, a CLOCK signal and a control signal C are shown in a simulation waveform diagram in a starting process;
FIG. 5 shows PWM provided by the present invention 1 Signal, PWM 2 The signal, the CLOCK signal and the control signal C are schematic diagrams of simulation waveforms in the shutdown process;
FIG. 6 shows PWM provided by the present invention 1 Signal, PWM 2 The signal, the CLOCK signal and the control signal C are schematic diagrams of actually measured waveforms in the starting process;
FIG. 7 shows PWM provided by the present invention 1 Signal, PWM 2 The signal, the CLOCK signal and the control signal C are schematic diagrams of actually measured waveforms in the shutdown process;
FIG. 8 shows PWM during the power-on process of the load-side capacitor array with residual voltage 3 Signal, PWM 4 Signal, output voltage V o Actually measuring a oscillogram;
FIG. 9 shows the PWM during shutdown with a capacitor array at the output 4 Signal MOS transistor V ds Output current I o Actually measuring a oscillogram;
Detailed Description
A current backflow prevention time sequence synchronous control circuit for an isolated DC-DC can solve the current backflow problem under the control of a synchronous rectification mode, utilizes the working characteristic that when a PWM control chip works normally, the phase of a CLOCK signal in each period of the PWM control chip is ahead of a primary PWM signal, the CLOCK signal is generated before the primary PWM signal in the starting process, and the CLOCK signal is behind the disappearance of the primary PWM signal in the shutdown process, detects whether a primary side driving signal exists or not cycle by cycle to realize the control of a secondary side driving signal, achieves the effect that the primary side driving and the secondary side driving are on and off simultaneously, thereby inhibiting the current at a load end from flowing backwards to a secondary side MOS tube, and improving the stability and the reliability of a secondary power supply for aerospace, and has the specific structure as follows:
comprises a drive signal detection circuit K 1 Self-locking circuit K 2 And a drive control circuit K 3 Wherein:
drive control circuit K 3 Comprises a primary PWM control chip, a secondary drive chip, and a drive signal detection circuit K 1 In each period, according to the state of the primary side driving signal output by the primary side PWM control chip, detecting a driving signal by a circuit K 1 The output end of the circuit is controlled by the state of a level signal, and a self-locking circuit K 2 Detecting circuit K according to driving signal 1 Output level state of, via a self-locking circuit K 2 Self-switch control realizes pair self-locking circuit K 2 Control of the level state of the output, drive control circuit K 3 According to a self-locking circuit K 2 And the output control of the secondary side driving signal is realized through the on-off control of the secondary side driving chip according to the level state of the output end, and the simultaneous output control of the primary side driving signal and the secondary side driving signal is completed.
Wherein, the drive signal detection circuit K 1 Comprises a triode Q 1 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 1 Resistance R 2 Parallel connection, after parallel connection, one end is connected with PWM of primary side PWM control chip 1 、PWM 2 One end of the transistor is connected with a triode Q 1 Base electrode of (3), resistor R 4 One end of the control circuit is connected with a CLOCK pin of the primary side PWM control chip, and the other end is connected with a triode Q 1 Collector electrode of (2), resistor R 3 One end is connected with a triode Q 1 The other end of the emitter of the triode (Q) 1 A base electrode of (1);
self-locking circuit K 2 Comprising a resistor R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 And a resistor R 10 Resistance R 11 Triode Q 2 Triode Q 3 Diode D 1 Resistance R 5 Resistance R 6 And a triode Q 2 Is transmitted byThe electrode-collector electrodes are connected in series, one end of the series-connected electrode-collector electrodes is connected with a +5V power supply, the other end of the series-connected electrode-collector electrodes is grounded, and a resistor R is connected with the other end of the series-connected electrode-collector electrodes 7 Resistance R 8 And a triode Q 3 The emitter and the collector of the resistor are connected in series, after the series connection, one end of the +5V power supply is connected in series, the other end of the +5V power supply is grounded, and the resistor R is connected in series 9 Resistance R 10 Resistance R 11 A triode Q connected in series with one end connected with a +5V power supply and the other end grounded 2 Base electrode of the resistor is connected with a resistor R 7 Resistance R 8 Connection point, triode Q 3 Base electrode of the resistor is connected with a resistor R 5 Resistance R 6 Connection point, diode D 1 Anode is connected to resistor R 9 And a resistor R 10 A connection point with a cathode connected to a transistor Q 2 Base electrode of the triode Q 1 The collector of the transistor is connected with a triode Q 3 A base electrode of (1);
drive signal detection circuit K 1 In, R 4 And Q 1 Collector connecting point C of 1 As an output, when the primary side drive signal disappears, C 1 The level state is high level, when the primary side driving signal is normal, C 1 The level state is low level;
self-locking circuit K 2 In, C 1 Is connected to R 5 、R 6 And Q 3 As the input terminal of the self-locking circuit, the resistor R 10 Resistance R 11 Connection point C of 2 As an output terminal, when C 1 In the high state, the primary driving signal disappears, C 2 The electric level is clamped to a low-level state until a primary side driving signal is generated; when C is present 1 In the low level state, the primary side drive signal is normal, C 2 The level is clamped to a high state;
drive control circuit K 3 In, C 2 A control pin connected to the secondary side drive chip according to C 2 When C is the level state of the secondary side drive signal 2 When the level state of the secondary side driving chip is high, the primary side driving signal is normal, the secondary side driving chip normally sends out a secondary side driving signal, and when the level state of the secondary side driving chip is high, the secondary side driving signal is sent out 2 When the level state is low, the primary side driving signal disappears, and the secondary side driving chip stops sending the secondary side driving signal, so that primary side driving is realizedAnd simultaneously outputting and controlling the dynamic signal and the secondary side driving signal.
A primary side PWM control chip adopts a UC1825ALQMLV chip, a secondary side driving chip adopts a UC1715W-SP chip, and a control pin is an ENBL pin of the UC1715W-SP chip;
self-locking circuit K 2 The power supply voltage is 5V when the drive control circuit K 3 After actuation, the circuit K is self-locked 2 C is to be 2 The voltage clamp is at low level until the primary side drive signal is normally output, and when the drive control circuit K 3 After stopping, the circuit K is locked 2 C is to be 2 The voltage clamp is at a low level.
Specifically, due to the limitation of the selection range of components in the field of aerospace secondary power supplies and the high requirement of the application environment with the extremely complex end in space on the reliability of the components, the current backflow prevention PWM control chip commonly used in the market cannot be applied to the field of aerospace secondary power supplies.
The following is further illustrated according to specific examples:
in the present embodiment, the circuit is as shown in FIG. 1, the first part is represented by R 1 、R 2 、R 3 、R 4 And Q 1 Composition, e.g. K in FIG. 1 1 Shown; the second part is composed of R 5 、R 6 、R 7 、R 8 、R 9 、R 10 、R 11 、Q 2 、Q 3 And D 1 Composition, e.g. K in FIG. 1 2 Shown; the third part consists of a primary PWM control chip and a secondary drive chip, such as K in figure 1 3 Shown;
when the PWM control chip works normally, the phase of a CLOCK signal in each period of the PWM control chip is ahead of that of a primary side PWM signal, the CLOCK signal is generated before the primary side PWM signal in the starting process, and the CLOCK signal disappears after the primary side PWM signal in the shutdown process. Therefore, when the PWM control chip works normally, the triode Q 1 All the time, C 1 The point voltage clamp is at zero, then K 2 The self-locking circuit in (1) can not be switched on to work, C 2 The dot voltage is always high. During the starting process, since the CLOCK signal is generated before the primary PWM signal, the CLOCK signal will be K before the PWM signal is generated 2 The self-locking circuit in (1) is opened, at this time C 2 The point voltage is clamped to a low level until the primary side PWM signal is generated, and the timing relationship is shown in fig. 2. In the shutdown process, since the CLOCK signal disappears later than the primary PWM signal, once the primary PWM signal stops sending waves, the CLOCK signal sends K 2 The self-locking circuit in (1) is opened, at this time C 2 The dot voltage is clamped low and the timing relationship is shown in fig. 3.
From the above analysis, in the whole period of the PWM control chip, when the primary side PWM signal is normally emitted, K is obtained 2 C in 2 The point voltage is in a high level state, if the primary side PWM signal can not be generated, K 2 C in 2 The dot voltage is in a low state. Thus, K 3 The secondary side driving chip in (1) can be based on C 2 The primary side PWM signal is judged whether to emit wave normally or not by the level state of the primary side PWM signal, so that the on-off of the secondary side MOS tube is controlled, and the effect of driving the primary side and the secondary side to be on and off simultaneously is achieved.
Circuit level simulation and verification of the circuit are performed using saber software. The main power topology adopts a half-bridge-full-wave rectifying circuit, the primary side control chip adopts a UC1825 chip, the secondary side control chip adopts a UC1715 chip, and the power supply voltage of the self-locking circuit is 5V. As shown in fig. 4, during the startup process, the CLOCK signal is generated before the primary PWM signal, and due to the effect of the self-locking circuit, C is generated 2 The voltage clamp is positioned at a low level until the primary side PWM signal normally sends waves. As shown in fig. 5, during shutdown, the CLOCK signal disappears later than the primary PWM signal, and due to the self-locking circuit, C is lost 2 Voltage clampAt a low level;
the physical verification is carried out on the synchronous sequential control circuit, wherein a half-bridge-full-wave rectifying circuit is adopted in a main power topology, a UC1825 chip is adopted in a primary side control chip, a UC1715 chip is adopted in a secondary side control chip, and the power supply voltage of the self-locking circuit is 5V. PWM as shown in FIG. 6 and FIG. 7 1 Corresponding to MOS transistor M in FIG. 1 1 CLOCK corresponds to the CLOCK signal in fig. 1, and C corresponds to C in fig. 1 2 Dot voltage, PWM 4 Corresponding to MOS transistor M in FIG. 1 4 In the starting process, a CLOCK signal is generated before a primary PWM signal, and C is generated under the action of a self-locking circuit 2 The voltage clamp is positioned at a low level until the primary side PWM signal normally sends waves. In the shutdown process, the CLOCK signal disappears later than the primary side PWM signal, and the C2 voltage clamp is at a low level due to the effect of the self-locking circuit.
In addition, under the condition that a load end is provided with a large capacitor array, the on-off test is carried out on the output voltage and the output current of the main power circuit. When the capacitor array is started up with residual voltage, the output voltage waveform is as shown in fig. 8, and it can be seen from the figure that the output voltage keeps monotone rising. When the power is turned off under light load with the capacitor array at the output end, the waveform of the output current is as shown in fig. 9, and it can be seen from the figure that the output current slowly drops to zero, and the phenomenon of reverse flow of the current does not occur.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Those skilled in the art will appreciate that the details of the invention not described in detail in this specification are well within the skill of those in the art.

Claims (7)

1. A current backflow prevention time sequence synchronous control circuit for isolated DC-DC is characterized in that:
comprises a drive signal detection circuit K 1 Self-locking circuit K 2 And a drive control circuit K 3 Wherein:
drive control circuit K 3 Comprises a primary PWM control chip, a secondary drive chip, and a drive signal detection circuit K 1 In each period, according to the state of the primary side driving signal output by the primary side PWM control chip, the driving signal detection circuit K is detected 1 The output end of the circuit is controlled by the state of a level signal, and a self-locking circuit K 2 Detecting circuit K according to driving signal 1 Output terminal level state of, through a self-locking circuit K 2 Self-switch control realizes pair self-locking circuit K 2 Control of the level state of the output, drive control circuit K 3 According to a self-locking circuit K 2 And the output control of the secondary side driving signal is realized through the on-off control of the secondary side driving chip according to the level state of the output end, and the simultaneous output control of the primary side driving signal and the secondary side driving signal is completed.
2. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
drive signal detection circuit K 1 Comprising a triode Q 1 Resistance R 1 And a resistor R 2 Resistance R 3 And a resistor R 4 Resistance R 1 Resistance R 2 Parallel connection, after parallel connection, one end is connected with PWM of primary side PWM control chip 1 、PWM 2 One end of the transistor is connected with a triode Q 1 Base electrode of (3), resistor R 4 One end of the control circuit is connected with a CLOCK pin of the primary side PWM control chip, and the other end is connected with a triode Q 1 Collector electrode of (1), resistor R 3 One end is connected with a triode Q 1 The other end of the emitter of the triode (Q) 1 The base of (1).
3. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
self-locking circuit K 2 Comprising a resistor R 5 Electricity, electricityResistance R 6 Resistance R 7 Resistance R 8 And a resistor R 9 Resistance R 10 Resistance R 11 Triode Q 2 Triode Q 3 Diode D 1 Resistance R 5 Resistance R 6 And a triode Q 2 The emitter and the collector are connected in series, one end of the series-connected emitter-collector is connected with a +5V power supply, the other end of the series-connected emitter-collector is grounded, and a resistor R is connected with a resistor R 7 Resistance R 8 And a triode Q 3 The emitter and the collector are connected in series, after the series connection, one end of the series connection is a +5V power supply, the other end of the series connection is grounded, and a resistor R is connected in series 9 Resistance R 10 And a resistor R 11 A triode Q connected in series with one end connected with a +5V power supply and the other end grounded 2 Base electrode of the resistor is connected with a resistor R 7 Resistance R 8 Connection point, triode Q 3 Base electrode of the resistor is connected with a resistor R 5 Resistance R 6 Connection point, diode D 1 Anode is connected to resistor R 9 Resistance R 10 A connection point, a cathode connected to the transistor Q 2 Base electrode of the triode Q 1 The collector of the transistor is connected with a triode Q 3 The base of (1).
4. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
drive signal detection circuit K 1 In, R 4 And Q 1 Collector connecting point C of 1 As an output, when the primary side drive signal disappears, C 1 The level state is high level, when the primary side driving signal is normal, C 1 The level state is low.
5. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
self-locking circuit K 2 In, C 1 Is linked to R 5 、R 6 And Q 3 As the input terminal of the self-locking circuit, the resistor R 10 Resistance R 11 Connection point C of 2 As an output terminal, when C 1 In the high level state, the primary side drive signal disappears, C 2 The electric level is clamped to a low-level state until a primary side driving signal is generated; when C is present 1 In the low state, the primary driving signal is normal, C 2 The level is clamped to a high state.
6. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
drive control circuit K 3 In, C 2 A control pin connected to the secondary side drive chip according to C 2 When C is the level state of the secondary side drive signal 2 When the level state of the secondary side driving chip is high, the primary side driving signal is normal, the secondary side driving chip normally sends out a secondary side driving signal, and when the level state of the secondary side driving chip is high, the secondary side driving signal is sent out 2 When the level state of the primary side driving chip is low level, the primary side driving signal disappears, and the secondary side driving chip stops sending out the secondary side driving signal, so that the primary side driving signal and the secondary side driving signal are simultaneously output and controlled.
7. The current-backflow-preventing sequential synchronous control circuit for the isolated DC-DC as claimed in claim 1, wherein:
the primary side PWM control chip adopts a UC1825ALQMLV chip, the secondary side drive chip adopts a UC1715W-SP chip, and a control pin is an ENBL pin of the UC1715W-SP chip.
CN202210554563.XA 2022-05-19 2022-05-19 Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC Pending CN114977107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210554563.XA CN114977107A (en) 2022-05-19 2022-05-19 Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210554563.XA CN114977107A (en) 2022-05-19 2022-05-19 Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC

Publications (1)

Publication Number Publication Date
CN114977107A true CN114977107A (en) 2022-08-30

Family

ID=82984707

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210554563.XA Pending CN114977107A (en) 2022-05-19 2022-05-19 Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC

Country Status (1)

Country Link
CN (1) CN114977107A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115811237A (en) * 2023-01-17 2023-03-17 长城电源技术有限公司 Synchronous rectification control circuit and control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115811237A (en) * 2023-01-17 2023-03-17 长城电源技术有限公司 Synchronous rectification control circuit and control method

Similar Documents

Publication Publication Date Title
US7224590B2 (en) Forward converter with synchronous rectifier and reverse current control
CN103094884B (en) System and method of power conversion system on condition of open circuit and/or short circuit
CN100571001C (en) Switching regulaor
US9240739B2 (en) Driving system for driving switching element
TW201251287A (en) Constant on-time switching regulator implementing dual control loops
CN107271756B (en) Load voltage detection circuit and method
US20230369960A1 (en) Zero-crossing State Detection Device for Converter
CN114977107A (en) Current-backflow-preventing sequential synchronous control circuit for isolated DC-DC
JP4687839B2 (en) 3-phase power supply phase loss detection circuit
CN113726165A (en) Flyback converter and control method thereof
CN110504832B (en) Control circuit and method for high-voltage BUCK switch converter
CN109149968B (en) Synchronous rectifier diode and synchronous rectification control circuit
CN110831284B (en) LED driving power supply and controller thereof
US11644502B2 (en) Circuit and method for reducing interference of power on/off to hardware test
KR20210079936A (en) Ground fault detection method and apparatus
CN216122649U (en) Power correction circuit of television switching power supply
CN104617751A (en) Audion drive circuit and drive method
CN209858693U (en) Bipolar transistor performance detection device
TWI477047B (en) High boost power conversion device
CN211530997U (en) Regulating circuit and BUCK circuit
CN112165247B (en) Zero current sampling method and circuit of bridgeless PFC circuit
CN114364097A (en) Buffer circuit for LED drive circuit, LED drive circuit and control method thereof
CN112462131A (en) Commercial power zero-crossing detection circuit and non-isolated power supply system applying same
CN101378197B (en) Charger with boundary mode control
CN216056801U (en) Power converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination