CN115796111A - File processing method suitable for agf, computer equipment and readable storage medium - Google Patents

File processing method suitable for agf, computer equipment and readable storage medium Download PDF

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CN115796111A
CN115796111A CN202211379995.8A CN202211379995A CN115796111A CN 115796111 A CN115796111 A CN 115796111A CN 202211379995 A CN202211379995 A CN 202211379995A CN 115796111 A CN115796111 A CN 115796111A
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file
information
unit
chip
name
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张涵
王子彧
陈熙
贺青
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Tongji University
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Tongji University
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Abstract

The application relates to a file processing method, computer equipment and a readable storage medium suitable for agf, wherein the file processing method comprises the following steps: acquiring a target file, wherein layout information of at least one chip unit is stored in the target file; reading the layout information of each chip unit from the target file, and storing the layout information in a unit file corresponding to each chip unit; establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of the layout information in each unit file; and taking the index information as the file name of the corresponding unit file. When the information is read, the storage position of the information to be searched in the unit file is searched in the file name of the unit file according to the information name, and the information to be searched is read. According to the method and the device, the index information of the file content is stored as the file name, so that the information can be quickly inquired and obtained, and the operation efficiency of multi-process data processing is improved.

Description

File processing method suitable for agf, computer equipment and readable storage medium
Technical Field
The application relates to the technical field of data processing, in particular to a agf file processing method, computer equipment and a readable storage medium.
Background
In the chip design process, after design criteria verification (DRC) and circuit Layout Verification (LVS) are performed, parasitic parameter extraction is performed. The DRC and LVS tool most commonly used at present is calibre, the output of which is a CCI file, which contains layout connection information of the chip extracted by the LVS and is a common input file of parasitic parameter extraction software. In the CCI file, the. agf file is a binary file, and stores all the graphic information in the layout in a hierarchical structure (hierarchy), and the. agf file uses a chip unit (cell) as a basic unit, and the chip unit includes an instance (instance) of a chip sub-unit and graphics under different masks (masks).
When the existing parasitic parameter reading software reads a agf file in a CCI file, all information is read from a agf file in sequence and is kept in a memory mainly according to GDSII specifications. When the chip has a large scale, a multi-process method is usually adopted to process data, and finally, the processing results are integrated. However, since each process is independent, the information obtained from the agf file needs to be allocated to each process, which not only wastes a lot of time in the allocation process, but also occupies a lot of memory for repeated data, resulting in low efficiency.
Disclosure of Invention
In view of the above technical problems, the present application provides a file processing method, an information reading method, a computer device, and a storage medium, in which index information of file contents is stored as a file name, so that information can be quickly queried and obtained, and the operation efficiency of multi-process data processing is improved.
Technical scheme one
A file processing method is suitable for a agf file, and is characterized by comprising the following steps of:
step 1, a writing step for establishing a database, specifically comprising the following steps:
acquiring a target file, wherein layout information of at least one chip unit is stored in the target file;
reading layout information of each chip unit from the target file, and storing the layout information in unit files corresponding to the chip units;
establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of layout information in each unit file;
taking the index information as the file name of the corresponding unit file;
step 2, reading information, namely reading the file processed in the step 1, and specifically comprising the following steps of:
acquiring an information name of information to be searched;
searching the storage position of the information to be searched in the file name of the unit file according to the information name;
and reading the information to be searched from the unit file according to the storage position.
The method is characterized in that reading layout information of each chip unit from the target file comprises:
obtaining the unit name of the at least one chip unit from the netlist file;
and respectively searching the layout information of each chip unit in the target file according to the unit name of the at least one chip unit.
The method is characterized in that the index information comprises the information name of the layout information, the element number of the information and the offset address of the information.
The method is characterized in that the step of establishing index information corresponding to each unit file comprises the following steps:
determining initial index information, wherein the initial index information comprises an information name of layout information of a chip unit, the number of elements of the information and an initial offset address of the information;
writing layout information with element number not being 0 in the unit file, and recording an actual offset address;
and assigning the actual offset address to the initial offset address to generate index information of the unit file.
The method is characterized by further comprising the following steps:
before determining initial index information, counting the maximum file size of a unit file according to layout information, and newly building the unit file;
and after the index information of the unit file is generated, resetting the file size of the unit file according to the value of the maximum offset address in the unit file.
The method is characterized in that the step of storing the layout information in the unit file corresponding to each chip unit comprises the following steps:
acquiring graph data of the same layer of graph in the layout information, wherein the graph data comprises vertex coordinates of each graph;
sequencing the vertex coordinates, and determining the position attribute of each vertex of the graph in the same layer;
and taking the vertex coordinates and the position attributes of the corresponding vertexes as converted graphic data and storing the graphic data in unit files corresponding to the chip units.
The method is characterized in that the step of sequencing the vertex coordinates and determining the position attribute of each vertex of the graph in the same layer comprises the following steps:
respectively sequencing the abscissa and the ordinate of the vertex coordinates of all the graphs;
determining sequence marks of each abscissa and each ordinate according to the sequencing result;
mapping each vertex coordinate into a sequence number group consisting of a sequence mark of an abscissa and a sequence mark of an ordinate so as to obtain a position attribute of the corresponding vertex;
the step of taking the vertex coordinates and the position attributes of the corresponding vertices as converted graphic data and storing the converted graphic data in unit files corresponding to the chip units includes:
combining the vertex name and the position attribute of the vertex in a 2D vector format;
and taking the combined data and the vertex coordinates as converted graph data and storing the converted graph data in a unit file corresponding to each chip unit.
A computer device, comprising: the device comprises a memory and a processor, wherein the memory is stored with an operating program, and the processing program realizes the method when being executed by the processor.
A readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the method.
The file processing method, the information reading method, the computer device and the storage medium of the application comprise the following steps: acquiring a target file, wherein layout information of at least one chip unit is stored in the target file; reading the layout information of each chip unit from the target file, and storing the layout information in a unit file corresponding to each chip unit; establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of the layout information in each unit file; and taking the index information as the file name of the corresponding unit file. When the information is read, the storage position of the information to be searched in the unit file is searched in the file name of the unit file according to the information name, and the information to be searched is read. According to the method and the device, the index information of the file content is stored as the file name, so that the information can be quickly inquired and obtained, and the operation efficiency of multi-process data processing is improved.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating a document processing method according to an embodiment of the present application;
fig. 2 is a graph illustrating comparison of effects of (a) before conversion and (b) after conversion of graphic data according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application is provided for illustrative purposes, and other advantages and capabilities of the present application will become apparent to those skilled in the art from the present disclosure.
In the following description, reference is made to the accompanying drawings that describe several embodiments of the application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Although the terms first, second, etc. may be used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
Also, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
Fig. 1 is a flowchart illustrating a document processing method according to an embodiment of the present application. As shown in fig. 1, the file processing method according to the embodiment of the present application includes the following steps:
s1, acquiring a target file, wherein layout information of at least one chip unit is stored in the target file;
s2, reading layout information of each chip unit from the target file, and storing the layout information in a unit file corresponding to each chip unit;
s3, establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of the layout information in each unit file;
and S4, taking the index information as the file name of the corresponding unit file.
By the method, the data read from the target file does not need to be left in the memory, but only the index information can be kept in the hard disk, and the method is more suitable for operation of a distributed system. When the multi-process scheme is used, each process does not need to copy layout information with huge data volume, but transmits light-weight index information, and when some information is needed, the information can be quickly inquired and obtained according to the guidance of the index information, so that the operation efficiency of multi-process data processing is effectively improved. In addition, the index information is used as the file name, the storage position of the searched information in the file can be quickly positioned, and the data searching speed is improved.
The target file may be a agf file, which stores all graphic information in a layout with hierarchy structure, and a agf file uses a chip unit (cell) as a basic unit, and the chip unit includes an instance (instance) of a chip sub-unit and graphics under different masks (masks). It is understood that the type of the target file is not limited thereto, and may be other types of layout information suitable for storing the chip unit.
Optionally, in the step S2, reading layout information of each chip unit from the target file, where the reading includes:
obtaining the unit name of at least one chip unit from the netlist file;
and respectively searching the layout information of each chip unit in the target file according to the unit name of at least one chip unit.
The netlist file (. Nl) corresponding to the layout design stores unit names of all the chip units, and after the unit names of at least one chip unit are obtained from the netlist file, the position of each chip unit can be found in the target file, so that the layout information of each chip unit is read and obtained. Taking the target file agf as an example, the operation is read-only for the agf file, and the chip units in the agf file are arranged in parallel, so that the reading operation of the chip units can be independent of each other, and the reading operation of all the chip units can be completed in parallel. After the layout information of each chip unit is read from the target file, the layout information is stored in the unit file corresponding to each chip unit.
Optionally, the unit file of each chip unit may include a file name and file content, where the file name is named using index information, and the file content includes layout information such as an instance (instance) of a chip sub-unit and a graph under a different mask (mask). Optionally, the index information includes an information name of the layout information, a number of elements of the information, and an offset address of the information, where the elements may be instances of chip sub-units, patterns of masks, and the like.
Optionally, the step S3 includes:
determining initial index information, wherein the initial index information comprises an information name of layout information of a chip unit, the number of elements of the information and an initial offset address of the information;
writing layout information with element number not being 0 in the unit file, and recording an actual offset address;
and assigning the actual offset address to the initial offset address to generate index information of the unit file.
Wherein, the initial offset address is assigned as-1, and is the default offset address of the information when the number of elements is 0. Writing the layout information with the element number not being 0 into the end of the file, and recording a corresponding actual offset address, wherein optionally, the actual offset address is the actual offset address of the first element. Then, assigning the actual offset address to the initial offset address, where the information name of the layout information of the chip unit, the number of elements of the information, and the actual offset address of the information form index information of a unit file, and the index information of one unit file may be as follows:
instance_list 3 36
mask_num 2 100
mask_offset 2 108,
the first row represents an example that the chip unit comprises three chip sub-units, the offset address of the first chip sub-unit is 36, and the specific layout information of the first chip sub-unit can be obtained by locating the 36 th position of the unit file. The second and third lines describe the own graphics of the chip unit, and all the graphics information of the specified mask can be quickly taken through the index information.
Optionally, the method of this embodiment may further include:
before determining initial index information, counting the maximum size of a unit file according to layout information, and creating a new unit file;
after the index information of the unit file is generated, the size of the unit file is reset according to the value of the maximum offset address in the unit file.
When reading and storing information from the target file, the maximum size of the file can be counted according to the existing information, and the unit file is newly built and set. After the setting of the file name is completed, the size of the file may be reset according to the value of the maximum offset address in the file in order to avoid the file being too large.
The layout information read from the target file is usually the same as the layout information stored in the target file, and for example, the agf file, the graphic data exists in the following form:
Figure BDA0003927979740000061
it can be seen that in the original graphics data, a layer of graphics contains several polygons, where each polygon is composed of interconnected edges, each edge further composed of two vertices. However, in EDA tools, a lot of operations are often performed on graphics, such as boolean operations on different mask graphics, or relationships between graphics within the same mask, such as overlapping, connecting, adjacent relationships, etc., are often obtained, and the above description makes it difficult to obtain the relative relationship between polygons, because graphics operations usually require two-by-two operations on all polygons, resulting in unacceptable O (N2) complexity. When some fast algorithms are introduced, temporary data structure conversion needs to be carried out on the polygon, and the conversion time cannot be ignored when the operation times are huge. Therefore, the method for converting the graphic data is provided, the position relation of the graphic can be clearly described, the space is saved (repeated point and coordinate information is compressed), and the subsequent rapid introduction of the graphic operation algorithm is facilitated. The storage of the chip unit data or the conversion of the graphic format can be completed in linear time and can be completed in parallel, so that the operation speed of the EDA tool is increased on the whole.
Based on the concept of converting the graphic data, optionally, in the step S2, storing the layout information in the unit file corresponding to each chip unit, including the following steps:
acquiring graph data of the same layer of graph in the layout information, wherein the graph data comprises vertex coordinates of each graph;
sequencing the vertex coordinates, and determining the position attribute of each vertex of the same layer of graph;
and taking the vertex coordinates and the position attributes of the corresponding vertexes as converted graphic data and storing the graphic data in unit files corresponding to the chip units.
The relative position relation of each vertex of the same layer of graph can be clarified by determining the position attribute of each vertex of the same layer of graph. Taking fig. 2 as an example, in (a), two graphs have 8 vertex coordinates corresponding thereto, and there is no clear relative position attribute between them before conversion, such as an order of arrangement, and in (b), 8 vertex coordinates are converted into 8 points in a sequence relationship of P1 to P8, having a specific order. Taking the example of finding adjacent graphs, if the graph format in the agf file is directly used, as shown in fig. 2 (a), it is very difficult to visually see the adjacent relation of the graphs, and when all other graphs are checked and compared for a certain graph, the complexity of O (N2) or more is easily generated. However, after the graphic data is converted, as shown in fig. 2 (b), the adjacency relation of the graphics can be expressed at the relative positions of the points, and based on this configuration, it becomes simple to extract the adjacency relation: and defining a scanning line, and starting scanning from bottom to top. Firstly, two points P2 and P3 are scanned, the positions and information of the points P2 and P3 are recorded on a scanning line, then when the points P6 and P7 are scanned, the adjacency of the polygon where the points P7 and P2 are located can be judged based on the record on the scanning line, and the like, the adjacency relation of all the graphs can be obtained as long as one-time data scanning is carried out along a certain direction, so that the calculation among irrelevant graphs can be reduced as much as possible by utilizing a new format, and the graph operation efficiency is improved.
Optionally, the step of sorting the vertex coordinates and determining the position attribute of each vertex of the same layer of graph includes:
respectively sequencing the abscissa and the ordinate of the vertex coordinates of all the graphs;
determining sequence marks of each abscissa and each ordinate according to the sequencing result;
each vertex coordinate is mapped to a sequence number group consisting of a sequence mark of an abscissa and a sequence mark of an ordinate to obtain a position attribute of the corresponding vertex.
First, taking the example shown in fig. 2 (b) as an example, 8 independent points can be obtained by traversing a polygon once, and an abscissa sequence and an ordinate sequence of vertex coordinates can be obtained by traversing the points, respectively, with the following results:
x position list[3.2,3.53,1.24,1.82]
y position list[-0.12,-2.1,-0.95],
the abscissa and ordinate at this time are unordered, and the abscissa and ordinate of the vertex coordinates of all the figures are sorted respectively, with the following results:
x position list[1.24 1.82 3.2 3.53]
y position list[-2.1 -0.95 -0.12],
at this time, according to the sorting result, the sequence flag of each abscissa and each ordinate can be determined, for example, if the sequence flag corresponding to the abscissa 1.82 is 1, it means that it is the 2 nd element in the x-position list (similarly, the sequence flag of the first element 1.24 is 0). The purpose of using sequence marks is to facilitate subsequent graphic operations and to quickly access the original coordinate values. According to the sorting result, the corresponding relation between the coordinates and the sequence marks is as follows:
Position-index map
Figure BDA0003927979740000081
next, mapping each vertex coordinate to a sequence number group formed by the sequence marks of the abscissa and the sequence marks of the ordinate, and completing the conversion of the sequence marks of all the points, wherein the process is as follows: traversing all the points, obtaining the value of the sequence mark through a coordinate lookup table of the points, and expressing the 8 points of the two rectangles after conversion by the following method:
Point position-index mapping
P1:(3.2,-0.12)->(2,2)
P2:(3.2,-2.1)->(2,0)
P3:(3.53,-2.1)->(3,0)
P4:(3.53,-0.12)->(3,2)
P5:(1.24,-0.12)->(0,2)
P6:(1.24,-0.95)->(0,1)
P7:(1.82,-0.95)->(1,1)
P8:(1.82,-0.12)->(1,2),
thus, taking P2 (2,0) as an example, when the output result requires real coordinates, the real coordinates of P2 can be obtained by querying the sequence of the abscissa or the ordinate using the sequence tag as follows:
x_position_list[2]=3.2;y_position_list[0]=-2.1
P2(2,0)->P2(3.2,-2.1)。
after determining the position attribute of each vertex of the same layer of graph, optionally, taking the vertex coordinates and the position attribute of the corresponding vertex as converted graph data, and storing the converted graph data in a unit file corresponding to each chip unit, including:
combining the vertex name and the position attribute of the vertex in a 2D vector format;
and storing the combined data and the vertex coordinates as converted graphic data in a unit file corresponding to each chip unit.
Wherein, a series of points are sorted according to sequence marks and stored in the unit file, which may specifically be: all points are sorted according to the ordinate first, and then points located on the same ordinate are sorted according to the abscissa again. Taking the format of the 2D vector as an example, the final output result is as follows:
Point 2D vector
y=0:{(2,P2),(3,P3)};
y=1:{(0,P6),(1,P7)};
y=2:{(0,P5),(1,P8),(2,P1),(3,P4)},
finally, combining the information to obtain the graphic data of a layer of graphics in the converted chip unit:
x position list[1.24 1.82 3.2 3.53]
y position list[-2.1 -0.95 -0.12]
Point 2D vector
y=0:{(2,P2),(3,P3)};
y=1:{(0,P6),(1,P7)};
y=2:{(0,P5),(1,P8),(2,P1).(3,P4)}。
in practical implementation, in the layout design process, the decimal place (dbu) and the precision place (k) of the graph have uniform requirements, so that the coordinate values can be converted into integers firstly through the decimal places and the precision places provided in the design file, and then the integers are sequenced.
The file processing method comprises the following steps: acquiring a target file, wherein layout information of at least one chip unit is stored in the target file; reading the layout information of each chip unit from the target file, and storing the layout information in the unit file corresponding to each chip unit; establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of the layout information in each unit file; and taking the index information as the file name of the corresponding unit file. When the information is read, the storage position of the information to be searched in the unit file is searched in the file name of the unit file according to the information name, and the information to be searched is read. According to the method and the device, the index information of the file content is stored as the file name, so that the information can be quickly inquired and obtained, and the operation efficiency of multi-process data processing is improved.
After the file is processed by the file processing method in the above embodiment, the information in the file can be read based on the file name of the unit file.
As shown in fig. 1, the process of reading information includes the following steps:
s5, acquiring an information name of the information to be searched;
s6, searching the storage position of the information to be searched in the unit file in the file name of the unit file according to the information name;
and S7, reading the information to be searched from the unit file according to the storage position.
In this way, when some information is needed, the index information can be quickly inquired and acquired according to the guidance of the index information, and the data inquiry speed is improved. In addition, when a multi-process scheme is used, each process does not need to copy layout information with huge data quantity, but transmits light-weight index information, and the operation efficiency of multi-process data processing is effectively improved. The setting mode of the index information is detailed in the above description, and is not repeated herein.
The present application further provides a computer device, comprising: the device comprises a memory and a processor, wherein the memory stores an operating program, and the processing program realizes the method of the above embodiment when being executed by the processor.
The present application also provides a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method as described in the above embodiments.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.

Claims (9)

1. A file processing method suitable for agf is characterized by comprising the following steps:
step 1, a writing step for establishing a database, specifically comprising the following steps:
acquiring a target file, wherein layout information of at least one chip unit is stored in the target file;
reading layout information of each chip unit from the target file, and storing the layout information in a unit file corresponding to each chip unit;
establishing index information corresponding to each unit file, wherein the index information is used for recording the storage position of layout information in each unit file;
taking the index information as the file name of the corresponding unit file;
step 2, reading information, specifically comprising the following steps of:
acquiring an information name of information to be searched;
searching the storage position of the information to be searched in the file name of the unit file according to the information name;
and reading the information to be searched from the unit file according to the storage position.
2. The method according to claim 1, wherein reading layout information of each of the chip units from the target file comprises:
acquiring a unit name of the at least one chip unit from the netlist file;
and respectively searching the layout information of each chip unit in the target file according to the unit name of the at least one chip unit.
3. The method according to claim 1, wherein the index information comprises information names of layout information, element numbers of information, and offset addresses of information.
4. The method of claim 3, wherein the step of creating index information corresponding to each of the unit files comprises:
determining initial index information, wherein the initial index information comprises an information name of layout information of a chip unit, the number of elements of the information and an initial offset address of the information;
writing layout information with the element number not being 0 into the unit file, and recording an actual offset address;
and assigning the actual offset address to the initial offset address to generate index information of the unit file.
5. The method of claim 4, further comprising:
before determining initial index information, counting the maximum file size of a unit file according to layout information, and newly building the unit file;
after the index information of the unit file is generated, the file size of the unit file is reset according to the value of the maximum offset address in the unit file.
6. The method according to any one of claims 1 to 5, wherein the storing the layout information in a unit file corresponding to each chip unit comprises the following steps:
acquiring graph data of the same layer of graph in the layout information, wherein the graph data comprises vertex coordinates of each graph;
sequencing the vertex coordinates, and determining the position attribute of each vertex of the same layer of graph;
and taking the vertex coordinates and the position attributes of the corresponding vertexes as converted graphic data and storing the graphic data in unit files corresponding to the chip units.
7. The method of claim 6, wherein the step of ordering the vertex coordinates and determining the position attributes of the vertices of the same layer of graphics comprises:
respectively sequencing the abscissa and the ordinate of the vertex coordinates of all the graphs;
determining sequence marks of each abscissa and each ordinate according to the sequencing result;
mapping each vertex coordinate into a sequence number group consisting of a sequence mark of an abscissa and a sequence mark of an ordinate so as to obtain a position attribute of the corresponding vertex;
the step of taking the vertex coordinates and the position attributes of the corresponding vertices as converted graphic data and storing the converted graphic data in unit files corresponding to the chip units includes:
combining the vertex name and the position attribute of the vertex in a 2D vector format;
and taking the combined data and the vertex coordinates as converted graph data and storing the converted graph data in a unit file corresponding to each chip unit.
8. A computer device, comprising: memory, a processor, wherein the memory has stored thereon an operating program which, when executed by the processor, implements the method of any one of claims 1-7.
9. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the method according to any one of claims 1-8.
CN202211379995.8A 2022-11-04 2022-11-04 File processing method suitable for agf, computer equipment and readable storage medium Pending CN115796111A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117576249A (en) * 2024-01-19 2024-02-20 弈芯科技(杭州)有限公司 Chip layout data processing method and device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117576249A (en) * 2024-01-19 2024-02-20 弈芯科技(杭州)有限公司 Chip layout data processing method and device
CN117576249B (en) * 2024-01-19 2024-04-02 弈芯科技(杭州)有限公司 Chip layout data processing method and device

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