CN116881515A - Method and electronic equipment for comparing capacitance results solved by different algorithms - Google Patents
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Abstract
The application relates to a method and electronic equipment for comparing capacitance results solved by different algorithms. The method comprises the following steps: acquiring first capacitance extraction information and second capacitance extraction information which are obtained by extracting parasitic capacitance from a target circuit layout by adopting different algorithms, wherein the first capacitance extraction information comprises graphic information of a first node and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of a second node and second capacitances among different second nodes; determining at least one target second node pair matched with the at least one target first node pair according to the graphic information; acquiring a first capacitor of at least one target first node pair and a second capacitor of at least one target second node pair; and outputting a comparison result of the capacitors. According to the application, the nodes determined based on different algorithms are matched based on the node graph information, so that the comparison result of the capacitors solved by the different algorithms is determined, and the comparison efficiency of the capacitors solved by the different algorithms can be improved.
Description
Technical Field
The application belongs to the technical field of circuits, and particularly relates to a method and electronic equipment for comparing capacitance results solved by different algorithms.
Background
In order to improve the accuracy of the algorithm to extract the parasitic capacitance of the integrated circuit, the capacitances solved by different algorithms are generally compared, and a predefined circuit model is adjusted to correct the deviation of the extraction result according to the capacitance comparison result. Taking the model matching algorithm to extract the parasitic capacitance of the circuit as an example, in order to improve the accuracy of the model matching algorithm to extract the parasitic capacitance of the circuit, the capacitance solved based on the model matching algorithm and the capacitance solved based on the field solving algorithm can be compared, and a predefined circuit model is adjusted according to the capacitance comparison result to correct the deviation between the capacitance solved based on the model matching algorithm and the capacitance solved based on the field solving algorithm.
However, at present, capacitors solved based on different algorithms are compared in a manual comparison mode, for example, keywords of one algorithm output file and keywords of another algorithm output file are captured according to a script language, and then the capacitors solved based on the different algorithms are compared according to the capacitor keywords, so that the efficiency is low.
Disclosure of Invention
Aiming at the technical problems, the application provides a method and electronic equipment for comparing capacitance results solved by different algorithms, which can improve the comparison efficiency of the capacitance solved by different algorithms.
The application provides a method for comparing capacitance results solved by different algorithms, which comprises the following steps:
acquiring first capacitance extraction information and second capacitance extraction information, wherein the first capacitance extraction information and the second capacitance extraction information are obtained by extracting parasitic capacitance from a target circuit layout by adopting different algorithms, the first capacitance extraction information comprises graphic information of a first node in a first node set and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of a second node in a second node set and second capacitances among different second nodes;
determining at least one target second node pair in the second node set matched with at least one target first node pair in the first node set according to the graphic information of the first node set and the graphic information of the second node set;
acquiring a first capacitor of the at least one target first node pair and a second capacitor of the at least one target second node pair;
And outputting a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair.
In one embodiment, the step of determining at least one target second node pair in the second node set that matches at least one target first node pair in the first node set according to the graphic information of the first node set and the graphic information of the second node set includes:
determining, in response to a node selection operation, the at least one target first node pair among the first node set, one target first node pair including a first target node and a second target node;
determining a third target node matched with the first target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set, determining a fourth target node matched with the second target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set, and forming a target second node pair by the third target node and the fourth target node.
In one embodiment, the step of determining a third target node matching the first target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set includes:
determining the graphic information of the first target node according to the graphic information of the first node set;
determining at least one target node to be matched with the first target node in the second node set according to the network position of the first target node in the target circuit layout;
according to the graphic information of the second node set, the graphic information of at least one target node to be matched with the first target node is obtained;
determining a first graph overlapping rate according to the graph information of the first target node and the graph information of at least one target node to be matched with the first target node;
and determining a third target node matched with the first target node in the at least one target node to be matched with the first target node according to the first graph overlapping rate.
In one embodiment, the step of determining a fourth target node matching the second target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set includes:
Determining the graphic information of the second target node according to the graphic information of the first node set;
determining at least one target node to be matched with the second target node in the second node set according to the network position of the second target node in the target circuit layout;
according to the graphic information of the second node set, the graphic information of at least one target node to be matched with the second target node is obtained;
determining a second graph overlapping rate according to the graph information of the second target node and the graph information of at least one target node to be matched with the second target node;
and determining a fourth target node matched with the second target node in the at least one target node to be matched with the second target node according to the second graph overlapping rate.
In one embodiment, the network location includes a layer in which a node is located in the target circuit layout and a circuit network in which the node is located;
the step of determining at least one target node in the second node set to be matched with the first target node according to the network position of the first target node in the target circuit layout includes:
Determining at least one node in the second node set, which is in the same layer as the first target node and in the same circuit network as the first target node, as at least one target node to be matched with the first target node;
the step of determining at least one target node to be matched with the second target node in the second node set according to the network position of the second target node in the target circuit layout includes:
and determining at least one node in the second node set, which is in the same layer as the second target node and in the same circuit network as the second target node, as at least one target node to be matched with the second target node.
In one embodiment, the step of determining at least one target second node pair in the second node set that matches at least one target first node pair in the first node set according to the graphic information of the first node set and the graphic information of the second node set includes:
determining, in response to a node selection operation, the at least one target first node pair among the first node set, one target first node pair including a first target node and a second target node;
Determining at least one target node pair to be matched with the target first node pair in the second node set according to the network positions of the first target node and the second target node in the target circuit layout;
calculating the graph overlapping rate between the target first node pair and each target node pair according to the graph information of the target first node pair and the graph information of the at least one target node pair;
and determining a target second node pair matched with the target first node pair in the at least one target node pair according to the graph overlapping rate.
In one embodiment, one of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information obtained by converting three-dimensional graphic information obtained by calculation of a first algorithm; the other of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information calculated by a second algorithm.
In one embodiment, the step of outputting a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair includes:
Outputting an interface according to a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair;
the interface comprises a plurality of comparison results, and each comparison result comprises a name of the first capacitor, a name of one target first node pair corresponding to the first capacitor, a value of a second capacitor corresponding to the first capacitor and an error between the value of the first capacitor and the value of the corresponding second capacitor.
In one embodiment, after the step of outputting a comparison of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair, the method further comprises:
and responding to the selection operation of the target comparison result, outputting the graph of the first node in the first node set and the graph of the second node in the second node set, and identifying the graph of the target first node pair corresponding to the target comparison result and the graph of the target second node pair matched with the target first node pair corresponding to the target comparison result.
The application also provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of comparing the capacitance results solved by different algorithms when executing the computer program.
The application also provides a computer storage medium storing a computer program which when executed by a processor implements the steps of the above method of comparing capacitance results of different algorithm solutions.
According to the method and the electronic equipment for comparing the capacitance results solved by different algorithms, first capacitance extraction information and second capacitance extraction information which are obtained by extracting parasitic capacitance from a target circuit layout by different algorithms are obtained, wherein the first capacitance extraction information comprises graphic information of a first node and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of a second node and second capacitances among different second nodes; determining at least one target second node pair matched with the at least one target first node pair according to the graphic information; acquiring a first capacitor of at least one target first node pair and a second capacitor of at least one target second node pair; and outputting a comparison result of the capacitors. According to the scheme provided by the application, the nodes determined based on different algorithms are matched based on the node graph information, so that the comparison result of the capacitors solved by the different algorithms is determined, and the comparison efficiency of the capacitors solved by the different algorithms can be improved.
Drawings
Fig. 1 is a flowchart of a method for comparing capacitance results obtained by solving different algorithms according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a node according to a first embodiment of the present application.
Fig. 3 is a schematic diagram illustrating conversion from 3D graphics to 2D graphics of a node according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an output interface of a capacitance comparison result according to an embodiment of the application.
Fig. 5 is a schematic diagram of a node corresponding to a capacitance comparison result according to an embodiment of the present application.
Fig. 6 is a schematic flow chart of a method for comparing capacitors solved by different algorithms according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of an electronic device according to a second embodiment of the present application.
Detailed Description
The technical scheme of the application is further elaborated below by referring to the drawings in the specification and the specific embodiments. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 is a flowchart of a method for comparing capacitance results obtained by solving different algorithms according to an embodiment of the present application. As shown in fig. 1, the method of the present application may include the steps of:
step S10: acquiring first capacitance extraction information and second capacitance extraction information, wherein the first capacitance extraction information and the second capacitance extraction information are obtained by extracting parasitic capacitance from a target circuit layout by adopting different algorithms, the first capacitance extraction information comprises graphic information of first nodes in a first node set and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of second nodes in a second node set and second capacitances among different second nodes;
step S20: determining at least one target second node pair in the second node set matched with at least one target first node pair in the first node set according to the graphic information of the first node set and the graphic information of the second node set;
step S30: acquiring a first capacitor of at least one target first node pair and a second capacitor of at least one target second node pair;
step S40: and outputting a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair.
According to the method provided by the embodiment of the application, based on the graph information of the nodes extracted from the same circuit by different algorithms, at least one node pair forming the capacitor determined by the different algorithms is matched, so that the comparison result of the solved capacitors of the different algorithms is obtained, and the comparison efficiency of the capacitors solved on the basis of the different algorithms can be improved.
The different algorithms include a first algorithm by which one of the graphic information of the first node set and the graphic information of the second node set is obtained and a second algorithm by which the other of the graphic information of the first node set and the graphic information of the second node set is obtained. Correspondingly, the first capacitance is obtained based on an algorithm for obtaining the graphic information of the first node set, and the second capacitance is obtained based on an algorithm for obtaining the graphic information of the second node set.
Optionally, the first algorithm and the second algorithm are respectively a model matching algorithm and a field solving algorithm, or respectively different optimized versions of the same algorithm. Taking a model matching algorithm and a field solving algorithm as an example, inputting a design file (such as a process file) of a target circuit layout into a model matching solver, dividing each circuit network in the target circuit layout into a plurality of first nodes based on the model matching algorithm, and outputting graph information comprising the first nodes in the target circuit layout and first capacitance extraction information of first capacitances among different first nodes. The method comprises the steps of inputting design files of the same target circuit layout into a field solver, dividing each circuit network in the target circuit layout into a plurality of second nodes based on a field solving algorithm, and outputting graphic information comprising the second nodes in the target circuit layout and second capacitance extraction information of second capacitances among different second nodes. It will be appreciated that the second capacitance extraction information may also be solved by a model matching algorithm, and the first capacitance extraction information may also be solved by a field solving algorithm.
The model matching solver processes the 3D structure of the target circuit layout into a 2D graph, and the first node obtained based on the model matching algorithm is a 2D graph obtained by dividing each circuit network in the 2D graph of the target circuit layout, such as a rectangle shown in fig. 2 (a). The field solver processes the 3D structure of the target circuit layout into a 3D graph, the second node obtained based on the field solving algorithm is a 3D graph formed by one or more conductors next to each other in the 3D structure of the target circuit layout after dividing each circuit network in the 3D graph of the target circuit layout, and as shown in (b) of fig. 2, the shape of the conductors may be cuboid or quadrangular frustum.
Optionally, one of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information obtained by converting the three-dimensional graphic information obtained by the first algorithm calculation, and the other of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information obtained by the second algorithm calculation. When the first capacitance extraction information is obtained by solving a model matching algorithm, the graph information of the first node is two-dimensional graph information, the graph information comprises the coordinates of the vertexes or the boundary lines in the 2D graph of the first node under the coordinate system of the target circuit layout, when the graph information of the second node set is obtained by solving a field solving algorithm, the original graph information of the second node is three-dimensional graph information, the graph information comprises the coordinates of the vertexes or the boundary lines in the 3D graph of the second node under the coordinate system of the target circuit layout, and then the two-dimensional graph information is obtained through conversion.
In one embodiment, when the graphic information of the second node set is obtained by solving by the field solution algorithm, before step S20, the method includes:
the graphical information of the second set of nodes is converted from three-dimensional graphical information to two-dimensional graphical information.
As shown in fig. 3, assuming that the graph of the first node is located on a plane formed by an X axis and a Y axis in the coordinate system of the target circuit layout, setting the Z axis coordinate of the graph boundary in the three-dimensional graph information of the second node under the coordinate system of the target circuit layout to be 0, that is, projecting the 3D graph of the second node onto the plane where the graph of the first node is located to obtain a plurality of 2D graphs, merging the plurality of 2D graphs obtained by projection according to the maximum boundary (such as the boundary of the graph formed by the plurality of 2D graphs in fig. 3), generating the 2D graph of the second node (such as the rectangle obtained by 3D to 2D conversion in fig. 3), and extracting the coordinate of the boundary in the 2D graph of the second node to obtain the two-dimensional graph information of the second node.
In one embodiment, step S20 includes:
determining at least one target first node pair in the first node set in response to the node selection operation, the one target first node pair including a first target node and a second target node;
According to the graphic information of the first node set and the graphic information of the second node set, a third target node matched with the first target node is determined in the second node set, and according to the graphic information of the first node set and the graphic information of the second node set, a fourth target node matched with the second target node is determined in the second node set, wherein the third target node and the fourth target node form a target second node pair.
Specifically, after one node is selected from the first node set, the node and other nodes may form a pair of nodes forming a capacitor, which is used as a target first node pair, where a capacitor is formed between a first target node and a second target node in the target first node pair. The third target node in the second node set is matched with the first target node in the first node set in a pattern mode, the fourth target node in the second node set is matched with the second target node in the first node set in a pattern mode, and the third target node and the fourth target node form a target second node pair in the second nodes.
In one embodiment, determining at least one target first node pair among the first node set in response to a node selection operation, comprises:
Determining a first target node of the target first node pair in response to the first node selection operation;
acquiring a node related to a first target node;
in response to the second node selection operation, a second target node of the target first node pair is determined from the nodes associated with the first target node.
By the method, the target first node pair which needs to be matched can be selected. In actual implementation, all target first node pairs in the first node set can be matched to obtain target second node pairs matched with each target first node pair.
The 3D structure of the target circuit layout is processed into a 2D graph by the model matching solver based on the model matching algorithm to carry out capacitance solving, the 3D structure of the target circuit layout is processed into a 3D graph by the field solver based on the field solving algorithm to carry out capacitance solving, and as the 2D graph and the 3D graph are both from the 3D structure of the same target circuit layout, the coordinates of the 2D graph and the 3D graph obtained by the two algorithm processing in the coordinate system of the target circuit layout cannot deviate too much no matter the 3D structure of the target circuit layout is processed into the 2D graph or the 3D graph, so that a third target node matched with a first target node in the first node set and a fourth target node matched with a second target node in the first node set can be determined in the second node set in a pattern matching mode, and rapid matching among nodes obtained by different algorithms is realized.
Optionally, the first capacitance extraction information further includes a network location of the first node in the target circuit layout, and the second capacitance extraction information further includes a network location of the second node in the target circuit layout.
In an embodiment, determining a third target node matching the first target node in the second node set according to the graph information of the first node set and the graph information of the second node set includes:
determining the graphic information of the first target node according to the graphic information of the first node set;
determining at least one target node to be matched with the first target node in the second node set according to the network position of the first target node in the target circuit layout;
according to the graphic information of the second node set, the graphic information of at least one target node to be matched with the first target node is obtained;
a first graph overlapping rate according to the graph information of the first target node and the graph information of at least one target node to be matched with the first target node;
and determining a third target node matched with the first target node in at least one target node to be matched with the first target node according to the first graph overlapping rate.
In an embodiment, determining a fourth target node matching the second target node in the second node set according to the graph information of the first node set and the graph information of the second node set includes:
Determining the graphic information of the second target node according to the graphic information of the first node set;
determining at least one target node to be matched with the second target node in the second node according to the network position of the second target node in the target circuit layout;
according to the graphic information of the second node set, the graphic information of at least one target node to be matched with the second target node is obtained;
determining a second graph overlapping rate according to the graph information of the second target node and the graph information of at least one target node to be matched with the second target node;
and determining a fourth target node matched with the second target node in at least one target node to be matched with the second target node according to the second graph overlapping rate.
Optionally, the network location includes a layer (layer) in which the node is located in the target circuit layout and a circuit network (net) in which the node is located. The network location of the first target node in the target circuit layout comprises a layer where the first target node is located in the target circuit layout and a circuit network where the first target node is located. The network location of the second target node in the target circuit layout includes a layer in which the second target node is located in the target circuit layout and a circuit network in which the second target node is located.
In one embodiment, determining at least one target node in the second set of nodes to be matched with the first target node according to the network location of the first target node in the target circuit layout includes:
at least one node in the second set of nodes at the same layer as the first target node and in the same circuit network as the first target node is determined as at least one target node to be matched with the first target node.
In one embodiment, the step of determining at least one target node in the second node set to be matched with the second target node according to the network position of the second target node in the target circuit layout includes:
and selecting at least one node in the second node set, which is in the same layer as the second target node and in the same circuit network as the second target node, as at least one target node to be matched with the second target node.
Specifically, at least one node which is in the same layer as the first target node and is in the same circuit network as the first screening condition is screened out from the second node set and is in accordance with the first screening condition and is used as at least one target node to be matched with the first target node, so that the node range to be matched with the first target node in the second node set can be reduced, and the efficiency of determining the target node matched with the first target node in the second node set is improved. And the second node is selected as at least one target node to be matched with the second target node, so that the node range of the second node set to be matched with the second target node can be reduced, the efficiency of determining the target node matched with the second target node in the second node set is improved, and the comparison efficiency of the capacitors solved based on different algorithms is further improved.
Alternatively, the pattern overlap ratio=a/(s1+s2-a), where a is the overlapping area of two patterns, S1 is the area of one pattern, and S2 is the area of the other pattern. The overlapping area is calculated according to the boundary coordinates of the two graphics, when the two rectangles are overlapped, the overlapping part of the two rectangles is also a rectangle, so when the vertex coordinates of the rectangles are known, the overlapping area of the two graphics can be calculated through line segment projection between the two rectangles, which is known to the person skilled in the art and is not repeated. The graph overlapping rate can show the similarity degree of the positions between the graphs, and the higher the graph overlapping rate is, the closer the positions between the two graphs can be indicated, so that the matching between the nodes can be carried out according to the graph overlapping rate.
Specifically, when the first graph overlapping rate and the second graph overlapping rate are calculated, the coordinates of the graph boundary of the first target node under the target circuit layout coordinate system and the coordinates of the graph boundary of the second target node under the target circuit layout coordinate system are respectively extracted from the graph information of the first node set, the graph area of the first target node can be determined according to the graph boundary coordinates of the first target node, and the graph area of the second target node can be determined according to the graph boundary coordinates of the second target node. After the graphic information of the second node is converted from the three-dimensional graphic information to the two-dimensional graphic information, the coordinates of the graphic boundary of at least one target node to be matched with the first target node under the target circuit layout coordinate system and the coordinates of the graphic boundary of at least one target node to be matched with the second target node under the target circuit layout coordinate system are respectively extracted from the graphic information of the second node set, the graphic area of at least one target node to be matched with the first target node can be determined according to the graphic boundary coordinates of at least one target node to be matched with the first target node, and the graphic area of at least one target node to be matched with the second target node can be determined according to the graphic boundary coordinates of at least one target node to be matched with the second target node. In some embodiments, the graph boundaries are represented by vertices or boundary lines of the graph. When the graphics are matched, the graphics overlapping rate can be calculated by combining the graphics area and the graphics boundary coordinates, so that the nodes corresponding to the positions can be accurately matched.
In one embodiment, determining a third target node to be matched with the first target node from the at least one target node to be matched with the first target node according to the graphic area and the graphic boundary coordinates of the first target node and the graphic area and the graphic boundary coordinates of the at least one target node to be matched with the first target node includes:
calculating the graph overlapping area of the first target node and at least one target node to be matched with the first target node according to the graph boundary coordinates of the first target node and the graph boundary coordinates of the at least one target node to be matched with the first target node;
determining a first graph overlapping rate between the first target node and at least one target node to be matched with the first target node according to the graph overlapping area, the graph area of the first target node and the graph area of the at least one target node to be matched with the first target node;
and if the first graph overlapping rate is greater than or equal to a preset threshold value, the corresponding target node is used as a third target node matched with the first target node.
Based on the formula for calculating the graph overlapping rate, the first graph overlapping rate between the first target node and at least one target node to be matched with the first target node can be calculated, and when the first graph overlapping rate is greater than or equal to a preset threshold value, the positions of the two graphs are indicated to be similar, the two graphs can be considered to be the same node, and the matching is successful. The preset threshold is preferably greater than or equal to 50% to improve the accuracy of the matching result.
In an embodiment, determining a fourth target node to be matched with the second target node in the at least one target node to be matched with the second target node according to the graphic area and the graphic boundary coordinates of the second target node and the graphic area and the graphic boundary coordinates of the at least one target node to be matched with the second target node includes:
calculating the graphic overlapping area of the second target node and the at least one target node to be matched with the second target node according to the graphic boundary coordinates of the second target node and the graphic boundary coordinates of the at least one target node to be matched with the second target node;
determining a second graph overlapping rate between the second target node and the at least one target node to be matched with the second target node according to the graph overlapping area, the graph area of the second target node and the graph area of the at least one target node to be matched with the second target node;
and if the second graph overlapping rate is greater than or equal to a preset threshold value, the corresponding target node is used as a fourth target node matched with the second target node.
Optionally, the process of determining the fourth target node is the same as the process of determining the third target node, and will not be described again.
Specifically, the first graph overlapping rate is greater than or equal to a preset threshold value as a first matching condition, so that a third target node matched with the first target node can be rapidly determined from at least one target node to be matched with the first target node. And the second graph overlapping rate is larger than or equal to a preset threshold value to serve as a second matching condition, so that a fourth target node matched with the second target node can be rapidly determined from at least one target node to be matched with the second target node, and the comparison efficiency of the capacitors solved based on different algorithms is further improved.
And obtaining a second target node pair matched with one target first node pair by determining a third target node matched with the first target node and a fourth target node matched with the second target node, and obtaining a second capacitor between the third target node and the fourth target node to obtain a comparison result of the first capacitor between the first target node and the second capacitor between the third target node and the fourth target node. And traversing the target nodes in all node pairs of the capacitor formed by the first node set and the selected nodes, and repeatedly executing the node matching process to determine the node pairs matched with all node pairs of the capacitor formed by the first node set in the second node set. And obtaining the second capacitances of the node pairs in the second node set, which are matched with all the node pairs forming the capacitances in the first node set, so as to obtain a comparison result of the first capacitances and the corresponding second capacitances of all the node pairs forming the capacitances in the first node set and the selected nodes.
In one embodiment, step S20 includes:
determining at least one target first node pair in the first node set in response to the node selection operation, the one target first node pair including a first target node and a second target node;
determining at least one target node pair to be matched with the target first node pair in the second node set according to the network positions of the first target node and the second target node in the target circuit layout;
calculating the graph overlapping rate between the target first node pair and each target node pair according to the graph information of the target first node pair and the graph information of at least one target node pair;
and determining a target second node pair matched with the target first node pair in at least one target pair according to the graph overlapping rate.
The process of determining the target second node pair is different from the process of determining the third target node and the fourth target node matched with the first target node and the second target node respectively, and the process of directly matching the target second node pair by adopting the graph overlapping rate between the node pairs can also be adopted.
According to the network positions of the first target node and the second target node in the target circuit layout, determining at least one target node pair to be matched with the target first node pair in the second node set, including:
Determining at least one fifth target node according to the network position of the first target node in the target circuit layout;
determining at least one sixth target node according to the network position of the second target node in the target circuit layout;
and determining at least one target node pair to be matched with the target first node pair in the second node set according to the relevance between the at least one fifth target node and the at least one sixth target node.
The method includes determining at least one fifth target node according to a network position of a first target node in a target circuit layout, and determining at least one sixth target node according to a network position of a second target node in the target circuit layout, wherein the content of the node to be matched can be determined according to the network position by referring to the foregoing, and will not be described again. The association between the at least one fifth target node and the at least one sixth target node is that the nodes can be coupled to form a capacitance. Thus, at least one target node pair may be determined by combining at least one fifth target node with at least one sixth target node based on the association between the at least one fifth target node and the at least one sixth target node. The graph overlapping rate between the node pairs may be obtained by adding the graph overlapping rate of the first target node and the fifth target node to the graph overlapping rate of the second target node and the sixth target node, or may be obtained by taking the maximum value of the graph overlapping rates between each node in the target first node pair and each node in the target node pair as the graph overlapping rate between the node pairs. The graphics overlapping rate between the calculated points is the same as that described above, and will not be described again. And determining a target second node pair matched with the target first node pair in at least one target pair according to the graph overlapping rate, wherein the preset threshold can be adopted, and when the graph overlapping rate is greater than or equal to the preset threshold, the positions of the two node pairs are relatively similar, and the matching is successful.
In one embodiment, step S30 includes:
outputting an interface according to a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair;
the interface comprises a plurality of comparison results, and each comparison result comprises a name of a first capacitor, a name of a target first node pair corresponding to the first capacitor, a value of a second capacitor corresponding to the first capacitor and an error between the value of the first capacitor and the value of the corresponding second capacitor.
As shown in fig. 4, in the interface, the content displayed in column 1 is the name of the first capacitor, the content displayed in column 2 is the name of the first destination node in one of the target first node pairs corresponding to the first capacitor, the content displayed in column 3 is the name of the second destination node in one of the target first node pairs corresponding to the first capacitor, the content displayed in column 4 is the value of the first capacitor, the content displayed in column 5 is the value of the second capacitor corresponding to the first capacitor, the content displayed in column 6 is the error between the value of the first capacitor and the value of the corresponding second capacitor, and column 7 is the capacitor display control column.
Optionally, the plurality of comparison results in the interface are displayed in a sorted order of magnitude of error between the value of the first capacitance and the value of the corresponding second capacitance. Wherein the error between the value of the first capacitance and the value of the corresponding second capacitance = (value of the first capacitance-value of the corresponding second capacitance)/value of the first capacitance is 100%.
In addition, a user can judge whether the precision of the capacitor solving based on one algorithm meets the requirement through the error value, if the precision meets the requirement, the algorithm does not need to be optimized, and if the precision does not meet the requirement, the algorithm can be optimized through the modes of modifying a capacitor lookup table (captable), adjusting algorithm parameters and the like, so that the precision of the capacitor solving by the algorithm is improved. Aiming at the abnormal capacitance without the comparison result, prompt information that the abnormal capacitance cannot be identified is displayed on an interface, so that a user can find the reason of unsuccessful comparison to optimize a model matching algorithm.
In an embodiment, after step S30, the method provided by the present application further includes:
and responding to the selection operation of the target comparison result, outputting the graph of the first node in the first node set and the graph of the second node in the second node set, and identifying the graph of the target first node pair corresponding to the target comparison result and the graph of the target second node pair matched with the target first node pair corresponding to the target comparison result.
Specifically, after outputting the capacitance comparison result interface, if the user selects one or more target comparison results, outputting the graph of the first node in the first node set and the graph of the second node in the second node set, and identifying the graph of the target first node pair corresponding to the one or more target comparison results and the graph of the target second node pair matched with the target first node pair corresponding to the one or more target comparison results in the graph.
The selection operation of the target comparison result may be performed by clicking on the capacitive display control column in fig. 4, to determine the target comparison result. As shown in fig. 5, in response to a result of comparing an item label selected by a user, according to the graphic boundary coordinates of a first node in a first node set and the graphic boundary coordinates of a second node in a second node set, the graphic of the first node set and the graphic of the second node set are displayed on an interface, wherein, according to the graphic boundary coordinates of the first node set, the graphic of a target first node pair corresponding to the result of comparing the item label is 2 graphics of a larger frame in fig. 5, and according to the graphic boundary coordinates of the second node set, the graphic of a target second node pair matching the target first node pair is 2 graphics of a smaller frame in fig. 5, so that an anti-label effect is formed between the graphic of one target first node pair and the graphic of one target second node pair, thereby facilitating visual comparison by the user. In practical applications, the graphics of the target first node pair and the graphics of one target second node pair may be displayed and distinguished by different colors. The user can verify the correctness of node matching and capacitance comparison by observing the information such as the size, the position and the like of the graph, find out the wrong comparison result in time, and optimize one algorithm by modifying the capacitance lookup table (captable), algorithm parameters and the like so as to improve the accuracy of solving the capacitance.
The method of the present application will be specifically described with reference to fig. 6. First, the run-field solver obtains the corresponding graph and capacitance, whose graph information can be converted into two-dimensional graph information based on the manner shown in fig. 3, and the run-model match solver obtains its graph and capacitance. Then, comparing the capacitance solved by the field with the capacitance solved by the model matching by a graph matching method, specifically, the graph matching method performs matching between nodes based on the graph information (the graph information of the second node) solved by the field and the graph information (the graph information of the first node) matched by the model, determines matched nodes according to the graph overlapping rate, acquires the capacitance between the corresponding nodes according to the matching result to perform comparison, obtains a comparison result of the capacitance, and can calculate the error of two capacitances in each comparison result, and the output of node matching and capacitance comparison is described in reference to the steps S20-S40 and is not repeated. And then, generating a capacitance graph control table (a comparison result output interface) according to the comparison result, sequencing the capacitance with the comparison result in the capacitance graph control table according to the capacitance error from high to low so as to facilitate quick searching by a user, if the user judges that the error meets the accuracy requirement, indicating that the accuracy of the model matching and solving the capacitance meets the accuracy requirement, ending the comparison process, and if the user judges that the error does not meet the accuracy requirement, adjusting a method for solving the capacitance by the model matching, re-solving the corresponding graph and the capacitance, and repeating the comparison process. In addition, in the capacitance graph control table, the comparison result can be selected, and the graph of the corresponding node is highlighted in the interface, so that the user can conveniently conduct visual comparison.
According to the method for comparing the capacitance results solved by different algorithms, first capacitance extraction information and second capacitance extraction information which are obtained by extracting parasitic capacitance from a target circuit layout by different algorithms are obtained, wherein the first capacitance extraction information comprises graphic information of a first node and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of a second node and second capacitances among different second nodes; determining at least one target second node pair matched with the at least one target first node pair according to the graphic information; acquiring a first capacitor of at least one target first node pair and a second capacitor of at least one target second node pair; and outputting a comparison result of the capacitors. According to the scheme provided by the application, the nodes determined based on different algorithms are matched based on the node graph information, so that the comparison result of the capacitors solved by the different algorithms is determined, and the comparison efficiency of the capacitors solved by the different algorithms can be improved.
Fig. 7 is a schematic structural diagram of an electronic device according to a second embodiment of the present application. The electronic device of the present application includes: a processor 110, a memory 111 and a computer program 112 stored in the memory 111 and executable on the processor 110. The steps of the method embodiments described above are implemented by the processor 110 when executing the computer program 112.
Electronic devices may include, but are not limited to, processor 110, memory 111. It will be appreciated by those skilled in the art that fig. 7 is merely an example of an electronic device and is not meant to be limiting, and that more or fewer components than shown may be included, or that certain components may be combined, or that different components may be included, for example, an electronic device may also include an input-output device, a network access device, a bus, etc.
The processor 110 may be a central processing unit (CentralProcessingUnit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-ProgrammableGateArray, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 111 may be an internal storage unit of the electronic device, such as a hard disk or a memory of the electronic device. The memory 111 may also be an external storage device of the electronic device, such as a plug-in hard disk provided on the electronic device, a smart memory card (SmartMediaCard, SMC), a security word (SecureDigital, SD) card, a flash memory card (FlashCard), or the like. Further, the memory 111 may also include both an internal storage unit and an external storage device of the electronic device. The memory 111 is used to store computer programs and other programs and data required by the electronic device. The memory 111 may also be used to temporarily store data that has been output or is to be output.
The application also provides a computer storage medium, on which a computer program is stored which, when being executed by a processor, implements the steps of the above-described method embodiments.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (11)
1. A method of comparing capacitive results of different algorithmic solutions, the method comprising:
Acquiring first capacitance extraction information and second capacitance extraction information, wherein the first capacitance extraction information and the second capacitance extraction information are obtained by extracting parasitic capacitance from a target circuit layout by adopting different algorithms, the first capacitance extraction information comprises graphic information of a first node in a first node set and first capacitances among different first nodes, and the second capacitance extraction information comprises graphic information of a second node in a second node set and second capacitances among different second nodes;
determining at least one target second node pair in the second node set matched with at least one target first node pair in the first node set according to the graphic information of the first node set and the graphic information of the second node set;
acquiring a first capacitor of the at least one target first node pair and a second capacitor of the at least one target second node pair;
and outputting a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair.
2. The method of claim 1, wherein the step of determining at least one target second node pair in the second node set that matches at least one target first node pair in the first node set based on the graphical information of the first node set and the graphical information of the second node set comprises:
Determining, in response to a node selection operation, the at least one target first node pair among the first node set, one target first node pair including a first target node and a second target node;
determining a third target node matched with the first target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set, determining a fourth target node matched with the second target node in the second node set according to the graphic information of the first node set and the graphic information of the second node set, and forming a target second node pair by the third target node and the fourth target node.
3. The method of claim 2, wherein the step of determining a third target node in the second node set that matches the first target node based on the graphical information of the first node set and the graphical information of the second node set comprises:
determining the graphic information of the first target node according to the graphic information of the first node set;
determining at least one target node to be matched with the first target node in the second node set according to the network position of the first target node in the target circuit layout;
According to the graphic information of the second node set, the graphic information of at least one target node to be matched with the first target node is obtained;
determining a first graph overlapping rate according to the graph information of the first target node and the graph information of at least one target node to be matched with the first target node;
and determining a third target node matched with the first target node in the at least one target node to be matched with the first target node according to the first graph overlapping rate.
4. The method of claim 3, wherein the step of determining a fourth target node in the second node set that matches the second target node based on the graphical information of the first node set and the graphical information of the second node set comprises:
determining the graphic information of the second target node according to the graphic information of the first node set;
determining at least one target node to be matched with the second target node in the second node set according to the network position of the second target node in the target circuit layout;
according to the graphic information of the second node set, the graphic information of at least one target node to be matched with the second target node is obtained;
Determining a second graph overlapping rate according to the graph information of the second target node and the graph information of at least one target node to be matched with the second target node;
and determining a fourth target node matched with the second target node in the at least one target node to be matched with the second target node according to the second graph overlapping rate.
5. The method of claim 4, wherein the network location includes a layer in which a node is located in the target circuit layout and a circuit network in which the node is located;
the step of determining at least one target node in the second node set to be matched with the first target node according to the network position of the first target node in the target circuit layout includes:
determining at least one node in the second node set, which is in the same layer as the first target node and in the same circuit network as the first target node, as at least one target node to be matched with the first target node;
the step of determining at least one target node to be matched with the second target node in the second node set according to the network position of the second target node in the target circuit layout includes:
And determining at least one node in the second node set, which is in the same layer as the second target node and in the same circuit network as the second target node, as at least one target node to be matched with the second target node.
6. The method of claim 1, wherein the step of determining at least one target second node pair in the second node set that matches at least one target first node pair in the first node set based on the graphical information of the first node set and the graphical information of the second node set comprises:
determining, in response to a node selection operation, the at least one target first node pair among the first node set, one target first node pair including a first target node and a second target node;
determining at least one target node pair to be matched with the target first node pair in the second node set according to the network positions of the first target node and the second target node in the target circuit layout;
calculating the graph overlapping rate between the target first node pair and each target node pair according to the graph information of the target first node pair and the graph information of the at least one target node pair;
And determining a target second node pair matched with the target first node pair in the at least one target node pair according to the graph overlapping rate.
7. The method according to any one of claims 1 to 6, wherein one of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information converted from three-dimensional graphic information obtained by calculation by a first algorithm; the other of the graphic information of the first node set and the graphic information of the second node set is two-dimensional graphic information calculated by a second algorithm.
8. The method of claim 1, wherein the step of outputting a comparison of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair comprises:
outputting an interface according to a comparison result of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair;
the interface comprises a plurality of comparison results, and each comparison result comprises a name of the first capacitor, a name of one target first node pair corresponding to the first capacitor, a value of a second capacitor corresponding to the first capacitor and an error between the value of the first capacitor and the value of the corresponding second capacitor.
9. The method of claim 8, wherein after the step of outputting a comparison of the first capacitance of the at least one target first node pair and the second capacitance of the at least one target second node pair, the method further comprises:
and responding to the selection operation of the target comparison result, outputting the graph of the first node in the first node set and the graph of the second node in the second node set, and identifying the graph of the target first node pair corresponding to the target comparison result and the graph of the target second node pair matched with the target first node pair corresponding to the target comparison result.
10. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1 to 9 when the computer program is executed.
11. A computer storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 9.
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