CN1157790C - Chip stack package structure - Google Patents
Chip stack package structure Download PDFInfo
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- CN1157790C CN1157790C CNB001333712A CN00133371A CN1157790C CN 1157790 C CN1157790 C CN 1157790C CN B001333712 A CNB001333712 A CN B001333712A CN 00133371 A CN00133371 A CN 00133371A CN 1157790 C CN1157790 C CN 1157790C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a chip stacking package structure which comprises a basal plate, a plurality of chips, a plurality of cushion blocks, a plurality of sticking layers, a plurality of welding wires, a package colloid and a plurality of tin balls, wherein the basal plate is provided with an upper surface and a back surface corresponding to the upper surface; circumferences of the chips at least comprise a plurality of welding cushions which have similar size; the chips are stacked on the upper surface of the basal plate in layers; the cushion blocks are arranged among the chips; the welding cushions of each chip can be respectively and electrically connected with the basal plate by the welding wires. The cushion blocks, the chips and the basal plate are mutually bonded by the sticking layers. The package colloid is covered on the upper surface of the basal plate, the cushion blocks, the chips and the sticking layers. The back surface of the basal plate is embedded with the tin balls. The basal plate and the tin balls can be used as carrier tools, and can be changed to conducting wire frames with connected pins.
Description
Technical field
The present invention relates to a kind of chip stack package structure, and particularly relate to a kind of ball grid array kenel encapsulating structure that semiconductor chip piles up that is applied to.
Background technology
In the world of information explosion now, integrated circuit has inseparable relation with daily life, no matter lives row still aspect the amusement at the food clothing, and all regular meeting uses the product that integrated circuit component is formed.Along with the continuous evolution of electronics technology, more humane, functional more complicated electronic product is constantly weeded out the old and bring forth the new, yet various product is invariably towards light, thin, short, little trend design, so that more convenient comfortable use to be provided.
On semiconductor technology, marched toward the volume production epoch of 0.18 micron integrated circuit, actively the semiconductor product of Du Genggao is easy to get.And integrated circuit (Integrated Circuits, generation IC) mainly are divided into three phases: the encapsulation (Package) of the manufacturing of silicon, the making of integrated circuit and integrated circuit etc.With regard to the encapsulation of integrated circuit, this promptly is a final step of finishing the integrated circuit finished product.The purpose of encapsulation be to provide chip (Die) and printed circuit board (PCB) (Printed Circuit Board, PCB) or media that is electrically connected between other suitable elements and protection chip.
Please refer to Fig. 1, its illustrate is the profile of existing chip stack package structure.
(Ball Grid Array, the BGA) mode of encapsulating structure stacked chips commonly used is such as piling up identical memory (Memory), with the capacity of the capable increase of Jing memory for the ball grid array of general chip-stacked (Stacked-die).As shown in Figure 1, dispose first chip, 106, the second chips 108 on the substrate 102 and be disposed on first chip 106, and be to fix joint between substrate 102, first chip 106 and second chip 108 with an adhesion coating 104 in the mode of piling up.Then implement the step of wire-bonded (WireBond) respectively, first chip 106 is electrically connected to substrate 102 with bonding wire 110a and with second chip 108 with bonding wire 110b.Again via the step of sealing (Encapsulate), with packing colloid 114 (MoldCompound) covered substrate 102, first chip 106, second chip 108 and bonding wire 110a, 110b.Add that at last tin ball 112 (Solid Ball) promptly finishes the ball grid array package structure that entire chip is piled up.
Yet, first chip, 106 sizes of this structure need much larger than second chip 108, monolateral big or small gap needs greater than 0.15mm, otherwise because the sizableness of first chip 106 and second chip 108 is approaching or identical, or monolateral gap is less than 0.15mm, can cause to implement the operation of wire-bonded, or second chip 108 can touch bonding wire 110a.
Please refer to Fig. 2, its illustrate is the profile of existing chip rotation back stack package structure.
As shown in Figure 2, US5,721,452 disclose above a substrate 802, dispose first chip 806.And second chip 808 revolved turn 90 degrees, be disposed at first chip, 806 tops.Respectively have several weld pads 822 first chip 806 and second chip 808 bilateral.Owing to during to the wire-bonding step of substrate 802, have the worry of bursting apart, so need add back-up block 840 between the substrate 802 and second chip 808 at the weld pad 822 that carries out second chip 808.Though have the structural capacity that can pile up the identical chips size, only for the bilateral chip that weld pad is arranged, and four limits have the chip of weld pad to adapt to.
Please refer to Fig. 3, its illustrate is the profile of the stacked structure of carrier for having now with the lead frame.
As shown in Figure 3, US5,291,061 to disclose one be the stacked structure of carrier (Carrier) with lead frame (Lead Frame).First chip 906 and second chip 908 have close size.At first, first chip configuration on lead frame 902, is electrically connected first chip 906 respectively to lead frame 902 with bonding wire 910a.Above first chip 906, dispose a glue-line (Polyimide Tape) 930, again second chip 908 is stacked on first chip, 906 tops.Bonding wire 910b is electrically connected the weld pad of second chip 908 respectively to lead frame 902.At last again with packing colloid 914 with first chip 906, second chip 908, bonding wire 910a, 910b and lead frame 902 encapsulated mouldings, only expose the pin 932 of lead frame 902.Its mesoglea 930 is the cost height not only, and poor radiation, and second chip, 908 heat radiations that are stacked on the top are difficult for.And need to use special installation to carry out high-temperature operation more than 400 ℃, and cause the raising of manufacturing cost with the glue-line 930 between pressing first chip 906, second chip 908.In addition, glue-line 930 can cause cushion (Cushion) effect at second chip 908, influences the reliability and the quality of second chip, 908 wire-bonded.
Summary of the invention
Therefore, a purpose of the present invention is promptly providing a kind of for the close chip stack package structure of size.
Another object of the present invention is providing a kind of close for size, and the chip stack package structure of weld pad can be set around the tool.
A further object of the present invention is providing a kind of close for size, and around the tool chip of weld pad can be set, and the stack package structure of bonding wire cushion effect can not take place.
Another purpose of the present invention is providing a kind of tool can promote the chip stack package structure of integral heat sink effect.
A still purpose of the present invention is providing a kind of chip stack package structure that does not need can reduce with special installation material cost and manufacturing cost.
According to above-mentioned purpose of the present invention, a kind of chip stack package structure is proposed, comprise at least: a substrate, several chips, several cushion blocks, several adhesion coatings, several bonding wires, a packing colloid and several tin balls.Wherein substrate has a upper surface and with respect to the back side of upper surface.At least comprise several weld pads around the chip, and have close size.Several chips are stacked in layer by layer on the upper surface of substrate, and between chip, dispose several cushion blocks, be electrically connected the weld pad of each chip respectively to substrate with bonding wire.And be to be bonded with each other with several adhesion coatings between cushion block, chip and substrate.And cover packing colloid in upper surface, cushion block, the chip of substrate and comprise adhesion coating.Implant the tin ball in the back side of substrate at last, can have the function of input and output.
According to the preferred embodiments of the present invention, elargol or non-conductive glue that chip stack package structure of the present invention uses traditional handicraft to use are adhesion coating, temperature must be increased to more than 400 ℃, in the time of can simplifying processing procedure and avoid with high temperature pressing chip, cause chip rupture.When using ultrasonic waves to carry out the wire-bonding step of bonding wire, can avoid because chip rigidity deficiency produces the cushion effect, and then improve the finished product rate.Cushion block can be full slice system or column formula, and its material has good heat radiating, and thermal coefficient of expansion is also close with chip, can not produce the problem of thermal stress.By the heat-delivery surface of the fin that exposes cushion block to the open air or installed additional, more can produce better heat radiating effect.
Description of drawings
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 illustrate is the profile of existing chip stack package structure.
Fig. 2 illustrate is the profile of existing chip rotation back stack package structure.
Fig. 3 illustrate is the profile of the stacked structure of carrier for having now with the lead frame.
Fig. 4 A and Fig. 4 B illustrate plane graph and the profile according to chip stack package structure first preferred embodiment of the present invention.
Fig. 5 A and Fig. 5 B illustrate plane graph and the profile according to chip stack package structure second preferred embodiment of the present invention.
Fig. 6 illustrates the profile according to chip stack package structure the 3rd preferred embodiment of the present invention.
Fig. 7 illustrates the profile according to chip stack package structure the 4th preferred embodiment of the present invention.
Fig. 8 illustrates the profile according to chip stack package structure the 5th preferred embodiment of the present invention.
Fig. 9 illustrates the profile according to chip stack package structure the 6th preferred embodiment of the present invention.
The sign explanation of accompanying drawing:
201,301,401,501,601,701: upper surface
102,202,302,402,502,602,702,802: substrate
203,303,403,503,603,703: the back side
104,204,304,404,504,604,704: adhesion coating
106,206,306,406,506,606,706,806,906: the first chips
108,208,308,408,508,608,708,808,908: the second chips
110a, 110b, 210a, 210b, 310a, 310b, 310c, 410a, 410b, 510a, 510b, 610a, 610b, 710a, 710b, 810,910a, 910b: bonding wire
112,212,312,412,512,612,712: the tin ball
114,214,314,414,514,614,714,914: packing colloid
309: the three chips
220,320a, 320b, 420a, 420b, 520a, 520b, 620,720: cushion block
222,322,622,722,822: weld pad
430,530: heat-delivery surface
532: fin
840: back-up block
930: glue-line
702,902: lead frame
932,712: pin
Embodiment
Embodiment
Please refer to Fig. 4 A and Fig. 4 B, its illustrate is according to the plane graph and the profile of chip stack package structure first preferred embodiment of the present invention.Wherein Fig. 4 B is the 4B-4B profile of Fig. 4 A.
Shown in Fig. 4 A and Fig. 4 B, substrate 202 has the back side 203 that a upper surface 201 reaches with respect to upper surface 201.At least comprise several weld pads 222 around first chip 206 and second chip 208.And first chip 206 and second chip 208 have close size.At first, first chip 206 is disposed on the upper surface 201 of substrate 202, is electrically connected the weld pad 222 of first chip 206 respectively to substrate 202 with bonding wire 210a.Above first chip 206, configuration cushion block 220 is stacked on second chip 208 first chip 206 and cushion block 220 tops again.Bonding wire 210b is electrically connected the weld pad 222 of second chip 208 respectively to substrate 202.
Wherein cushion block (Spacer) is column (Column) formula, and purpose is in order to reduce employed material cost, also can to reach the function of high second chip 208 of frame.And between cushion block 220, first chip 206, second chip 208 and substrate 202, be to be bonded with each other with several adhesion coatings 204.The material of adhesion coating 204 wherein such as being elargol or the heat conduction non-conducting glue that traditional handicraft is used, must not be increased to temperature more than 400 ℃, can simplify processing procedure, and when avoiding engaging with high temperature, causes first chip 206 or second chip 208 to break.And, when using ultrasonic waves to carry out the wire-bonding step of bonding wire 210a, 210b, can avoid because second chip, 208 rigidity deficiencies produce the cushion effect, and then improve the finished product rate.
Then cover a packing colloid 214 in upper surface 201, cushion block 220, first chip 206, second chip 208 of substrate 202 and comprise adhesion coating 204.The material of packing colloid 214 wherein is such as being insulation material such as epoxy resin (Epoxy).Implant tin ball 212 in the back side 203 of substrate 202 at last, can have the function of input and output (Input/Output).Wherein the material of cushion block 220 is such as being silicon, blank chip (Dummy Chip) or other metal materials with good heat radiating, thermal coefficient of expansion is also identical or very approaching with second chip 208 with first chip 206, therefore can not produce the problem of thermal stress.Wherein substrate 201 and tin ball 212 are carrier, also variable lead frame of more having a pin.
Please refer to Fig. 5 A and Fig. 5 B, its illustrate is according to the plane graph and the profile of chip stack package structure second preferred embodiment of the present invention.Wherein Fig. 5 B is the 5B-5B profile of Fig. 5 A.
Shown in Fig. 5 A and Fig. 5 B, substrate 302 has the back side 303 that a upper surface 301 reaches with respect to upper surface 301.At least comprise several weld pads 322 around first chip 306, second chip 308 and the 3rd chip 309.And first chip 306, second chip 308 and the 3rd chip 309 have close size.At first, first chip 306 is disposed on the upper surface 301 of substrate 302, is electrically connected the weld pad 322 of first chip 306 respectively to substrate 302 with bonding wire 310a.Above first chip 306, configuration cushion block 320a is stacked on second chip 308 first chip 306 and cushion block 320a top again.Be electrically connected the weld pad 322 of second chip 308 respectively to substrate 302 with bonding wire 310b.Above second chip 308, configuration cushion block 320b is stacked on the 3rd chip 309 first chip 306, second chip 308 and cushion block 320b top again.Be electrically connected the weld pad 322 of the 3rd chip 309 respectively to substrate 302 with bonding wire 310c.Wherein cushion block 320a, 320b can be the column formula or are full slice system.And between cushion block 320a, 320b, first chip 306, second chip 308, the 3rd chip 309 and substrate 302, be to be bonded with each other with several adhesion coatings 304.Then cover a packing colloid 314 in upper surface 301, cushion block 302a, 302b, first chip 306, second chip 308, the 3rd chip 309 of substrate 302 and comprise adhesion coating 304.Implant tin ball 312 in the back side 303 of substrate 302 at last.
In the second above-mentioned preferred embodiment, piled up first chip 306, second chip 308 and the 3rd chip 309, so the present invention's permission at least two chips, also comprise several chip stacked in multi-layers.Wherein substrate 301 and tin ball 312 are carrier, the also variable lead frame that more has pin.
Please refer to Fig. 6, its illustrate is according to the profile of chip stack package structure the 3rd preferred embodiment of the present invention.
As shown in Figure 6, substrate 402 has the back side 403 that a upper surface 401 reaches with respect to upper surface 401.At least comprise several weld pads around first chip 406 and second chip 408.And first chip 406 and second chip 408 have close size.At first, first chip 406 is disposed on the upper surface 401 of substrate 402, the weld pad that is electrically connected first chip 406 with bonding wire 410a respectively is to substrate 402.Above first chip 406, configuration cushion block 420a is stacked on second chip 408 first chip 406 and cushion block 420a top again, and the weld pad that is electrically connected second chip 408 with bonding wire 410b respectively is to substrate 402.Above second chip 408, configuration cushion block 420b.Cushion block 420b comprises a heat-delivery surface 430 at least.And between cushion block 420a, 420b, first chip 406, second chip 408 and substrate 402, be to be bonded with each other with several adhesion coatings 404.
Then cover a packing colloid 414 in upper surface 401, cushion block 420a, 420b, first chip 406, second chip 408 of substrate 402 and comprise adhesion coating 404, but expose the heat-delivery surface 430 of cushion block 420b.Implant tin ball 412 in the back side 403 of substrate 402 at last.And, can produce better heat radiating effect by the heat-delivery surface 430 that exposes cushion block 420b to the open air.Wherein substrate 401 and tin ball 412 are carrier, also variable lead frame of more having a pin.
Please refer to Fig. 7, its illustrate is according to the profile of chip stack package structure the 4th preferred embodiment of the present invention.
As shown in Figure 7, substrate 502 has the back side 503 that a upper surface 501 reaches with respect to upper surface 501.At least comprise several weld pads around first chip 506 and second chip 508.And first chip 506 and second chip 508 have close size.At first, first chip 506 is disposed on the upper surface 501 of substrate 502, the weld pad that is electrically connected first chip 506 with bonding wire 510a respectively is to substrate 502.Above first chip 506, configuration cushion block 520a is stacked on second chip 508 first chip 506 and cushion block 520a top again, and the weld pad that is electrically connected second chip 508 with bonding wire 510b respectively is to substrate 502.Above second chip 508, configuration cushion block 520b.And fin 532 is stacked on the cushion block 520b.Wherein fin 532 has the good material of thermal conductivity, comprises a heat-delivery surface 530 at least.And between cushion block 520a, 520b, first chip 506, second chip 508, fin 532 and substrate 502, be to be bonded with each other with several adhesion coatings 504.
Then cover a packing colloid 514 in upper surface 501, cushion block 520, first chip 506, second chip 508, the fin 532 of substrate 502 and comprise adhesion coating 504, but expose the heat-delivery surface 530 of fin 532.Implant tin ball 512 in the back side 503 of substrate 502 at last.And, can produce better heat radiating effect by the heat-delivery surface 530 that exposes fin 532 to the open air.Wherein substrate 501 and tin ball 512 are carrier, also variable lead frame of more having a pin.
Please refer to Fig. 8, its illustrate is according to the profile of chip stack package structure the 5th preferred embodiment of the present invention.
As shown in Figure 8, substrate 602 has the back side 603 that a upper surface 601 reaches with respect to upper surface 601.At least comprise several weld pads 622 around first chip 606 and second chip 608.Different is that first chip 606 can be slightly larger than second chip 608, must be below 0.3mm but differ.At first, first chip 606 is disposed on the upper surface 601 of substrate 602, is electrically connected the weld pad 622 of first chip 606 respectively to substrate 602 with bonding wire 610a.Above first chip 606, configuration cushion block 620 is stacked on second chip 608 first chip 606 and cushion block 620a top again, and bonding wire 610b is electrically connected the weld pad 622 of second chip 608 respectively to substrate 602.And between cushion block 620, first chip 606, second chip 608 and substrate 602, be to be bonded with each other with several adhesion coatings 604.Then cover a packing colloid 614 in upper surface 601, cushion block 620, first chip 606, second chip 608 of substrate 602 and comprise adhesion coating 604.Implant tin ball 612 in the back side 603 of substrate 602 at last.It is noted that the edge of second chip 608 is aligned in the weld pad 622 of first chip 606 approximately.Wherein substrate 601 and tin ball 612 are carrier, also variable lead frame of more having a pin.
Please refer to Fig. 9, its illustrate is according to the profile of chip stack package structure the 6th preferred embodiment of the present invention.
As shown in Figure 9, lead frame (Lead Frame) 702 has a upper surface 701 and several pins 712.At least comprise several weld pads 722 around first chip 706 and second chip 708.Different is that first chip 706 can be slightly larger than second chip 708, at first, first chip 706 is disposed on the upper surface 701 of lead frame 702, is electrically connected the weld pad 722 of first chip 706 respectively to lead frame 702 with bonding wire 710a.Above first chip 706, configuration cushion block 720 is stacked on second chip 708 first chip 706 and cushion block 720a top again.Bonding wire 710b is electrically connected the weld pad 722 of second chip 708 respectively to lead frame 702.And between cushion block 720, first chip 706, second chip 708 and lead frame 702, be to be bonded with each other with several adhesion coatings 704.Then cover a packing colloid 714 coated wire framves 702, cushion block 720, first chip 706, second chip 708 and comprise adhesion coating 704.It is noted that the edge of first chip 706 is aligned in the weld pad 722 of second chip 708 approximately.Wherein base carriage 702 and pin 712 are carrier, also variable substrate of more having a tin ball.
In sum, the present invention has following advantage at least:
1. elargol or the non-conductive glue that uses traditional handicraft to use is adhesion coating, temperature must be increased to more than 400 ℃, in the time of can simplifying processing procedure and avoid with high temperature pressing chip, causes chip rupture.
2. elargol or the heat conduction non-conducting glue that uses traditional handicraft to use is adhesion coating, when using ultrasonic waves to carry out the wire-bonding step of bonding wire, can avoid because chip rigidity deficiency produces the cushion effect, and then improve the finished product rate.
3. cushion block can be full slice system or column formula, and utilizes the high chip of cushion block frame, but the chip of the close size of stacked in multi-layers.
4. the material of cushion block own has good heat radiating, and thermal coefficient of expansion is identical with chip, can not produce the problem of thermal stress.By the heat-delivery surface of the fin that exposes cushion block to the open air or installed additional, more can produce better heat radiating effect.
Though the present invention discloses as above in conjunction with a preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.
Claims (28)
1. chip stack package structure comprises at least:
One carrier has a upper surface and with respect to the back side of this upper surface;
At least distinctly comprise a plurality of weld pads around a plurality of chips, each those chip, and those chips are stacked in layer by layer on this upper surface of this carrier;
A plurality of cushion blocks are disposed between every adjacent two those chips;
A plurality of adhesion coatings are disposed between those cushion blocks, those chips and this carrier;
Many bonding wires, those weld pads that are electrically connected those chips are to this carrier; And
One packing colloid covers this upper surface, those cushion blocks, those chips and those adhesion coatings of this carrier,
Wherein, those die size are close, and wherein any two those die size differ below the 0.3mm.
2. chip stack package structure as claimed in claim 1, wherein this cushion block is the column formula.
3. chip stack package structure comprises at least:
One carrier has a upper surface and with respect to the back side of this upper surface;
Comprise a plurality of weld pads around a plurality of chips, each those chip, and those chips are stacked in layer by layer on this upper surface of this carrier;
A plurality of cushion blocks are disposed at the top of those chips, and one of them comprises a heat-delivery surface at least;
A plurality of adhesion coatings are disposed between those cushion blocks, those chips and this carrier;
Many bonding wires, those weld pads that are electrically connected those chips are to this carrier; And
One packing colloid covers this upper surface, those cushion blocks, those chips and those adhesion coatings of this carrier, and exposes this heat-delivery surface of one of those cushion blocks.
4. chip stack package structure as claimed in claim 3, wherein this carrier is a substrate, and also includes a plurality of tin balls at this back side of this substrate.
5. chip stack package structure as claimed in claim 3, wherein this carrier is a lead frame, and this lead frame also includes a plurality of pins.
6. chip stack package structure as claimed in claim 3, wherein those die size equate.
7. chip stack package structure as claimed in claim 3, wherein those die size are close, and wherein any two those die size differ below the 0.3mm.
8. chip stack package structure as claimed in claim 3, wherein the material of this cushion block is a silicon.
9. chip stack package structure as claimed in claim 3, wherein the material of this cushion block is a blank chip.
10. chip stack package structure as claimed in claim 3, wherein the material of this cushion block is a metal, and this cushion block thermal coefficient of expansion is near those chips.
11. chip stack package structure as claimed in claim 3, wherein this cushion block is a full slice system.
12. chip stack package structure as claimed in claim 3, wherein this cushion block is the column formula.
13. chip stack package structure as claimed in claim 3, wherein the material of this adhesion coating is an elargol.
14. chip stack package structure as claimed in claim 3, wherein the material of this adhesion coating is a heat conduction non-conducting glue.
15. chip stack package structure as claimed in claim 3, wherein the material of this packing colloid is an epoxy resin.
16. a chip stack package structure comprises at least:
One carrier has a upper surface and with respect to the back side of this upper surface;
Comprise a plurality of weld pads around a plurality of chips, each those chip, and those chips are stacked in layer by layer on this upper surface of this substrate;
One fin comprises a heat-delivery surface at least, and this fin piles up on those chips;
A plurality of cushion blocks are disposed between every adjacent two those chips and between those chips and this fin;
A plurality of adhesion coatings are disposed between those cushion blocks, those chips, this fin and this carrier;
Many bonding wires, those weld pads that are electrically connected those chips are to this carrier; And
One packing colloid covers this upper surface, those cushion blocks, those chips and those adhesion coatings of this carrier, but exposes this heat-delivery surface of this fin.
17. chip stack package structure as claimed in claim 16, wherein this carrier is a substrate, and also includes a plurality of tin balls at this back side of this substrate.
18. chip stack package structure as claimed in claim 16, wherein this carrier is a lead frame, and this lead frame also includes a plurality of pins.
19. chip stack package structure as claimed in claim 16, wherein those die size equate.
20. chip stack package structure as claimed in claim 16, wherein those die size are close, and wherein any two those die size differ below the 0.3mm.
21. chip stack package structure as claimed in claim 16, wherein the material of this cushion block is a silicon.
22. chip stack package structure as claimed in claim 16, wherein the material of this cushion block is a blank chip.
23. chip stack package structure as claimed in claim 16, wherein the material of this cushion block is a metal, and this cushion block thermal coefficient of expansion is near those chips.
24. chip stack package structure as claimed in claim 16, wherein this cushion block is a full slice system.
25. chip stack package structure as claimed in claim 16, wherein this cushion block is the column formula.
26. chip stack package structure as claimed in claim 16, wherein the material of this adhesion coating is an elargol.
27. chip stack package structure as claimed in claim 16, wherein the material of this adhesion coating is a heat conduction non-conducting glue.
28. chip stack package structure as claimed in claim 16, wherein the material of this packing colloid is an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001333712A CN1157790C (en) | 2000-11-27 | 2000-11-27 | Chip stack package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001333712A CN1157790C (en) | 2000-11-27 | 2000-11-27 | Chip stack package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1355568A CN1355568A (en) | 2002-06-26 |
| CN1157790C true CN1157790C (en) | 2004-07-14 |
Family
ID=4595677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001333712A Expired - Lifetime CN1157790C (en) | 2000-11-27 | 2000-11-27 | Chip stack package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1157790C (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4128473B2 (en) * | 2003-03-07 | 2008-07-30 | 松下電器産業株式会社 | Semiconductor device |
| JP4587676B2 (en) * | 2004-01-29 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | Three-dimensional semiconductor device having a stacked chip configuration |
| CN100392845C (en) * | 2004-11-12 | 2008-06-04 | 日月光半导体制造股份有限公司 | Packaging structure with high adhesivity between substrate and packing colloid |
| JP2006344824A (en) * | 2005-06-09 | 2006-12-21 | Nec Electronics Corp | Semiconductor device and method for manufacturing semiconductor device |
| CN101740552B (en) * | 2008-11-25 | 2012-05-23 | 南茂科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
| US8743561B2 (en) * | 2009-08-26 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level molded structure for package assembly |
| US8642387B2 (en) * | 2011-11-01 | 2014-02-04 | Flextronics Ap, Llc | Method of fabricating stacked packages using laser direct structuring |
| CN102509722A (en) * | 2012-01-06 | 2012-06-20 | 日月光半导体制造股份有限公司 | Semiconductor encapsulating element and manufacture method thereof |
| CN104064551B (en) * | 2014-06-05 | 2018-01-16 | 华为技术有限公司 | A kind of chip stack package structure and electronic equipment |
| CN108010898A (en) * | 2017-11-02 | 2018-05-08 | 上海玮舟微电子科技有限公司 | A kind of chip-packaging structure |
| CN108899307B (en) * | 2018-06-22 | 2020-02-21 | 西安微电子技术研究所 | Method for preparing lateral interconnection structure of integrated module of substrate stacking system |
| CN108987381B (en) * | 2018-08-14 | 2024-01-02 | 苏州德林泰精工科技有限公司 | Stacked chip packaging structure based on special-shaped resin gasket |
| CN114242669B (en) * | 2022-02-28 | 2022-07-08 | 甬矽电子(宁波)股份有限公司 | Stack packaging structure and stack packaging method |
-
2000
- 2000-11-27 CN CNB001333712A patent/CN1157790C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1355568A (en) | 2002-06-26 |
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