CN102509722A - Semiconductor encapsulating element and manufacture method thereof - Google Patents
Semiconductor encapsulating element and manufacture method thereof Download PDFInfo
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- CN102509722A CN102509722A CN201210002980XA CN201210002980A CN102509722A CN 102509722 A CN102509722 A CN 102509722A CN 201210002980X A CN201210002980X A CN 201210002980XA CN 201210002980 A CN201210002980 A CN 201210002980A CN 102509722 A CN102509722 A CN 102509722A
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- packaging body
- substrate
- depressed part
- distance
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
The invention relates to a semiconductor encapsulating element and a manufacture method of the semiconductor encapsulating element. The semiconductor encapsulating element comprises a base plate, a semiconductor chip, an encapsulating body and a plurality of welding balls, wherein the base plate is provided with a side surface, an upper surface and a lower surface, the upper surface and the lower surface are opposite, the semiconductor chip is arranged on the upper surface of the base plate, the encapsulating body covers the semiconductor chip and is provided with a recessed part and an upper surface, the recessed part is recessed relative to the side surface of the base plate and extends a distance in a direction from the upper surface of the encapsulating body to the base plate, the distance at most equals to the thickness of the encapsulating body, and the recessed part and the side surface of the base plate are formed in different cutting processed. The welding balls are formed on the lower surface of the base plate.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacturing approach thereof, and particularly relevant for a kind of semiconductor package part and manufacturing approach of accomplishing with the multiple tracks cutting technique thereof.
Background technology
Traditional semiconductor package part comprises substrate, sealing and chip, and its chips is located on the surface of substrate, and the surface of sealing covered substrate and coating chip.
Yet, because sealing is different with the material of substrate, so its thermal expansion coefficient difference is quite big.Therefore, after sealing forms, cause the amount of warpage of semiconductor package part very big, and increase follow-up difficulty of planting ball.
Summary of the invention
The present invention is relevant for a kind of semiconductor package part and manufacturing approach thereof, and the amount of warpage of semiconductor package part is little, helps to promote the manufacturing property of planting ball.
According to one embodiment of the invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, semiconductor chip, a packaging body and several soldered balls.Substrate has a side and a relative upper surface and a lower surface.Semiconductor chip is located on the upper surface of substrate.Packaging body coats semiconductor chip and have a depressed part and a upper surface; A distance is extended toward depression and the direction from the upper surface of packaging body toward substrate in the side of the relative substrate of depressed part; This distance equals the thickness of packaging body at the most, and wherein depressed part forms in different cutting techniques with the side of substrate.Soldered ball is formed on the lower surface of substrate.
A kind of manufacturing approach of semiconductor package part is proposed according to another embodiment of the present invention.Manufacturing approach may further comprise the steps.One substrate is provided, has relative a upper surface and a lower surface; The semiconductor chip is set on the upper surface of substrate; Form a packaging body coats semiconductor chip, wherein packaging body has a upper surface; In packaging body, cut out a depressed part, wherein depressed part extends a distance from the upper surface of packaging body toward the direction of substrate, and this distance is less than the thickness of packaging body; Form several soldered balls on the lower surface of substrate; And the position of corresponding depressed part forms a Cutting Road through packaging body and substrate, and to cut off packaging body and substrate, wherein the width of Cutting Road is less than the width of depressed part.
For there is better understanding above-mentioned and other aspects of the present invention, hereinafter is special lifts embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Figure 1A illustrates the outside drawing according to the semiconductor package part of one embodiment of the invention.
Figure 1B illustrates among Figure 1A the profile along direction 1B-1B '.
Fig. 2 A to 2E illustrates the process drawing of the semiconductor package part of Figure 1A.
The main element symbol description:
100: semiconductor package part
100 ': encapsulating structure
110: substrate
110b: lower surface
110s, 140s: side
110u, 140u: upper surface
111: conductive through hole
112: line layer
120: soldered ball
130: semiconductor chip
140: packaging body
141b: bottom surface
141: depressed part
141s: sidewall
142: a part
150: bonding wire
160: support plate 160
161: adhesive layer
H1, H2, H3: distance
P: Cutting Road
S1, S2: cutter
T1, T2: thickness
W1, W2: width
Embodiment
Please with reference to Figure 1A, it illustrates the outside drawing according to the semiconductor package part of one embodiment of the invention.
Please with reference to Figure 1B, it illustrates among Figure 1A the profile along direction 1B-1B '.
Shown in Figure 1B, soldered ball 120 is formed on the lower surface 110b of substrate 110, and is formed on the corresponding conductive through hole 111.
Shown in Figure 1B, semiconductor chip 130 is located on the upper surface 110u of substrate 110.In the present embodiment, semiconductor chip 130 is to be located on the substrate 110 towards upper position (face-up), and bonding wire 150 connects the line layer 112 of semiconductor chip 130 and substrate 110, makes semiconductor chip 130 be electrically connected at soldered ball 120.
Among another embodiment, though figure does not illustrate, semiconductor chip 130 is located on the substrate 110 with orientation (face-down) down, and semiconductor chip 130 comprises at least one soldered ball, and semiconductor chip 130 is connected in substrate 110 with soldered ball.Among the another embodiment, though figure do not illustrate, so several semiconductor chips 130 can stack together up and down, or the limit keep to the side (side-by-side) be disposed on the substrate 110.
Shown in Figure 1B, packaging body 140 coats semiconductor chip 130 and has depressed part 141 and upper surface 140u.The side 110s of depressed part 141 relative substrates 110 extends a distance H 1 toward sunken inside and the direction from the upper surface 140u of packaging body 140 toward substrate 110; Wherein distance H 1 makes packaging body 140 self form one less than the thickness T 1 of packaging body 140 " up-narrow and down-wide " structure.
In addition, it for example is that cutter or laser cutting form that depressed part 141 can adopt, and forms in different cutting techniques with the side 110s of substrate 110.Via the formation of depressed part 141, can discharge the thermal stress of packaging body 140, help to promote the quality and the life-span of semiconductor package part 100, and the amount of warpage that reduces semiconductor package part 100.
Shown in Figure 1B, in the present embodiment, depressed part 141 does not extend to substrate 110, and keeps the part 142 of packaging body 140.Via the part 142 of packaging body 140, can keep or promote the intensity of semiconductor package part 100.
In the present embodiment, the ratio of the thickness T 1 of distance H 1 and packaging body 140 can be between about 2/3 to 3/4, as shown in the formula (1).Thus, can make the amount of warpage of semiconductor package part 100 be controlled at preset or desired extent, and can guarantee the intensity of semiconductor package part 100 simultaneously.Right formula (1) is not in order to the restriction present embodiment.
Shown in Figure 1B, in the present embodiment, the depressed part 141 of packaging body 140 has bottom surface 141b, and bottom surface 141b, can keep the intensity of substrate 110 and make the amount of warpage of semiconductor package part 100 very little under this design load at a distance of the distance H of substrate 110 2 about 100 microns.Among another embodiment, distance H 2 also can be less than or greater than 100 microns.
Though the depressed part 141 of present embodiment does not extend to substrate 110, so among another embodiment, depressed part 141 may extend to substrate 110.Under this design, the ratio 1 of the thickness T 1 of distance H 1 and packaging body 140.So, packaging body 140 and substrate 110 common formation one " up-narrow and down-wide " structure (width of packaging body 140 is narrower, and the wider width of substrate 110).
Shown in Figure 1B, packaging body 140 has side 140s, and depressed part 141 has sidewall 141s; The side 140s of the relative packaging body 140 of sidewall 141s is toward sunken inside; Wherein, side 140s is at a distance of 3 at least 5 microns of the distance H of sidewall 141s, and so this is non-in order to the restriction present embodiment.In addition, the package body 140 and the substrate 110 side of the side surface 140s 110s Shu cutting process in the same form, the package body 140 side of the side surface 140s 110s of the substrate 110 is substantially aligned, for example, are coplanar.
In addition, packaging body 140 can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.Packaging body 140 also can comprise suitable filler, for example is the silicon dioxide of powdery.In one object lesson, packaging body 140 sealings (molding compound).
Below explanation is according to the manufacture process of the semiconductor package part of one embodiment of the invention, is the example explanation with the manufacture process of the semiconductor package part of Figure 1A.
Please with reference to Fig. 2 A to 2E, it illustrates the process drawing of the semiconductor package part of Figure 1A.
Shown in Fig. 2 A, substrate 110 is provided, wherein substrate 110 has relative upper surface 110u and lower surface 110b.
Shown in Fig. 2 A, can adopt for example is that the surface is pasted technology (Surface mount technology SMT), is provided with at least semiconductor chip 130 on the upper surface 110u of substrate 110.
Shown in Fig. 2 A, can adopt for example is the routing technology, connects the line layer 112 of semiconductor chip 130 and substrate 110 with at least one bonding wire 150.
Shown in Fig. 2 B; Can adopt for example is compression forming (compression molding), injection moulding (injection molding) or metaideophone moulding (transfer molding); Form the upper surface 110u of packaging body 140 covered substrates 110 and coat semiconductor chip 130 and bonding wire 150, wherein packaging body 140 has upper surface 140u.
Because packaging body 140 at high temperature forms, it is inner after cooled and solidified understands heat history stress, so can reduce quality and the life-span of packaging body 140 and can increase packaging body 140 and the amount of warpage of substrate 110.Yet present embodiment can discharge the stress of packaging body 140 via the formation of follow-up depressed part 141, to promote the quality and the life-span of packaging body 140, is described below.
Shown in Fig. 2 C, can adopt for example is cutter or laser cutting, in packaging body 140, cuts out at least one depressed part 141, to form encapsulating structure 100 '.Wherein, depressed part 141 extends a distance H 1 from the upper surface 140u of packaging body 140 toward the direction of substrate 110, and this distance H 1 is less than the thickness T 1 of packaging body 140, and the part 142 of reservation packaging body 140.Preferable but non-exclusively, at least 100 microns of the thickness H2 of the part 142 of packaging body 140 so can make encapsulating structure 100 ' (substrate 110 and packaging body 140) possess sufficient intensity.Among another embodiment, if the thickness of substrate 110 is enough, then the thickness H2 of the part 142 of packaging body 140 is not limited at least 100 microns, also can be less than 100 microns.Among another embodiment, the thickness H2 of the part 142 of packaging body 140 also can be greater than 100 microns.
In the present embodiment; The thickness T of the thickness T 1 of packaging body 140 about 500 microns and substrate 110 2 about 500 microns, in the case down, distance H 1 can design 400 microns of written treaties; The amount of warpage that thus, can make substrate 110 possess sufficient intensity and encapsulating structure 100 ' obviously significantly reduces.Show that according to test data omit the amount of warpage height to 2.5 millimeter of the encapsulating structure 100 ' of depressed part 141, compared to this, the amount of warpage of the encapsulating structure 100 ' of present embodiment Fig. 2 C is reduced to 0.5 millimeter.
In the method that forms depressed part 141, with the cutter cutting, can adopt the wide cutter S1 that is about 55 microns of cutter, make the width W 1 of depressed part 141 be about 55 microns.Among another embodiment, also can adopt the wide cutter between 22 to 80 microns of cutter to form depressed part 141.
Shown in Fig. 2 D, form several soldered balls 120 on the lower surface 110b of substrate 110.Via the formation of depressed part 141, make the amount of warpage of encapsulating structure 100 ' very little, so soldered ball 120 can accurately be formed on the lower surface 110b of substrate 110, for example be accurately to be positioned on the corresponding conductive through hole 111.
Shown in Fig. 2 E, can adopt for example cutter or laser, the position of corresponding depressed part 141 forms Cutting Road P through packaging body 140 and substrate 110, to cut off packaging body 140 and substrate 110.Wherein, the width W 2 of Cutting Road P is less than the width W 2 of the depressed part 141 of correspondence, Cutting Road P is formed after, depressed part 141 forms one with Cutting Road P is common " wide at the top and narrow at the bottom " Cutting Road.So far, form at least just like the semiconductor package part shown in Figure 1A 100.
After the cutting, substrate 110 formation side 110s, and packaging body 140 formation side 140s, the side 110s of substrate 110 aligns in fact with the side 140s of packaging body 140, for example is coplane.Because the width W 2 of Cutting Road P is less than the width W 1 of depressed part 141, the side 110s of depressed part 141 relative substrates 110 is toward sunken inside.
In the formation method of Cutting Road P; Cut with cutter; Can adopt cutter S2 to form Cutting Road P; Wherein the width W 2 of cutter S2 thus, can avoid cutter S2 to destroy the side 140s (side 140s forms) of the packaging body 140 that has cut in the cutting technique of depressed part 141 less than the width W 1 (Fig. 2 C) of cutter S1.Among one embodiment, the width W 2 of cutter S2 is less than 1 at least 10 micron of the width W of cutter S1, and about 55 microns with the width of cutter S1, the width W of cutter S2 2 about 45 microns.Among another embodiment, the cutter of cutter S2 is wide can be between about 30 to 60 microns.
Before Cutting Road P forms, can encapsulating structure 100 ' (Fig. 2 D) be placed on the support plate 160, wherein support plate 160 comprises adhesive layer 161, it for example is a UV glue.Substrate 110 and soldered ball 120 can stick on the adhesive layer 161, and wherein soldered ball 120 can be imbedded in the adhesive layer 161.After Cutting Road P forms, can (Ultraviolet Rays UV), makes adhesive layer 161 lose stickiness, so can separate soldered ball 120 and adhesive layer 161 easily to adhesive layer 161 irradiating ultraviolet light.
In the present embodiment, Cutting Road P can the direction from packaging body 140 toward substrate 110 form; Among another embodiment, Cutting Road P can the direction from substrate 110 toward packaging body 140 form, and in the case, can the encapsulating structure 100 ' of Fig. 2 D be inverted, and is located at up on the support plate 160 with packaging body 140, and then cuts.Perhaps, as long as cutting equipment allows, also can be under the situation of not being inverted encapsulating structure 100 ', the direction from substrate 110 toward packaging body 140 forms Cutting Road P.
Semiconductor package part that the above embodiment of the present invention disclosed and manufacturing approach thereof, the amount of warpage of semiconductor package part is little, helps to promote the manufacturing property of planting ball.In addition,, can discharge the thermal stress of packaging body, help to promote the quality and the life-span of semiconductor package part via the formation of depressed part, and the amount of warpage that reduces semiconductor package part.Moreover the direction of depressed part from the upper surface of packaging body toward substrate extended a distance, this distance less than or equal the thickness of packaging body in fact.
In sum, though the present invention discloses as above with embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. semiconductor package part comprises:
One substrate has a side and a relative upper surface and a lower surface;
The semiconductor chip is located on this upper surface of this substrate;
One packaging body; Coat this semiconductor chip and have a depressed part and a upper surface; This depressed part relatively this side of this substrate extends a distance toward sunken inside and from this upper surface of this packaging body toward the direction of this substrate; This distance equals the thickness of this packaging body at the most, and this depressed part forms in different cutting techniques with this side of this substrate; And
Several soldered balls are formed on this lower surface of this substrate.
2. semiconductor package part as claimed in claim 1, wherein should distance and the ratio of the thickness of this packaging body between 2/3 to 3/4.
3. semiconductor package part as claimed in claim 2, wherein this depressed part has a bottom surface, and this bottom surface is at a distance of 100 microns of the distances of this substrate.
4. semiconductor package part as claimed in claim 1, wherein this packaging body has a side, and this depressed part has a sidewall, and relatively this side of this packaging body is toward sunken inside for this sidewall, and wherein this side of this packaging body is at a distance of at least 5 microns of the distances of this sidewall.
5. semiconductor package part as claimed in claim 1, wherein this packaging body has a side, and align in fact with this side of this packaging body in this side of this substrate.
6. the manufacturing approach of a semiconductor package part comprises:
One substrate is provided, has relative a upper surface and a lower surface;
The semiconductor chip is set on this upper surface of this substrate;
Form this semiconductor chip of a packaging body coats, wherein this packaging body has a upper surface;
In this packaging body, cut out a depressed part, wherein this depressed part extends a distance from this upper surface of this packaging body toward the direction of this substrate, and this distance is less than the thickness of this packaging body;
Form several soldered balls on this lower surface of this substrate; And
To position that should depressed part, form a Cutting Road through this packaging body and this substrate, to cut off this packaging body and this substrate, wherein the width of this Cutting Road is less than the width of this depressed part.
7. manufacturing approach as claimed in claim 6 wherein cuts out in this packaging body in this step of this depressed part, and the ratio of the thickness of this distance and this packaging body is between 2/3 to 3/4.
8. manufacturing approach as claimed in claim 7, wherein in this step of this depressed part of this packaging body cutting, this depressed part has a bottom surface, and this bottom surface is at a distance of 100 microns of the distances of this substrate.
9. manufacturing approach as claimed in claim 6 wherein cuts out in this packaging body in this step of this depressed part, and this depressed part forms a sidewall; In forming this Cutting Road this step through this packaging body and this substrate, this packaging body forms a side, and wherein this side of this packaging body is toward sunken inside relatively for this sidewall, and wherein this side of this packaging body is at a distance of at least 5 microns of the distances of this sidewall.
10. manufacturing approach as claimed in claim 6; Wherein in forming this Cutting Road this step through this packaging body and this substrate; This substrate forms a side, and this packaging body forms a side, aligns in fact with this side of this packaging body in this side of this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210002980XA CN102509722A (en) | 2012-01-06 | 2012-01-06 | Semiconductor encapsulating element and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210002980XA CN102509722A (en) | 2012-01-06 | 2012-01-06 | Semiconductor encapsulating element and manufacture method thereof |
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| CN102509722A true CN102509722A (en) | 2012-06-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210002980XA Pending CN102509722A (en) | 2012-01-06 | 2012-01-06 | Semiconductor encapsulating element and manufacture method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786269A (en) * | 2017-11-14 | 2019-05-21 | 蔡宜兴 | Reduce the method and semi-finished product structure of package substrate warpage |
| CN109904296A (en) * | 2017-12-08 | 2019-06-18 | 昱鑫制造股份有限公司 | The cutting method and semiconductor packages unit that die-filling group of semiconductor package |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355568A (en) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | Chip stack package structure |
| US20030024723A1 (en) * | 2001-06-12 | 2003-02-06 | Nitto Denko Corporation | Epoxy resin composition used for encapsulating semiconductor and semiconductor device using the composition |
| US20070114654A1 (en) * | 2005-11-21 | 2007-05-24 | Stmicroelectronics S.A. | Stackable semiconductor package and method for its fabrication |
| CN102074516A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and methods for manufacturing the same |
| CN102157400A (en) * | 2011-01-30 | 2011-08-17 | 南通富士通微电子股份有限公司 | Method for encapsulating high-integration wafer fan-out |
-
2012
- 2012-01-06 CN CN201210002980XA patent/CN102509722A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355568A (en) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | Chip stack package structure |
| US20030024723A1 (en) * | 2001-06-12 | 2003-02-06 | Nitto Denko Corporation | Epoxy resin composition used for encapsulating semiconductor and semiconductor device using the composition |
| US20070114654A1 (en) * | 2005-11-21 | 2007-05-24 | Stmicroelectronics S.A. | Stackable semiconductor package and method for its fabrication |
| CN102074516A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and methods for manufacturing the same |
| CN102157400A (en) * | 2011-01-30 | 2011-08-17 | 南通富士通微电子股份有限公司 | Method for encapsulating high-integration wafer fan-out |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786269A (en) * | 2017-11-14 | 2019-05-21 | 蔡宜兴 | Reduce the method and semi-finished product structure of package substrate warpage |
| CN109904296A (en) * | 2017-12-08 | 2019-06-18 | 昱鑫制造股份有限公司 | The cutting method and semiconductor packages unit that die-filling group of semiconductor package |
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Application publication date: 20120620 |