CN115714138B

CN115714138B - IGBT device and preparation method thereof

Info

Publication number: CN115714138B
Application number: CN202211408019.0A
Authority: CN
Inventors: 侯晓伟; 郭依腾; 罗杰馨; 柴展
Original assignee: Shanghai Gongcheng Semiconductor Technology Co Ltd
Current assignee: Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date: 2022-11-10
Filing date: 2022-11-10
Publication date: 2023-08-15
Anticipated expiration: 2042-11-10
Also published as: CN115714138A

Abstract

The application provides an IGBT device and a preparation method thereof, wherein the device comprises: a substrate on which an emitter, an IGBT gate and a collector of the IGBT device are formed; a dummy gate disposed between the gate and the emitter; the first NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the first NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the first NMOS tube is electrically connected with the dummy grid electrode; and the second NMOS tube is arranged between the dummy grid electrode and the emitter electrode, the source electrode of the second NMOS tube is electrically connected with the dummy grid electrode, the drain electrode of the second NMOS tube is electrically connected with the emitter electrode, and the grid electrode is electrically connected with the emitter electrode through an inductor. According to the application, the change of the potential of the dummy grid is controlled in different working states (on state and off process) of the device, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

Description

IGBT device and preparation method thereof

Technical Field

The application belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to an IGBT device and a preparation method thereof.

Background

An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (bipolar transistor) and a MOS (insulated gate field effect transistor). The IGBT device has the advantages of reduced saturation voltage, high current density, small driving power and high switching speed, and is suitable for a power supply management system with the withstand voltage of more than 600V.

The losses of the IGBT device generally include a conduction loss and a switching loss, and in designing the device, a compromise is generally required between the conduction loss and the switching loss, and in order to optimize the switching loss of the device, a dummy gate is generally used to reduce the switching loss of the device, but the arrangement of the dummy gate increases the conduction loss of the IGBT device.

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide an IGBT device and a method for manufacturing the same, which are used for solving the problem of larger conduction loss or/and switching loss of the IGBT device in the prior art.

To achieve the above and other related objects, the present application provides an IGBT device comprising: a substrate on which an emitter, an IGBT gate and a collector of the IGBT device are formed; a dummy gate disposed between the gate and the emitter; the first NMOS tube is arranged on the substrate and between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the first NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the first NMOS tube is electrically connected with the dummy grid electrode; the second NMOS tube is arranged on the substrate, between the dummy grid and the emitter, the source electrode of the second NMOS tube is electrically connected with the dummy grid, the drain electrode of the second NMOS tube is electrically connected with the emitter, and the grid electrode of the second NMOS tube is electrically connected with the emitter through an inductor.

Optionally, when the IGBT device is turned on, the IGBT gate applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, so that the IGBT gate is connected to the dummy gate, and a channel is formed under the dummy gate to reduce the turn-on loss of the IGBT device.

Optionally, when the IGBT device is turned off, the current of the emitter decreases, and there is a voltage change in the inductance between the second NMOS transistor and the emitter, so that the second NMOS transistor is turned on, and the dummy gate is connected to the emitter, thereby reducing the turn-off loss of the IGBT device.

Optionally, the threshold voltage of the first NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the first NMOS transistor is only less than or equal to 5V.

Optionally, the IGBT gate and the dummy gate are arranged in a ring shape, the dummy gate surrounds the emitter periphery, and the IGBT gate surrounds the dummy gate periphery.

Optionally, the substrate includes a first surface and a second surface opposite to each other, the emitter and the IGBT gate are disposed on the first surface of the substrate, and the collector is disposed on the second surface of the substrate, or/and the IGBT device further includes a field stop layer disposed in the substrate and disposed near the collector.

Optionally, the inductance value of the inductor is 10nH to 20nH.

The application also provides a preparation method of the IGBT device, which comprises the following steps: providing a substrate, and forming an emitter, an IGBT grid, a collector and a dummy grid of the IGBT device on the substrate, wherein the dummy grid is arranged between the grid and the emitter; a first NMOS tube is arranged on the substrate, the first NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the first NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the first NMOS tube is electrically connected with the dummy grid electrode; and a second NMOS tube is arranged on the substrate, the second NMOS tube is arranged between the dummy grid electrode and the emitter electrode, the source electrode of the second NMOS tube is electrically connected with the dummy grid electrode, the drain electrode of the second NMOS tube is electrically connected with the emitter electrode, and the grid electrode of the second NMOS tube is electrically connected with the emitter electrode through an inductor.

Optionally, disposing the first NMOS transistor and the second NMOS transistor on the substrate includes the steps of: forming a first P well and a second P well in the substrate through an ion implantation process; forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate, a gate of a first NMOS tube and a gate of a second NMOS tube through patterning; forming a source electrode and a drain electrode of a first NMOS tube in the first P well through an ion implantation process, and forming a source electrode and a drain electrode of a second NMOS tube in the second P well; forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through patterning, enabling a source electrode and a grid electrode of the first NMOS tube to be electrically connected with the IGBT grid electrode, enabling a drain electrode to be electrically connected with the dummy grid electrode, enabling a source electrode of the second NMOS tube to be electrically connected with the dummy grid electrode, enabling the drain electrode to be electrically connected with the emitter electrode, and enabling the grid electrode to be connected with a contact point.

Optionally, the method further comprises the steps of: and an inductor is connected between the contact point of the grid electrode of the second NMOS tube and the emitter through an external pin, and the inductance value of the inductor is 10 nH-20 nH.

Optionally, when the IGBT device is turned on, the IGBT gate applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, so that the IGBT gate is connected to the dummy gate, and a channel is formed under the dummy gate to reduce the turn-on loss of the IGBT device; when the IGBT device is turned off, the current of the emitter is reduced, and voltage variation exists in the inductance between the second NMOS tube and the emitter, so that the second NMOS tube is conducted, the dummy grid is connected with the emitter, and turn-off loss of the IGBT device is reduced.

As described above, the IGBT device and the method of manufacturing the same of the present application have the following advantageous effects:

when the IGBT device is conducted, the threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the first NMOS tube to conduct the first NMOS tube, so that the IGBT gate is connected with the dummy gate, and a channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned off, the current of the emitter is reduced, and the inductance between the second NMOS tube and the emitter has voltage change, so that the second NMOS tube is turned on, the dummy grid is connected with the emitter, and the turn-off loss of the IGBT device is reduced. According to the application, the change of the potential of the dummy grid is controlled in different working states (on state and off process) of the device, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

The first NMOS tube and the second NMOS tube are arranged among the IGBT grid electrode, the dummy grid electrode and the emitter electrode, the area of the device is not required to be occupied additionally, the turn-off loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the manufacturing process of the IGBT device is compatible with the conventional manufacturing process of the IGBT device, additional manufacturing equipment is not required to be added, and the manufacturing cost of the device can be effectively controlled.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the application.

Fig. 1 is a schematic diagram of a layout structure of an IGBT device according to an embodiment of the present application.

Fig. 2 is a schematic circuit diagram of an IGBT device according to an embodiment of the application.

Fig. 3 to 8 show schematic structural diagrams of steps of a method for manufacturing an IGBT device according to an embodiment of the application.

Description of element reference numerals

10 IGBT grid

11. Dummy gate

12. Emitter electrode

13. First NMOS tube

14. Second NMOS tube

15. Inductance

101. Substrate and method for manufacturing the same

102. First P well

103. Second P well

104. First NMOS gate

105. Second NMOS gate

106. First NMOS source electrode

107. First NMOS drain electrode

108. Second NMOS source electrode

109. Second NMOS drain electrode

110. Insulating layer

111. First wiring

112. Second wiring

113. Contact point

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

As shown in fig. 1 to 8, the present embodiment provides an IGBT device including: a substrate 101, wherein an emitter 12, an IGBT gate 10 and a collector of the IGBT device are formed on the substrate 101; a dummy gate 11 disposed between the gate and the emitter 12; a first NMOS transistor 13, where the first NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, a source 106 and a gate 104 of the first NMOS transistor 13 are electrically connected to the IGBT gate 10, and a drain 107 is electrically connected to the dummy gate 11; and a second NMOS transistor 14, wherein the second NMOS transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12, a source 108 of the second NMOS transistor 14 is electrically connected to the dummy gate 11, a drain 109 is electrically connected to the emitter 12, and a gate 105 is electrically connected to the emitter 12 through an inductor 15.

The substrate 101 may be, for example, a silicon substrate 101, and the substrate 101 may also include other semiconductors such as germanium, silicon carbide (SiC), or silicon germanium (SiGe), among others. The substrate 101 may include a compound semiconductor and/or an alloy semiconductor, such as gallium nitride, gallium arsenide, or the like. In addition, the substrate 101 may include an epitaxial layer (epitaxial layer) or may be strained to improve performance. In this embodiment, the substrate 101 includes a drift region, such as an N-type lightly doped drift region.

The substrate 101 includes a first surface and a second surface opposite to each other, the emitter 12 and the IGBT gate 10 are disposed on the first surface of the substrate 101, and the collector is disposed on the second surface of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed near the collector.

In one embodiment, the emitter 12 of the IGBT device includes an n+ type emitter region, and a P type body region, not shown, disposed between the n+ type emitter region and the N-type drift region.

As shown in fig. 1, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, such as a rectangular ring, a rounded rectangular ring, an elliptical ring, a circular ring, etc., the dummy gate 11 surrounds the emitter 12, the IGBT gate 10 surrounds the dummy gate 11, a space is provided between the IGBT gate 10 and the dummy gate 11, and a space is provided between the dummy gate 11 and the emitter 12.

As shown in fig. 1 and 8, fig. 8 is a schematic cross-sectional structure of the dashed line in fig. 1, where the first NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, and the first NMOS transistor 13 includes a first P-well 102 disposed in the substrate 101, a first NMOS gate 104 disposed on the first P-well 102, and a source and a drain disposed in the first P-well 102 on both sides of the first NMOS gate 104. In one embodiment, the threshold voltage of the first NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the threshold voltage of the IGBT gate 10 is only different from the threshold voltage of the first NMOS transistor 13 by less than or equal to 5V. For example, the threshold voltage of the gate of the IGBT device may be 15V, and the threshold voltage of the gate of the first NMOS transistor 13 may be set between 13.5V and 15V. According to the application, through controlling the change of the potential of the dummy grid electrode in different working states of the device, the heating of the device can be effectively improved, the power density is increased, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

As shown in fig. 1 and 8, the second NMOS transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12, and the second NMOS transistor 14 includes a second P-well 103 disposed in the substrate 101, a second NMOS gate 105 disposed on the second P-well 103, and a source and a drain disposed in the second P-well 103 on both sides of the second NMOS gate 105.

As shown in fig. 8, the source and gate of the first NMOS transistor 13 are electrically connected to the IGBT gate 10 through a first wiring 111, the drain of the dummy gate 11 is electrically connected to the source of the second NMOS transistor 14 through a second wiring 112, the drain of the second NMOS transistor 14 is electrically connected to the emitter 12, a contact point 113 is provided on the gate through the wiring, and when a pin is subsequently provided, the contact point 113 is electrically connected to the emitter 12 through an inductor 15.

In one embodiment, the inductance value of the inductor 15 is 10nH to 20nH, for example, the inductance value of the inductor 15 may be 13nH.

In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the first NMOS transistor 13 to turn on the first NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and a channel is formed under the dummy gate 11 to reduce the turn-on loss of the IGBT device.

In one embodiment, when the IGBT device is turned off, the current of the emitter 12 decreases, and there is a voltage change in the inductance 15 between the second NMOS transistor 14 and the emitter 12, so that the second NMOS transistor 14 is turned on, so that the dummy gate 11 is connected to the emitter 12, thereby reducing the turn-off loss of the IGBT device.

As shown in fig. 2, the schematic circuit diagram of the IGBT device of this embodiment is specifically that when the IGBT device is in the on state, the voltage of the gate is about 15V, the drain of the first NMOS transistor 13 is shorted to the IGBT gate 10 at this time, the dummy gate 11 is shorted to the source, when the voltage of the first NMOS gate 104 is 15V, the first NMOS transistor 13 is turned on, the potential of the IGBT gate 10 is the same as the potential of the dummy gate 11, at this time, the channels on both sides of the dummy gate 11 of the device are opened, and VCESAT of the device is reduced, thereby reducing the conduction loss of the device.

The inductance 15 exists in the emitter 12 of the IGBT device of this embodiment, for example, the inductance 15 is integrated in the TO247, when the device is in the turn-off process, the current of the emitter 12 decreases, for example, the IGBT device of 650V15A, the current change di/dt in the inductance 15 is about 150A/us in the turn-off process of the device, so that the voltage change at two ends of the inductance 15 of the emitter 12 is about 1.95V, and the second NMOS tube 14 is turned on, so that the dummy gate 11 and the emitter 12 are connected together, thereby effectively reducing the turn-off loss of the device.

As shown in fig. 1 to 8, the present embodiment further provides a method for manufacturing an IGBT device, the method comprising the steps of: providing a substrate 101, forming an emitter 12, an IGBT gate 10, a collector and a dummy gate 11 of an IGBT device on the substrate 101, wherein the dummy gate 11 is arranged between the gate and the emitter 12; a first NMOS transistor 13 is disposed on the substrate 101, the first NMOS transistor 13 is disposed between the IGBT gate 10 and the dummy gate 11, a source 106 and a gate 104 of the first NMOS transistor 13 are electrically connected to the IGBT gate 10, and a drain 107 is electrically connected to the dummy gate 11; a second NMOS transistor 14 is disposed on the substrate 101, the second NMOS transistor 14 is disposed between the dummy gate 11 and the emitter 12, a source 108 of the second NMOS transistor 14 is electrically connected to the dummy gate 11, a drain 109 is electrically connected to the emitter 12, and the gate is electrically connected to the emitter 12 through an inductor 15.

In one embodiment, as shown in fig. 3 to 8, disposing the first NMOS transistor 13 and the second NMOS transistor 14 on the substrate 101 includes the following steps:

as shown in fig. 3 to 4, step 1) is performed first, and a first P-well 102 and a second P-well 103 are formed in the substrate 101 by an ion implantation process; of course, in this process, structures such as P-type body regions of the IGBT device may be fabricated at the same time, so as to save process costs.

As shown in fig. 5, step 2) is then performed to form a gate dielectric layer and a gate layer on the substrate 101, and form the IGBT gate 10, the dummy gate 11, the gate of the first NMOS transistor 13, and the gate of the second NMOS transistor 14 by a patterning process. The gate dielectric layer may be silicon dioxide, or the like, or may be a high-k dielectric, such as hafnium oxide, or the like, and the gate dielectric layer may be polysilicon, metal, or the like.

As shown in fig. 6, step 3) is performed, the source and the drain of the first NMOS transistor 13 are formed in the first P-well 102, and the source and the drain of the second NMOS transistor 14 are formed in the second P-well 103 by an ion implantation process. Of course, in this process, structures such as an emitter region of the IGBT may be simultaneously fabricated, so as to save the process cost.

As shown in fig. 7 to 8, step 4) is finally performed, an insulating layer 110 is formed on the substrate 101, a contact hole is formed in the insulating layer 110, a metal layer is formed on the contact hole and the insulating layer 110, a wiring layer is formed by patterning, the source and the gate of the first NMOS transistor 13 are electrically connected to the IGBT gate 10 through the contact hole and the wiring layer, the drain is electrically connected to the dummy gate 11, the source of the second NMOS transistor 14 is electrically connected to the dummy gate 11, the drain is electrically connected to the emitter 12, and the gate is connected to the contact point 113.

In one embodiment, the method further comprises the steps of: an inductor 15 is connected between the contact point 113 of the gate of the second NMOS transistor 14 and the emitter 12 through an external pin, and the inductance value of the inductor 15 is 10 nH-20 nH.

In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the first NMOS transistor 13 to turn on the first NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and a channel is formed under the dummy gate 11 to reduce the turn-on loss of the IGBT device; when the IGBT device is turned off, the current of the emitter 12 decreases, and there is a voltage change in the inductance 15 between the second NMOS transistor 14 and the emitter 12, so that the second NMOS transistor 14 is turned on, and the dummy gate 11 is connected to the emitter 12, thereby reducing the turn-off loss of the IGBT device.

In one embodiment, the threshold voltage of the first NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the threshold voltage of the IGBT gate 10 is only different from the threshold voltage of the first NMOS transistor 13 by less than or equal to 5V.

In one embodiment, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, the dummy gate 11 surrounds the emitter 12, and the IGBT gate 10 surrounds the dummy gate 11.

In one embodiment, the substrate 101 includes a first side and a second side opposite to each other, the emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, and the collector is disposed on the second side of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed adjacent to the collector.

when the IGBT device is turned on, the threshold voltage is applied to the IGBT gate 10, and the threshold voltage is simultaneously applied to the gate of the first NMOS tube 13 to enable the first NMOS tube 13 to be turned on, so that the IGBT gate 10 is connected with the dummy gate 11, and a channel is formed below the dummy gate 11 to reduce the conduction loss of the IGBT device. When the IGBT device is turned off, the current of the emitter 12 is reduced, and the inductance 15 between the second NMOS tube 14 and the emitter 12 has voltage change, so that the second NMOS tube 14 is turned on, the dummy gate 11 is connected with the emitter 12, and the turn-off loss of the IGBT device is reduced. According to the application, through controlling the change of the potential of the dummy gate 11 in different working states of the device, the heating of the device can be effectively improved, the power density is increased, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

The first NMOS tube 13 and the second NMOS tube 14 are arranged among the IGBT grid electrode 10, the dummy grid electrode 11 and the emitter electrode 12, the area of the device is not required to be occupied additionally, the turn-off loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the manufacturing process of the IGBT device is compatible with the conventional manufacturing process of the IGBT device, additional manufacturing equipment is not required to be added, and the manufacturing cost of the device can be effectively controlled.

Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. An IGBT device, the IGBT device comprising:

a substrate on which an emitter, an IGBT gate and a collector of the IGBT device are formed;

a dummy gate disposed between the IGBT gate and the emitter;

the first NMOS tube is arranged on the substrate and between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the first NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the first NMOS tube is electrically connected with the dummy grid electrode;

the second NMOS tube is arranged on the substrate and between the dummy grid and the emitter, a source electrode of the second NMOS tube is electrically connected with the dummy grid, a drain electrode of the second NMOS tube is electrically connected with the emitter, and a grid electrode of the second NMOS tube is electrically connected with the emitter through an inductor.

2. The IGBT device of claim 1 wherein: when the IGBT device is conducted, the IGBT gate electrode applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate electrode of the first NMOS tube to conduct the first NMOS tube, so that the IGBT gate electrode is connected with the dummy gate electrode, and a channel is formed below the dummy gate electrode to reduce the conduction loss of the IGBT device.

3. The IGBT device of claim 1 wherein: when the IGBT device is turned off, the current of the emitter is reduced, and voltage variation exists in the inductance between the second NMOS tube and the emitter, so that the second NMOS tube is conducted, the dummy grid is connected with the emitter, and turn-off loss of the IGBT device is reduced.

4. The IGBT device of claim 1 wherein: the threshold voltage of the first NMOS tube is smaller than or equal to that of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the first NMOS tube is smaller than or equal to 5V.

5. The IGBT device of claim 1 wherein: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the emitter, and the IGBT grid surrounds the periphery of the dummy grid.

6. The IGBT device of claim 1 wherein: the substrate comprises a first surface and a second surface which are opposite, the emitter and the IGBT grid electrode are arranged on the first surface of the substrate, the collector electrode is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the collector electrode.

7. The IGBT device of claim 1 wherein: the inductance value of the inductor is 10 nH-20 nH.

8. The preparation method of the IGBT device is characterized by comprising the following steps of:

providing a substrate, and forming an emitter, an IGBT grid, a collector and a dummy grid of the IGBT device on the substrate, wherein the dummy grid is arranged between the IGBT grid and the emitter;

a first NMOS tube is arranged on the substrate, the first NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, a source electrode and a grid electrode of the first NMOS tube are electrically connected with the IGBT grid electrode, and a drain electrode of the first NMOS tube is electrically connected with the dummy grid electrode;

and a second NMOS tube is arranged on the substrate, the second NMOS tube is arranged between the dummy grid electrode and the emitter electrode, the source electrode of the second NMOS tube is electrically connected with the dummy grid electrode, the drain electrode of the second NMOS tube is electrically connected with the emitter electrode, and the grid electrode of the second NMOS tube is electrically connected with the emitter electrode through an inductor.

9. The method for manufacturing the IGBT device according to claim 8, wherein: the step of arranging a first NMOS tube and a second NMOS tube on the substrate comprises the following steps:

forming a first P well and a second P well in the substrate through an ion implantation process;

forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate, a gate of a first NMOS tube and a gate of a second NMOS tube through patterning;

forming a source electrode and a drain electrode of a first NMOS tube in the first P well through an ion implantation process, and forming a source electrode and a drain electrode of a second NMOS tube in the second P well;

forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through patterning, enabling a source electrode and a grid electrode of the first NMOS tube to be electrically connected with the IGBT grid electrode through the contact hole and the wiring layer, enabling a drain electrode of the first NMOS tube to be electrically connected with the dummy grid electrode, enabling a source electrode of the second NMOS tube to be electrically connected with the dummy grid electrode, enabling a drain electrode of the second NMOS tube to be electrically connected with the emitter electrode, and enabling a grid electrode of the second NMOS tube to be connected with a contact point.

10. The method for manufacturing the IGBT device according to claim 9, characterized in that: the method also comprises the steps of: and an inductor is connected between the contact point of the grid electrode of the second NMOS tube and the emitter through an external pin, and the inductance value of the inductor is 10 nH-20 nH.

11. The method for manufacturing the IGBT device according to claim 10, wherein: when the IGBT device is conducted, the IGBT gate electrode applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate electrode of the first NMOS tube to conduct the first NMOS tube, so that the IGBT gate electrode is connected with the dummy gate electrode, and a channel is formed below the dummy gate electrode to reduce the conduction loss of the IGBT device; when the IGBT device is turned off, the current of the emitter is reduced, and voltage variation exists in the inductance between the second NMOS tube and the emitter, so that the second NMOS tube is conducted, the dummy grid is connected with the emitter, and turn-off loss of the IGBT device is reduced.

12. The method for manufacturing the IGBT device according to claim 8, wherein: the threshold voltage of the first NMOS tube is smaller than or equal to that of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the first NMOS tube is smaller than or equal to 5V.

13. The method for manufacturing the IGBT device according to claim 8, wherein: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the emitter, and the IGBT grid surrounds the periphery of the dummy grid.

14. The method for manufacturing the IGBT device according to claim 8, wherein: the substrate comprises a first surface and a second surface which are opposite, the emitter and the IGBT grid electrode are arranged on the first surface of the substrate, the collector electrode is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the collector electrode.