CN115713962A - Memory test method, system and computer readable storage medium - Google Patents
Memory test method, system and computer readable storage medium Download PDFInfo
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Abstract
The invention provides a memory test method, a system and a computer readable storage medium, wherein the method comprises the following steps: adjusting test acceleration factors of the memory to be tested according to preset conditions, wherein the test acceleration factors comprise temperature, working voltage, interface time sequence and the like; inputting preset test data into the tested internal memory, wherein the preset test data is used for testing whether the physical structure of the tested internal memory works normally under the influence of the test acceleration factor; acquiring actual test data of a memory to be tested; and when the actual test data is consistent with the preset test data, determining that the test is passed, and establishing a quality multidimensional approximate model of the product. The invention tests the internal memory under the state that the test acceleration factor is changed by changing the working environment of the tested internal memory, thereby detecting whether the physical structure of the tested internal memory can normally work under the current working environment, expanding the adjustable external factors in the test process and being more beneficial to exciting a deep fault mode.
Description
Technical Field
The present invention relates to the field of memory testing technologies, and in particular, to a memory testing method and system, and a computer-readable storage medium.
Background
At present, a memory (internal memory) and a solid state disk are widely applied to product equipment such as computers, mobile phones, servers, intelligent automobiles and the like. The memory and the solid state disk are key components for data processing and data storage, and the reliability of the memory and the solid state disk is very important. Meanwhile, storage media such as DRAM (Dynamic Random Access Memory), 3DNANDFLASH (NAND flash Memory) and the like are key devices for developing memories and solid state disks. These media all have a high discrete failure rate in physical properties. Therefore, when memory and solid state disk products are researched and developed, strict screening tests are carried out in the testing link of research and development and production, and accordingly, failure products which do not meet the requirements are screened out.
In the related art, a produced finished product is often inserted into a main board, and a fault is triggered by running preset test data, so that the purpose of screening is achieved. However, as the demands for capacity and density of storage media and reduction of power consumption are continuously increased, the manufacturing process is more complicated, and such test methods bring more and more randomness and uncertainty, and it is difficult to screen out deep faults.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a memory test method, a memory test system and a computer readable storage medium, which realize the detection of deep faults of the storage medium by carrying out joint control on interface time sequence, temperature and working voltage. Meanwhile, the critical conditions possibly encountered in the actual use process can be simulated more truly.
In a first aspect, an embodiment of the present invention provides a memory testing method, where the method includes:
adjusting a test acceleration factor of a memory to be tested according to a preset condition, wherein the test acceleration factor comprises temperature, working voltage and interface time sequence;
inputting preset test data into the tested internal memory, wherein the preset test data is used for testing whether a physical structure of the tested internal memory works normally under the influence of the test acceleration factor;
obtaining actual test data of the memory under test;
when the actual test data is consistent with the preset test data, determining that the test is passed;
and establishing a quality multidimensional approximate model according to the actual test data.
In some embodiments, the obtaining actual test data of the memory under test includes: acquiring the real-time test data for multiple times according to a preset interval; and obtaining the actual test data according to the plurality of real-time test data.
In some embodiments, the obtaining actual test data of the memory under test includes: and measuring the actual test data at a single time according to a preset time node.
In some embodiments, the method further comprises: and when the actual test data is inconsistent with the preset test data, determining that the test is not passed.
In some embodiments, the method further comprises: and when the test is determined not to pass, replacing the preset test data and testing the memory to be tested.
In some embodiments, the method further comprises: when the tested memory is determined not to pass the test, marking the tested memory as a failure product.
In some embodiments, the method further comprises: and after the test is finished, storing and recording the current preset test data and the test result.
In some embodiments, after the storing and recording the current preset test data, the method further includes: obtaining model data of the memory to be tested; and obtaining optimal test data corresponding to the model data according to the model data, the plurality of preset test data and the corresponding test results.
In some embodiments, the method further comprises: and establishing a mapping relation among the test acceleration factor, the model data, the preset test data and the optimal test data.
In some embodiments, the adjusting the test acceleration factor of the memory under test according to the preset condition specifically includes: and adjusting one or more test acceleration factors of the memory under test according to preset conditions.
In a second aspect, an embodiment of the present invention provides a memory test system, including:
the adjusting module is used for adjusting a test acceleration factor of the memory to be tested, wherein the test acceleration factor comprises temperature, working voltage and interface time sequence;
a writing module, configured to input preset test data into the internal memory under test, where the preset test data is used to test whether a physical structure of the internal memory under test normally operates under the influence of the test acceleration factor;
the reading module is used for obtaining actual test data of the memory to be tested;
the judging module is used for judging whether the actual test data is consistent with the preset test data or not, and when the actual test data is consistent with the preset test data, determining that the test is passed;
and the modeling module is used for establishing a quality multidimensional approximate model according to the actual test data.
In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the memory testing method according to the first aspect is implemented.
The embodiment of the invention comprises the following steps: and taking the temperature, the working voltage and the interface time sequence as test acceleration factors of the tested internal memory, and then adjusting the test acceleration factors of the tested internal memory according to preset conditions. After the test acceleration factors are set, inputting preset test data into the tested internal memory, and under the combined action of different test acceleration factors, the preset test data may change in the actual detection process, so after the preset test data is input and detection is performed, the actual test data needs to be read from the tested internal memory, the actual test data is compared with the preset test data, and when the actual test data is judged to be consistent with the preset test data, the test is determined to be passed. According to the scheme provided by the embodiment of the invention, the working environment of the tested internal memory is changed so as to test the internal memory under the state of different combinations of multiple test acceleration factors, thereby detecting whether the physical structure of the tested internal memory can normally work under the current working environment, and finally establishing the quality multidimensional approximate model according to actual test data. The invention expands the adjustable external factors in the test process, is more favorable for exciting a deep fault mode, and provides a wider idea for the design of the internal memory.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a flowchart of a memory testing method according to an embodiment of the present invention;
FIG. 2 is a flow chart of multiple times of actual test data acquisition provided by an embodiment of the present invention;
FIG. 3 is a flow chart of a single acquisition of actual test data provided by an embodiment of the present invention;
FIG. 4 is a flow chart for determining optimal test data provided by an embodiment of the present invention;
fig. 5 is a block diagram of a memory test system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
It is noted that while a division of functional blocks is depicted in a block diagram, and logical order is depicted in a flowchart, in some cases the steps depicted and described may be performed in a different order than the division of blocks within a block diagram or flowchart.
The memory testing method and the application scenario described in the embodiments of the present invention are for more clearly illustrating the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided in the embodiments of the present invention, and it is known to those skilled in the art that the technical solutions provided in the embodiments of the present invention are also applicable to similar technical problems along with the evolution of the memory testing field and the emergence of new application scenarios.
As shown in fig. 1, fig. 1 is a flowchart of a memory testing method according to an embodiment of the present invention. It is understood that the present invention provides a memory test method, including but not limited to step S100, step S200, step S300, step S400, and step S500.
And S100, adjusting a test acceleration factor of the memory to be tested according to preset conditions, wherein the test acceleration factor comprises temperature, working voltage and interface time sequence.
Step S200, inputting preset test data into the tested internal memory, where the preset test data is used to test whether the physical structure of the tested internal memory works normally under the influence of the test acceleration factor.
Step S300, obtaining actual test data of the memory under test.
And S400, when the actual test data is consistent with the preset test data, determining that the test is passed.
And S500, establishing a quality multidimensional approximation model according to the actual test data.
It can be understood that, in the process of testing the internal memory, step S100 needs to be performed first, and the test acceleration factor of the internal memory under test is adjusted according to the preset condition, where the test acceleration factor includes, but is not limited to, temperature, operating voltage, and interface timing. After the test acceleration factor is set, step S200 is executed to input preset test data into the memory under test. However, under the combined action of different test acceleration factors, the preset test data may change in the actual detection process, and therefore after the preset test data is input and detected, steps S300 to S400 need to be executed to read the actual test data from the tested internal memory, compare the actual test data with the preset test data, and when the actual test data is judged to be consistent with the preset test data, the test can be determined to pass. And finally, executing step S500, and establishing a quality multidimensional approximation model according to the actual test data.
It is to be understood that, after the steps S100 to S500 are performed, the step S100 may be performed again according to an actual test requirement, and the steps S200 to S500 may be performed in sequence to perform multiple tests on the internal memory, which is not limited in the present invention.
It should be noted that the preset test data is used to determine whether the physical structure of the input address space can work normally, that is, determine whether the internal memory can work normally. In the memory testing method provided by the invention, the working environment of the tested memory is changed, namely, the memory is tested in different combination states of a plurality of test accelerating factors, so that whether the physical structure of the tested memory can work normally in the current working environment is detected. According to the invention, various external test accelerating factors are integrated in the test process, adjustable external factors in the test process are expanded, the working environment of the internal memory can be flexibly and jointly adjusted in the test process, and the potential quality defect problem can be effectively triggered by applying the external test accelerating factors, so that a deep fault mode can be more favorably excited, and the test efficiency and the defect detection rate are improved. Meanwhile, a quality multidimensional approximate model of the product is established, and the model can be repeatedly updated according to a plurality of test results and is used for guiding subsequent tests so as to improve the efficiency and the accuracy.
It should be noted that each parameter in the working environment of the internal memory has a range in which it can work normally, for example, the working temperature may range from-40 ℃ to 85 ℃. If this range is exceeded, the internal memory may fail a large amount in operation. These failures can be potential weak points and also the normal performance of the internal memory. Therefore, in the process of testing the internal memory, the setting of the test acceleration factor is usually set to be out of a certain range, so as to detect the boundary condition of the trigger fault.
It should be noted that, when adjusting the test acceleration factor of the memory under test, since the test acceleration factor at least includes temperature, operating voltage and interface timing, one or more of the plurality of test acceleration factors may be adjusted according to actual requirements during adjustment.
As shown in fig. 2, fig. 2 is a flowchart for acquiring actual test data multiple times according to an embodiment of the present invention. It is understood that, in step S300, there are specifically, but not limited to, step S310 and step S320.
Step S310, real-time test data are obtained for multiple times according to preset intervals.
Step S320, obtaining actual test data according to the plurality of real-time test data.
It can be understood that, in the process of actually testing the internal memory, different data obtaining manners may be selected due to different requirements, and in this embodiment, the implementation test data is obtained multiple times according to the preset interval, and the multiple real-time test data is averaged, so as to obtain the actual test data. Therefore, the method of obtaining real-time test data for multiple times and averaging can improve the fault tolerance of the test.
As shown in fig. 3, fig. 3 is a flowchart of acquiring actual test data in a single time according to an embodiment of the present invention. It is understood that, in step S300, there is also included, but not limited to, step S330.
And step S330, measuring actual test data once according to the preset time node.
It can be understood that, besides the mode of obtaining real-time test data and averaging for multiple times, the detection can be directly performed at the preset time node according to the actual requirement, and such design can perform detection aiming at the special condition generated at a certain specific time node in the test process. It should be noted that, in the process of actually detecting the internal memory, the obtained actual test data only needs to be able to test whether the physical structure of the internal memory under test normally works under the influence of the test acceleration factor, and the specific obtaining mode of the actual test data is not limited in the present invention.
It should be noted that, when the actual test data acquired in step S300 is inconsistent with the preset test data, it is determined that the test does not pass. When the test fails, the preset test data can be replaced or the test acceleration factor can be changed according to the actual requirement, and the internal memory is tested again, or the internal memory is directly marked as a failure product which does not meet the requirement. By changing the working environment of the internal memory, namely changing the interface timing sequence, temperature, working voltage and other test acceleration factors of the internal memory, extreme situations which may be met by the internal memory in various use environments can be simulated more truly, and the test data acquired under the extreme situations can also bring a better idea for the design of the internal memory, provide a more flexible use method for a user, and provide better support for the development of an algorithm.
It should be noted that, after the test is completed, the system stores and records the preset test data currently written into the tested internal memory and the corresponding test result, so that the manager can call and check the preset test data.
As shown in fig. 4, fig. 4 is a flowchart for determining optimal test data according to an embodiment of the present invention. It is understood that, after the preset test data currently written into the memory under test and the corresponding test result are recorded, the method further includes, but is not limited to, step S510 and step S520.
And step S510, obtaining model data of the memory to be tested.
And S520, obtaining optimal test data corresponding to the model data according to the model data, the preset test data and the corresponding test results.
It can be understood that, the input preset test data are different, and the output results may be different; and for different models of internal memories or different batches of internal memories, the corresponding optimal test data may be different. Therefore, after the test, step S510 and step S520 need to be executed to obtain the model data of the internal memory under test, and according to the model data, a plurality of preset test data used by the internal memory in the test process, and the corresponding test result, the optimal test data corresponding to the internal memory of the batch under test is obtained.
It should be noted that, because the test result of the internal memory may also change when the value of the test acceleration factor changes, a mapping relationship between the test acceleration factor, the model data, the preset test data, and the optimal test data needs to be established, so that a designer can conveniently determine the working environment range of the internal memory.
As shown in fig. 5, fig. 5 is a block diagram of a memory test system according to an embodiment of the present invention. It is understood that the present invention also provides a memory test system 100, and the memory test system 100 includes, but is not limited to, a regulation module 110, a write module 120, a read module 130, a determination module 140, and a modeling module 150. The adjusting module 110 is configured to adjust a test acceleration factor of the memory under test, where the test acceleration factor includes a temperature, a working voltage, and an interface timing sequence; a write-in module 120, configured to input preset test data into the internal memory under test, where the preset test data is used to test whether a physical structure of the internal memory under test works normally under the influence of the test acceleration factor; a reading module 130, configured to obtain actual test data of the memory under test; the judging module 140 is configured to judge whether the actual test data is consistent with the preset test data, and determine that the test is passed when the actual test data is consistent with the preset test data; and the modeling module 150 is used for establishing a quality multidimensional approximate model according to the actual test data. In the memory test system 100 of the present invention, a device interface timing adjusting device, a working voltage adjusting device, and a temperature adjusting device (i.e. an adjusting module 110) are packaged on a test motherboard, and the interface timing, the working voltage, and the temperature are used as test acceleration factors to perform a test. The memory test system 100 provided by the present invention tests the internal memory under different combination states of multiple test acceleration factors by changing the working environment of the tested internal memory, thereby detecting whether the physical structure of the tested internal memory can work normally under the current working environment, and finally establishing a quality multidimensional approximate model by the modeling module 150. The invention expands the adjustable external factors in the test process, and is more favorable for exciting deep failure modes.
It should be noted that the memory test system 100 may further include a terminal device and an HTTP server. The memory test system 100 includes a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor executes the computer program to implement the memory test method in the above embodiment.
The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs and non-transitory computer executable programs, such as the memory test method in the above embodiments of the present invention. The processor implements the memory test method in the above embodiments of the present invention by running the non-transitory software program and the instructions stored in the memory.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data and the like required for executing the memory test method in the above-described embodiments. Further, the memory may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. It should be noted that the memory may optionally include memory located remotely from the processor, and that such remote memory may be coupled to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The non-transitory software programs and instructions required to implement the memory test method in the above embodiments are stored in the memory, and when executed by one or more processors, perform the memory test method in the above embodiments, for example, perform at least one of the above-described method steps S100 to S500 in fig. 1, method steps S310 to S320 in fig. 2, method step S330 in fig. 3, and method steps S510 to S520 in fig. 4.
The present invention also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the memory testing method in the above-described embodiments, for example, to execute at least one of the method steps S100 to S500 in fig. 1, the method steps S310 to S320 in fig. 2, the method step S330 in fig. 3, and the method steps S510 to S520 in fig. 4 described above.
The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The embodiments of the present invention are described in detail with reference to the drawings, but the present invention is not limited to the embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (12)
1. A memory test method, comprising:
adjusting a test acceleration factor of a memory to be tested according to a preset condition, wherein the test acceleration factor comprises temperature, working voltage and interface time sequence;
inputting preset test data into the tested internal memory, wherein the preset test data is used for testing whether a physical structure of the tested internal memory works normally under the influence of the test acceleration factor;
obtaining actual test data of the memory under test;
when the actual test data is consistent with the preset test data, determining that the test is passed;
and establishing a quality multidimensional approximate model according to the actual test data.
2. The method according to claim 1, wherein the obtaining actual test data of the memory under test comprises:
acquiring the real-time test data for multiple times according to a preset interval;
and obtaining the actual test data according to the plurality of real-time test data.
3. The method according to claim 1, wherein the obtaining actual test data of the memory under test comprises:
and measuring the actual test data in a single time according to a preset time node.
4. The memory test method of claim 1, further comprising:
and when the actual test data is inconsistent with the preset test data, determining that the test is not passed.
5. The memory test method of claim 4, further comprising:
and when the memory under test is determined not to pass the test, replacing the preset test data and testing the memory under test.
6. The memory test method of claim 4, further comprising:
when the tested memory is determined not to pass the test, marking the tested memory as a failure product.
7. The memory test method of claim 5, further comprising:
and after the test is finished, storing and recording the current preset test data and the test result.
8. The memory test method according to claim 7, further comprising, after the storing and recording the current preset test data:
obtaining model data of the memory to be tested;
and obtaining optimal test data corresponding to the model data according to the model data, the plurality of preset test data and the corresponding test results.
9. The memory test method of claim 8, further comprising:
and establishing a mapping relation among the test acceleration factor, the model data, the preset test data and the optimal test data.
10. The memory test method according to claim 9, wherein the adjusting the test acceleration factor of the memory under test according to the preset condition specifically comprises:
and adjusting one or more test acceleration factors of the memory to be tested according to preset conditions.
11. A memory test system, comprising:
the adjusting module is used for adjusting a test acceleration factor of the memory to be tested, wherein the test acceleration factor comprises temperature, working voltage and interface time sequence;
a writing module, configured to input preset test data into the internal memory under test, where the preset test data is used to test whether a physical structure of the internal memory under test normally operates under the influence of the test acceleration factor;
the reading module is used for obtaining actual test data of the tested internal memory;
the judging module is used for judging whether the actual test data is consistent with the preset test data or not, and when the actual test data is consistent with the preset test data, determining that the test is passed;
and the modeling module is used for establishing a quality multidimensional approximate model according to the actual test data.
12. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the memory testing method according to any one of claims 1 to 10.
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Inventor after: Liu Shizhu Inventor after: Cao Xiang Inventor after: Zeng Xiangwei Inventor before: Zhao Chunhui Inventor before: Liu Shizhu Inventor before: Cao Xiang Inventor before: Zeng Xiangwei |