CN115687228B

CN115687228B - PCIe bus-based satellite-borne solid-state storage system and method

Info

Publication number: CN115687228B
Application number: CN202310001279.4A
Authority: CN
Inventors: 刘畅; 董振兴; 安军社; 朱岩; 师雨杰
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2023-01-03
Filing date: 2023-01-03
Publication date: 2023-05-02
Anticipated expiration: 2043-01-03
Also published as: CN115687228A

Abstract

The invention belongs to the technical fields of spaceborne solid-state memories, space storage and transmission, and particularly relates to a PCIe bus-based spaceborne solid-state memory system and method. The system of the invention comprises: the data receiving module receives engineering data and application data sent by CPU software of an external main control module; the data storage module receives the data analyzed by the data receiving module and stores the data into two fixed partitions of the storage array according to the category; the data transmitting module plays back the delay data in the storage module according to the CPU software instruction of the main control module and transmits the delay data to the CPU software of the main control module; the communication control module is communicated with the CPU software of the main control module through a serial bus to complete control and state feedback of the storage related instructions; and the clock management module generates clocks with different frequencies needed inside the FPGA by the DCM from the externally input clock and generates a global reset signal. The invention has high modularization, clear logic, definite function division, strong reusability and strong expandability.

Description

PCIe bus-based satellite-borne solid-state storage system and method

Technical Field

The invention belongs to the technical fields of spaceborne solid-state memories, space storage and transmission, and particularly relates to a PCIe bus-based spaceborne solid-state memory system and method.

Background

The satellite-borne bus technology is very important in satellite-borne data acquisition and transmission, and buses or networks widely applied in the field of aerospace at present mainly comprise RS422, RS485, CAN buses, 1553 buses, LVDS and the like. Although these buses have a wide range of applications, with the complexity and difficulty of the task of space exploration, and the use of more advanced data acquisition devices such as synthetic aperture radars, multispectral imagers in the field of space, the amount of data required for the on-board buses is increasing, and these buses have shortcomings in terms of the rate of transmission, the distance of communication, the coordination of protocols, and power consumption. To meet the high-capacity data transfer and storage requirements, faster, more stable and efficient bus protocols need to be applied.

PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard proposed by intel in 2001, intended to replace the old PCI (Peripheral Component Interconnect ), PCI-X and AGP (Accelerated Graphical Port) bus standards. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices share channel bandwidth exclusively, do not share bus bandwidth, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, quality of service (QOS), and the like. The method has the main advantages of high data transmission rate, PCIe 3.0 speed of 8GT/s and considerable development potential, and is suitable for data transmission in aerospace scenes.

The satellite-borne solid-state storage system is one of key systems of a satellite platform and is used as a data hub to support the development and implementation of satellite tasks. The main function of the satellite-borne solid-state storage system is to receive system engineering data (reflecting working state data of each main control module and interfaces of a scientific experiment system) and application data (the general name of scientific data, video data and image data generated on the track) from CPU software of a main control module computer unit, and store the system engineering data according to classification of two fixed partitions of a project area and a load area; after receiving the playback instruction of the computer unit, reading out the data and sending the data to the computer unit; and to complete the instruction and status interactions with the computer unit.

Most of current satellite-borne solid-state storage systems are in customized design, namely, scheme design is needed to be carried out again on requirements such as effective load data types, storage capacity and storage speed according to different satellite model tasks, so that research and development efficiency is low, reusability is poor, and the like, and therefore hierarchical, modularized, regular and other architecture designs are needed to be carried out on the system, and the reconfigurability and universality of the satellite-borne storage system are improved.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides a PCIe bus-based satellite-borne solid-state memory system, and also discloses a PCIe bus-based satellite-borne solid-state memory method.

In order to achieve the above purpose, the present invention is realized by the following technical scheme.

The invention provides a PCIe bus-based satellite-borne solid-state storage system, which is applied to storage hardware and comprises: a data receiving module and a data storage module; wherein,

the data receiving module is used for receiving engineering data and application data sent by the external main control module, carrying out PCIe physical layer protocol analysis and data application layer protocol analysis, generating corresponding identification signals, and caching data ping-pong into corresponding FIFO;

the data storage module adopts a fixed partition storage mode, performs independent cyclic storage on data according to data types, and takes out and transmits delay data to computer unit CPU software after receiving a playback instruction.

As an improvement of the above technical solution, the data receiving module includes: the system comprises a PCIe protocol analysis receiving unit, an application layer protocol analysis unit, a scientific data pre-coding FIFO unit and an engineering data pre-coding FIFO unit; wherein,

the PCIe protocol analysis receiving unit is used for receiving engineering data and application data sent by the external main control module, checking the received data by using PCIe special IP to complete PCIe physical layer protocol analysis, converting the analyzed data stream and writing the converted data stream into an AXI bus;

The application layer protocol analysis unit is configured to receive the engineering data and the application data analyzed by the PCIe protocol analysis receiving unit, perform packet format discrimination on the received data, and buffer the data into a corresponding engineering data FIFO or application data FIFO according to the discriminated data type, and specifically includes: if the synchronous word is 0x55AA and the identification domain is 0xED D, judging that the data is an engineering data packet, starting one-time data receiving, and writing the received data into an engineering data FIFO for caching; if the synchronous word is 0x55AA and the identification domain is 0x6D 1D-0 x6DFD, judging that the synchronous word is an application data packet, starting data reception once, and writing the received data into an application data FIFO for caching; if the synchronous word is not 0x55AA or the synchronous word is 0x55AA, the identification domain is invalid, and data is not received;

the scientific data pre-coding FIFO unit is used for setting related parameters of an application data FIFO and providing prog_full signals to the data storage module as a read FIFO triggering condition;

the engineering data pre-coding FIFO unit is used for setting related parameters of the engineering data FIFO and providing prog_full signals to the data storage module as a read FIFO triggering condition.

As an improvement of the above technical solution, the data storage module includes: the device comprises an RS coding management unit, a data cache unit, a FLASH control management unit and a stored data output unit; wherein,

The RS encoding management unit is used for receiving engineering data and application data cached by the data receiving module, carrying out RS error correction encoding on the effective data according to the corresponding identification signals, and caching the data to the data caching unit in a ping-pong manner;

the data caching unit is used for fixedly partitioning the SDRAM storage space, wherein partition I is used for caching engineering data; the partition II is used for caching application data and then waiting for storage scheduling to be written into the FLASH chip; the system is also used for generating a signal reflecting the state of each data buffer area;

the FLASH control management unit is used for completing the storage control of engineering data and application data and completing the logic realization of the FLASH chip bottom layer drive;

and the storage data output unit is used for carrying out RS decoding on the played back delay storage data and writing the delayed storage data into the FIFO buffer memory for carrying out output preprocessing operation.

As an improvement of the above technical solution, the data caching unit performs fixed partition on the SDRAM memory space, where partition I is used to cache engineering data; the partition II is used for caching application data and then waiting for storage scheduling to be written into the FLASH chip, and specifically comprises the following steps:

when any buffer data amount of the engineering data buffer FIFO or the application data buffer FIFO reaches a threshold value, starting corresponding buffer FIFO reading operation; at this time, if the RS encoding enabling signal is valid, RS encoding is performed on the read data and the read data is written into the asynchronous ping-pong FIFO buffer, and if the RS encoding enabling signal is invalid, the read data is directly written into the asynchronous ping-pong FIFO buffer; when data is written into the asynchronous ping-pong FIFO, the corresponding channel number is recorded.

When the data quantity of any asynchronous FIFO buffer reaches 256 x 128bits, the RS coding management unit outputs an effective corresponding asynchronous ping-pong FIFO half full signal, and outputs corresponding FIFO buffer data and channel numbers after receiving an RS coded asynchronous ping-pong FIFO read enable signal;

when the half full signal of the asynchronous ping-pong FIFO is effective, corresponding asynchronous ping-pong FIFO read operation and SDRAM write operation are started, and the coded data source packet is written into the corresponding partition cache of the SDRAM according to the channel number from the 'RS coding management' module;

when the buffer data volume of any partition of the SDRAM engineering data partition or the application data partition is full of 4 clusters, starting 1 FLASH write operation, and reading target data from SDRAM by a data buffer unit according to SDRAM read request signals and read addresses from a FLASH control management unit and writing the target data into a back-end asynchronous buffer FIFO; and the FLASH control management unit finishes reading one cluster of data of the asynchronous cache FIFO according to the signal sent by the data cache unit.

As an improvement of the technical scheme, the logic implementation of the bottom layer driving of the FLASH chip is completed, and the logic implementation specifically comprises the following steps:

generating a driving signal for FLASH memory device operation and conforming to the operation time sequence requirement; operations include reset, read, write, and erase;

Automatically loading cluster mark information and system time code information in a spare area of each used cluster of the storage area;

starting the operation aiming at the designated FLASH storage area through a software command;

automatically detecting error information in a storage area, marking error clusters and blocks, and timely notifying equipment software;

maintaining relevant information representing the operating state of the hardware, and the information can be read by software from a specific address;

automatically generating BAT reflecting the use condition of all blocks of the storage area after each power-on, and reading the BAT from a designated address by software;

and automatically managing the storage block address sent by the CPU software of the computer unit, and completing automatic access, verification and forwarding of the unused block address, the block address to be replayed, the block address to be erased, the invalid block address to be marked and the CPU read cluster address cached in the communication control module according to the storage task scheduling.

As an improvement of the above technical solution, the system further includes a data transmission module; the data transmitting module comprises: SCI receive FIFO unit, ENG receive FIFO unit, data dispatch unit and PCIe data transmission unit; wherein,

the SCI receiving FIFO unit is used for receiving the application data played back by the data storage module and performing cross-clock domain processing; setting SCI receiving FIFO related parameters, and providing prog_full signals to a data scheduling unit as a reading FIFO triggering condition;

The ENG receiving FIFO unit is used for receiving the engineering data played back by the data storage module and performing cross-clock domain processing; setting the related parameters of an ENG receiving FIFO, and providing prog_full signals to a data scheduling unit as a reading FIFO triggering condition;

the data scheduling unit is used for monitoring the prog_full signal states of the SCI receiving FIFO unit and the ENG receiving FIFO unit, setting the GPIO signal to be effective if prog_full signal is '1', and notifying CPU software to read the PCIe bus, otherwise, the GPIO output high level indicates that PCIe is unreadable; when prog_full signals of the SCI receiving FIFO unit and the ENG receiving FIFO unit are valid, the ENG receiving FIFO, namely engineering data, is preferentially read;

the PCIe data transmitting unit is used for multiplexing the same links of the data receiving module in a time division manner at a physical layer, and the transmission layer is independently arbitrated and scheduled by a PCIe IP core; after the CPU software receives that the GPIO signal is effective, a PCIe bus reading request is initiated, the satellite-borne solid-state storage system based on the PCIe bus reads the corresponding SCI receiving FIFO or ENG receiving FIFO according to scheduling, and the data is placed on the AXI bus, read by the PCIe IP core and sent to the CPU software, so that data transmission is completed.

As an improvement of the above technical solution, the system further includes a communication control module; the communication control module includes: UART communication management unit, BAT buffer memory management unit and memory address management unit; wherein,

The BAT cache management unit is used for starting the reset configuration operation of the FLASH chips, and after the reset configuration of all FLASH chips of the storage array is completed, a CPU software instruction starts the BAT organization operation;

the UART communication management unit is used for monitoring the communication state of the UART bus and receiving control information according to a UART protocol; analyzing the received serial input data based on communication constraint of command frames and data frames between CPU software and a satellite-borne solid-state storage system based on a PCIe bus, if three continuous bytes are 0xEB A90A 1, considering that a command frame head is detected, starting to receive and analyze parameters in the command frame, otherwise, judging whether the received data is 0xEB A1 or not; judging whether the accumulated sum is correct after receiving the complete command frame, if so, executing the corresponding command and returning a correct response; if not, not executing the command and returning a corresponding response; forwarding the analyzed command or state, including storage soft reset, an external data input switch, an RS coding switch, an RS decoding switch, storage initialization ending, FLASH chip reset, data transmission state, storage start block count, storage mark invalidation and storage time code, to other internal functional modules; the data query is respectively completed according to the instruction, including state query, BAT reading and data point reading, including hardware state words, BAT information and specified clusters, and is fed back to CPU software; the method is also used for accumulating and checking the received command frames, if the accumulated sum is correct, carrying out instruction analysis or starting a storage block address receiving buffer, and if the accumulated sum is incorrect, carrying out no instruction analysis, namely, carrying out no information receiving buffer such as command forwarding or storage block address and the like, and directly feeding back frame error information to CPU software;

The storage address management unit is used for writing the analyzed multiple storage new block addresses, playback block addresses and erasure block addresses into the DPRAM partition for management, and performing autonomous maintenance of the internal storage addresses according to the storage state information.

As an improvement of the above technical solution, the system further includes a clock management module; the clock management module comprises: a master clock management unit and a reset logic management unit;

the master clock management unit comprises CSU5.1.1 DCM0, inputs a clock provided for an external crystal oscillator, and outputs a clock used for SDRAM related logic and a clock used for NAND FLASH related logic;

the reset logic management unit is used for generating reset signals used by all modules, wherein the LOCKED signals output by the DCM0 are logically bonded to generate uart_rst signals for output and are only used for resetting by the communication control module; the DCM0 outputs the generated uart_rst reset signal and the UART instruction from the UART communication management unit to reset the cmd_FPGA_rst signal phase, and then generates a global reset signal sys_rst through BUFG for resetting other modules except the communication control module.

The invention also provides a PCIe bus-based satellite-borne solid-state storage method, which is realized based on the system described in one of the above, and comprises the following steps:

After the storage hardware is powered on, the space-borne solid-state storage system based on the PCIe bus automatically starts FLASH chip reset configuration operation, and after the reset configuration of all FLASH chips of the storage array is completed, a CPU software instruction starts BAT organization operation; during the period of traversing the data of all the cluster vacant areas of the storage array, corresponding Hamming decoding operation is carried out, and when the BAT information of the storage array NAND FLASH is read by the CPU, the storage system enters a conventional task management state after receiving an initialization ending command;

the data storage module monitors the state of each data cache area from the internal data cache unit, when the cache data volume of any partition of the SDRAM is full of 4 clusters, the data storage module starts 1 FLASH write operation according to task scheduling, sends SDRAM read request signals to the data cache module, and starts four-level streaming data writing;

after each stage of pipelining loads effective data, cleaning corresponding SDRAM space use identifiers; detecting the internal programming state of the storage area after programming is finished, marking the error clusters and blocks, and notifying the storage management software; if the storage fails, automatically rewriting the failed cluster data into the substitute block;

when the data storage module receives a data playback instruction, starting a read FLASH operation according to a playback address sent by the communication control module, reading corresponding data according to clusters, and sending the read corresponding data to the data storage output unit;

When the data storage module receives a data erasing instruction, the erasing operation of the FLASH block is started according to the erasing address sent by the communication control module in a four-stage pipeline.

As an improvement of the above technical solution, the method further designs an error detection and correction coding protection mechanism and a bad block management mechanism: wherein,

the error detection and correction coding protection mechanism specifically comprises the following steps:

for the data stored in the NAND FLASH main storage area, a RS coding technology with higher performance is selected, namely, the engineering data and the application data are firstly RS coded before being stored and then written into the main storage area, and when the data are replayed, RS decoding and error correction are firstly carried out and then transmitted to CPU software;

for the auxiliary information storage of each page of the spare area of NAND FLASH, a simple and reliable Hamming encoding technology is selected, namely, hamming encoding protection is carried out when file information is stored, and Hamming decoding error correction is carried out when the file information is read;

the bad block management mechanism specifically comprises:

for invalid blocks existing when NAND FLASH chips leave the factory, the invalid blocks are treated as static bad blocks and are not used any more;

for the invalid block newly added in the using process of the chip, the invalid block is taken as a dynamic bad block to be managed by software and hardware together, and the specific method comprises the following steps: for the case of programming failure, normal read operation is carried out on the page which is programmed normally in the block, but the data of the page which is programmed failed is rewritten in another effective block, and the block is marked at the same time, so that further writing or erasing of the block is avoided; for erasing the invalid block, marking the block invalid in a PCIe bus-based satellite-borne solid-state storage system, so as to avoid writing or erasing the block later; the dynamic bad blocks can be selected to be not used in future, or can be selected to be used again after storage area maintenance.

Compared with the prior art, the invention has the advantages that:

1. the data transmission rate is high, and a PCIe bus with high transmission rate is used for load data interaction;

2. the system interface is simple and highly uniform, the external data interface only adopts a PCIe bus, the types of buses are reduced, various bus protocols are not required to be configured in development, and the design complexity is reduced;

3. the system has high modularization, clear logic, definite function division, strong reusability and strong expandability.

Drawings

FIG. 1 is a functional block diagram of a PCIe bus-based on-board solid state storage system;

FIG. 2 is a block diagram of a PCIe bus-based on-board solid state storage system;

FIG. 3 is a data storage path data flow and control flow diagram;

FIG. 4 is a diagram of a call relationship between data receiving modules

FIG. 5 is a diagram of a data storage module call relationship;

FIG. 6 is a diagram of the RS code management module call relationship;

FIG. 7 is a diagram of a data cache module call relationship;

FIG. 8 is a call relationship diagram of a FLASH control management module

FIG. 9 is a diagram of a store data output module call relationship;

FIG. 10 is a schematic diagram of a four-stage pipelined write FLASH operation;

FIG. 11 is a diagram of a data transmission module call relationship;

FIG. 12 is a call relationship diagram of a computer unit communication module;

Fig. 13 is a diagram of a clock management module call relationship.

Detailed Description

The invention aims to solve the problems faced by the existing spaceborne solid state storage system, provides a design of the spaceborne solid state storage system based on a PCIe bus, and uses the PCIe bus as a unified data interface of the spaceborne solid state storage system to carry out high-speed data transmission with an upper computer CPU, so that the data transmission rate is greatly improved. AXI4 bus communication is uniformly used among the internal modules, and the speed of the AXI4 bus communication can be matched with that of a PCIe high-speed interface. In addition, the invention provides a layering, modularization and regularization design method aiming at the technical problems of complex, poor generality, difficult upgrading, difficult maintenance, high cost and the like of the existing satellite-borne solid-state storage system, wherein the specific meaning is as follows:

1) Layering: the system is divided into several modules and then each module is further divided until the modules function sufficiently well.

2) And (3) modularization: all modules have defined interfaces and functions so that they can be easily interconnected without adverse effects.

3) Regularization: the consistency of each module is pursued on the premise of not influencing the functions during design, and the universal modules can be reused so as to reduce the number of different modules.

Therefore, the standardization, the reconfigurability and the universality of the satellite-borne solid-state storage system are realized, and the development cost is reduced.

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.

Example 1

FIG. 1 is a functional block diagram of a PCIe bus-based on-board solid state storage system; as shown in FIG. 2, a structure diagram of the PCIe bus-based on-board solid-state storage system is shown. The functions of the PCIe bus-based satellite-borne solid-state storage system mainly comprise:

1) A data receiving function; receiving engineering data and application data sent by CPU software of an external main control module;

2) A data storage function; receiving data analyzed by the data receiving module and storing the data into two fixed partitions of the storage array according to the category;

3) A data transmission function; playing back the delay data in the storage module according to the CPU software instruction of the main control module and sending the delay data to the CPU software of the main control module;

4) A communication control function; the control and the state feedback of the stored related instructions are completed by communicating with the CPU software of the main control module through a serial bus;

5) A clock management function; externally input clocks are generated by DCMs into different frequency clocks needed inside the FPGA (Field Programmable Gate Array ) and global reset signals are generated.

System data flow and control flow

The data storage path data flow and control flow are shown in fig. 3, in which the curved line portion is the data flow and the broken line portion is the control flow.

Data flow:

the method comprises the steps that a PCIe bus-based satellite-borne solid-state storage system receives system engineering data and application data from external CPU software through a 1-path x4 Lane PCIe interface; and the PCIe physical layer protocol analysis is completed by adopting the PCIe special IP core provided by the Xilinx.

The method comprises the steps that a data packet format judgment is carried out on received data by a satellite-borne solid-state storage system based on a PCIe bus, if a synchronous word is 0x55AA and an identification domain is 0xED D, the data is judged to be an engineering data packet, one-time data reception is started, the one-time data reception length is 2024 bytes, and the received data is written into an engineering data FIFO for caching; if the synchronous word is 0x55AA and the identification domain is 0x6D 1D-0 x6DFD, judging that the data packet is an application data packet, starting data reception once, and writing the received data into an application data FIFO for caching, wherein the data reception length of one time is 2024 bytes; if the sync word is not 0x55AA or the sync word is 0x55AA, the identification field is invalid, and no data is received.

After the system initialization is finished, if any buffer data amount of the engineering data buffer FIFO or the application data buffer FIFO is detected to reach a threshold value (2016 x 16 bits), starting corresponding buffer FIFO read operation; at this time, if the RS (252, 256) code enable signal is valid (default code enable signal is valid), RS code is performed on the read data and written into the asynchronous ping-pong FIFO buffer, and if the RS (252, 256) code enable signal is invalid, the read data is directly written into the asynchronous ping-pong FIFO buffer; when data is written into the asynchronous ping-pong FIFO, the corresponding channel number is recorded.

When the data quantity of any asynchronous FIFO buffer reaches 256 x 128bits, outputting an effective corresponding asynchronous ping-pong FIFO half full signal, and outputting corresponding FIFO buffer data and channel numbers after receiving an RS-encoded asynchronous ping-pong FIFO read enabling signal.

The satellite-borne solid-state storage system based on the PCIe bus monitors an asynchronous ping-pong FIFO half-full signal from the 'RS code management' module, starts corresponding asynchronous ping-pong FIFO read operation and SDRAM write operation when the half-full signal is valid, and writes the coded data source packet into the corresponding partition cache of SDRAM according to the channel number from the 'RS code management' module.

The data cache module is designed with status signals reflecting the status signals of each data cache area for the data storage module to inquire; when the buffer data volume of any partition of the SDRAM platform working parameter data partition or the load scientific data partition is full of 4 clusters (4 x 4096 x 128 bits), the data storage module starts 1 FLASH write operation, and the data buffer module reads out target data from SDRAM according to the SDRAM read request signal and the read address from the FLASH control management module and writes the target data into the back-end asynchronous buffer FIFO according to the clusters. And the FLASH control management module finishes asynchronous cache FIFO one-cluster data reading according to signals, such as half full cache FIFO, cluster data reading end and the like, sent by the data cache module.

The FLASH control management module monitors the states of all data buffer areas from the internal data buffer module, when the buffer data volume of any partition of the SDRAM is full of 4 clusters (4 x 4096 x 128 bits), the data storage module starts 1 FLASH write operation according to task scheduling, sends SDRAM read request signals and read addresses to the data buffer module, and starts four-level streaming data writing.

After each stage of pipelining is loaded with effective data, cluster marking information (comprising a time code) is written into a FLASH cluster spare area, and corresponding SDRAM space use identifiers are cleaned; detecting the internal programming state of the storage area after programming is finished, marking the error clusters and blocks, and notifying CPU software; if the storage fails, the failed cluster data is automatically rewritten into the replacement block.

( FLASH pages, clusters, blocks: the FLASH storage medium is formed by stacking 4 selected FLASH modules by taking a Main storage area (Main Array) of every 8K bytes plus a Spare area (Spare Array) of 448 bytes as one Page, forming 128 pages into one Block, forming 8192 blocks into one chip Device. The chips with the same serial numbers in the 16 stacking modules in the design are regarded as a whole to simultaneously perform various operations, namely a so-called parallel expansion operation. The pages of the same address of the 16 parallel FLASH chips are regarded as a basic unit, namely a 'cluster', so that the basic storage space of the 1 'cluster' is 8K multiplied by 128bits. )

When the PCIe bus-based satellite-borne solid-state storage system is in a 'start data transmission' working mode, the storage data output module receives playback data from the FLASH control management module; when an RS (252, 256) decoding switch is turned on (a default decoding switch is turned on), the stored data output module decodes the RS while receiving the data, and writes the decoded data into a corresponding first-level cache FIFO according to a playback channel identifier; when the RS (252, 256) decoding switch is closed, writing the effective data into the corresponding first-level buffer FIFO directly according to the playback channel identification; both first level buffer FIFOs are set to 4096 x 128bits in size.

When the data quantity in any one primary cache FIFO reaches a threshold value (504 x 128 bits), and the corresponding secondary cache FIFO is valid, starting the operation of writing the read primary cache FIFO into the corresponding secondary cache FIFO; both secondary cache FIFOs are set to 512 x 128bits in size. And when the data quantity in any two-level buffer FIFO reaches a threshold value (126 times 128 bits), the engineering data or the application data is sent to a data sending module. When the on-board solid-state storage system based on the PCIe bus is in a 'stop data transmission' working mode, the first-level cache FIFO and the second-level cache FIFO are in a reset state.

The data transmission module sets 2 data receiving FIFOs to respectively buffer and store the delay engineering data and the delay application data sent by the data output module, and when the data quantity of any buffer FIFO reaches 2024 bytes, the data transmission module triggers the GPIO signal to inform CPU software to read PCIe, and sends 1 packet of delay engineering data or delay application data to the PCIe bus according to the arbitration schedule, so that playback and transmission of 1 packet of data are completed.

Control flow:

the communication module is used for controlling and monitoring the communication state of the UART bus and receiving bus data according to the UART protocol.

The communication control module analyzes the received serial input data, if the continuous three bytes are 0xEB A1, the communication control module considers that the command frame head is detected, and starts to receive and analyze parameters in the command frame, otherwise, whether the received data is 0xEB A1 is always judged.

Judging whether the accumulated sum is correct after receiving the complete command frame, if so, executing the corresponding command and returning a correct response; if not, the command is not executed and a corresponding response is returned.

The communication control module forwards the analyzed commands or states such as storage soft reset, external data input switch, RS coding switch, RS decoding switch, storage initialization ending, flash chip reset, data transmission state, storage start block count, storage mark invalidation, storage time code and the like to other internal functional modules.

Writing the analyzed multiple storage new block addresses, playback block addresses and erasure block addresses (64 blocks at most) into a DPRAM partition for management, and performing autonomous maintenance of an internal storage address according to storage state information fed back by a storage control module; the storage management software completes automatic management and distribution of the storage new block address, the playback block address and the erasure address according to the hardware status word.

And respectively completing the inquiry feedback of the hardware state word, the BAT information and the designated cluster data according to the inquiry of the storage state, the reading of the BAT (Block Assignment Table, the block allocation table) and the data point reading instruction.

The PCIe bus is successfully applied to the satellite-borne solid-state storage system, so that the effective transmission of high-speed data is realized, the problem of supporting the high-speed data by the traditional data bus is solved, and the domestic leading level is reached;

example 2

The invention provides a layering, modularization and regularization design method of a satellite-borne solid-state storage system, which realizes rapid construction and project implementation of the satellite-borne solid-state storage system, and the universality of the scheme effectively solves the problems of low system research and development efficiency, poor reusability and the like.

The CSC1 data receiving module receives engineering data and application data from CPU software through a 1-path x4 Lane PCIe data receiving interface, performs PCIe physical layer protocol analysis and data application layer protocol analysis, generates corresponding identification signals, and caches data in corresponding FIFO (first in first out) in a ping-pong manner, wherein the calling relationship is shown in figure 4.

The data receiving module comprises PCIe protocol analysis and receiving, application layer protocol analysis, scientific data (SCI) pre-coding FIFO, engineering data (ENG) pre-coding FIFO module and the like.

The PCIe protocol analysis receiving module receives engineering data and application data from external CPU software through a 1-path x4 Lane PCIe interface, and an DMA/Bridge Subsystem for PCI Express IP core provided by the exemplified Xilinx finishes PCIe physical layer protocol analysis, and the analyzed data flow is converted into 64bits of data and is written into an AXI bus.

The application layer protocol analysis module judges the data packet format of the received data:

1) If the synchronous word is 0x55AA and the identification domain is 0xED D, judging that the data is an engineering data packet, starting one-time data receiving, wherein the one-time data receiving length is 2024 bytes, and writing the received data into an engineering data FIFO for caching;

2) If the synchronous word is 0x55AA and the identification domain is 0x6D 1D-0 x6DFD, judging that the data packet is an application data packet, starting data reception once, and writing the received data into an application data FIFO for caching, wherein the data reception length of one time is 2024 bytes;

3) If the sync word is not 0x55AA or the sync word is 0x55AA, the identification field is invalid, and no data is received.

The scientific data (SCI) pre-coding FIFO module sets an application data FIFO write clock of 250MHz, a write depth of 32768 x 64, a read clock of 32MHz, a read depth of 16384 x 128, a prog_full signal threshold of 252 x 128 bits, and provides prog_full signal to the data storage module as a read FIFO trigger condition.

The engineering data (ENG) pre-coding FIFO module sets an engineering data FIFO write clock of 250MHz, a write depth of 32768 x 64, a read clock of 32MHz, a read depth of 16384 x 128, a prog_full signal threshold of 252 x 128 bits, and provides prog_full signal to the data storage module as a read FIFO trigger condition.

The CSC2 data storage module mainly realizes the coding cache of engineering data and application data received by the data receiving module, then stores the data packet into the storage array, and after receiving a playback instruction, takes out the delay data and transmits the delay data to the computer unit CPU software. The CSC2 data storage module mainly comprises four parts, namely RS coding management, a data cache module, FLASH control management and stored data output, and the calling relation is shown in figure 5.

The CSU2.1 RS code management mainly completes RS (256, 252) code protection on the received engineering data and application data. The RS coding management module receives engineering data and application data cached by the data receiving module, and transmits the data to the RS (256, 252) coding module according to the corresponding identification signals; after RS (256, 252) error correction coding is carried out on the effective data, the data are cached in a data cache FIFO in a ping-pong manner. The call relationship is shown in fig. 6.

The CSU2.2 data caching module caches the platform data and the scientific data coded by the RS through an external SDRAM chip, and then waits for the storage schedule to be written into the FLASH chip. The data caching module supports fixed partition of SDRAM storage space, wherein partition I is used for caching engineering data; partition II is used to cache application data; after the system initialization is completed, the on-board solid-state storage system based on the PCIe bus monitors the state of a data cache FIFO, and when the cache data volume reaches 256 x 128bits, the data is written into the corresponding subareas of the SDRAM for respective cache according to the data category of engineering data or application data; when the buffer data volume of any partition of the SDRAM engineering data partition or the application data partition is full of 4 clusters, 1 FLASH write operation is started, and target data are read out from SDRAM according to addresses in clusters and written into a rear-end SDRAM output buffer FIFO. The call relationship is shown in fig. 7.

The CSU2.3 FLASH control management module mainly completes the storage control of engineering data and application data and the realization of bottom driving logic of NAND FLASH chips, and comprises the following steps: 1) Generating driving signals for resetting, reading, writing, erasing and other operations of the FLASH memory device and conforming to the time sequence requirements of the FLASH memory device; 2) Automatically loading cluster mark information and system time code information in a spare area of each used cluster of the storage area; 3) The operations of resetting, writing, playback, erasing and the like aiming at the designated FLASH storage area can be started through software commands; 4) Automatically detecting error information such as programming, erasing and the like in a storage area, marking the error clusters and blocks, and timely notifying equipment software; 5) Having information related to the operating state of the hardware, and the information being readable by the software from a specific address; 6) Automatically generating a Block Allocation Table (BAT) reflecting the use condition of all blocks in the storage area after each power-up, and reading the BAT from a designated address by software; 7) The automatic management of the storage block address sent by the CPU software of the computer unit is supported, and the functions of automatic access, verification, forwarding and the like of the unused block address, the block address to be replayed, the block address to be erased, the invalid block address to be marked, the CPU read cluster address and the like cached in the communication control function are completed according to the storage task scheduling. The call relationship is shown in fig. 8.

The CSU2.4 storage data output module performs RS decoding on the played back delay storage data, writes the delay storage data into the FIFO buffer memory to perform output preprocessing operation, and the calling relationship is shown in figure 9.

And the data storage module comprises an RS coding management module, a data cache module, a FLASH control management module and the like.

After the system initialization is finished, if the RS coding management module detects that any buffer data amount of an application data buffer FIFO (CSU 1.3 SCI pre-coding FIFO) or an engineering data buffer FIFO (CSU 1.4 ENG pre-coding FIFO) reaches a threshold value (252 x 128 bits), starting corresponding buffer FIFO read operation; at this time, if the RS (252, 256) code enable signal is valid (default code enable signal is valid), RS-encoding (CSU2.2.1 RS encoder 0 to CSU2.2.16 RS encoder 15) is performed on the read data and writing into the asynchronous ping-pong FIFO buffer (SCU2.2.17 RS encoded fifo_a or SCU2.2.18 RS encoded fifo_b), and if the RS (252, 256) code enable signal is invalid, directly writing into the asynchronous ping-pong FIFO buffer (SCU2.2.17 RS encoded fifo_a or SCU2.2.18 RS encoded fifo_b) on the read data; and recording a corresponding channel identifier when the data is written into the asynchronous ping-pong FIFO.

When the buffer data amount of any asynchronous FIFO (SCU2.2.17 RS encoded FIFO_A or SCU2.2.18 RS encoded FIFO_B) reaches 256 times 128bits, outputting a valid corresponding asynchronous ping-pong FIFO half full signal, and outputting corresponding FIFO buffer data and channel numbers after receiving an RS encoded asynchronous ping-pong FIFO read enable signal.

The data caching module supports fixed partition of SDRAM storage space, wherein partition I is used for caching engineering data; partition II is used to cache application data. Designing SDRAM to support partitioning of scientific data and engineering parameters into 4 groups of caches, 4 clusters of each group, and 4K x 128bits of data quantity of each cluster.

After the system initialization is completed, the on-board solid-state storage system based on the PCIe bus monitors the state of a data receiving buffer FIFO (SCU2.2.17 RS encoded FIFO_A or SCU2.2.18 RS encoded FIFO_B) from the CSU2.1 RS encoding management module, when the buffer data amount of any FIFO reaches 256 x 128bits, corresponding asynchronous ping-pong FIFO read operation and SDRAM write operation are started, and data are written into corresponding subareas of SDRAM for respective buffer according to the data types of engineering data or application data.

The data buffer module is designed with signals reflecting the states of the data buffer areas for the CSU2.3 FLASH control management module to inquire; when the buffer data volume of any partition of the SDRAM platform engineering data partition or the application data partition is full of 4 clusters (4 x 4096 x 128 bits), the data storage module starts 1 FLASH write operation, and the data buffer module reads out target data from SDRAM according to SDRAM read request signals and read addresses from a CSU2.3 FLASH control management module and writes the target data into a back-end asynchronous buffer FIFO (CSU2.2.2 SDRAM output FIFO) according to the clusters. And the FLASH control management module finishes asynchronous cache FIFO one-cluster data reading according to signals, such as half full cache FIFO, cluster data reading end and the like, sent by the data cache module.

And the space-borne solid-state storage system based on the PCIe bus completes SDRAM bottom logic driving (CSU2.2.1 SDRAM bottom driving) according to the DDR3 SDRAM relevant IP core provided by the Xilinx, and completes operation scheduling control on SDRAM reading, writing and the like.

The FLASH control management module comprises FLASH reset configuration, an organization BAT, FLASH writing, FLASH reading, a FLASH erasing module and the like.

(1) Storage solution design

In order to improve the storage throughput rate, the data storage module adopts a four-stage pipeline operation scheme, namely, writing and erasing operations of the NAND FLASH array are carried out according to four-stage pipeline, and reading operations of NAND FLASH data are carried out according to clusters. A four stage pipeline operation schematic is shown in fig. 10.

The storage area management mechanism adopts a fixed partition storage mode: according to task requirements, two storage partitions are set, the two storage partitions are respectively stored according to data types, engineering data are stored in the engineering data area, application data are stored in the application data partition, the data of the two storage partitions (the engineering data area and the application data area) are independently and circularly stored, and after any storage area is full, the oldest partial data are automatically erased and covered with new data; during playback, the engineering data area data is played back first, and then the application data area data is played back.

(2) Storage operation mode

1) Write only mode

And recording the application data and the engineering data into the storage area without downloading playback.

2) Read-only mode

And (5) returning and downloading the delay application data and the delay engineering data in the storage area, and not storing new data.

3) Write-while-wipe mode

After the storage area is full, the mode of writing and erasing is entered, namely the data stored first is erased when new data is stored, so that the rolling storage of the storage area is realized.

4) Write-while-read mode

And supporting a playback-while-storing working mode, namely, simultaneously performing data playback operation when new data is stored.

5) Read-while-wipe mode

After the storage area is full, the mode of playback while erasing and writing is supported.

(3) Storing workflows

After the storage hardware is powered up, the on-board solid-state storage system based on the PCIe bus automatically starts FLASH chip reset configuration operation (CSU2.3.1 FLASH reset configuration), and after the reset configuration of all FLASH chips of the storage array is completed, a BAT organization operation is started by a CPU software instruction (CSU2.3.2 organization BAT). During the period of traversing the data of all the cluster free areas of the memory array, corresponding Hamming decoding operation (CSU2.3.2.1 Hamming decoding 0-CSU2.3.2.4 Hamming decoding 3) is carried out, and when the BAT information of the memory array NAND FLASH is read by the CPU, the memory system enters a conventional task management state after receiving an initialization end command.

The data storage module monitors the states of all data cache areas from the internal CSU2.2 data cache module, when the cache data volume of any partition area of the SDRAM is full of 4 clusters (4 x 4096 x 128 bits), the data storage module starts 1 FLASH write operation (CSU2.3.3 FLASH write) according to task scheduling, sends an SDRAM read request signal to the data cache module, and starts four-level streaming data writing.

After each stage of pipelining loads effective data, cleaning corresponding SDRAM space use identifiers; detecting the internal programming state of the storage area after programming is finished, marking the error clusters and blocks, and notifying the storage management software; if the storage fails, the failed cluster data is automatically rewritten into the replacement block.

When the data storage module receives the data playback instruction, according to the playback address sent by the CSC4 communication control module, a read FLASH operation (CSU2.3.4 FLASH read) is started, and corresponding data are read out according to clusters and then sent to the CSU2.4 storage data output module.

When the data storage module receives the data erasing instruction, the erasing operation (CSU2.3.5 FLASH erasing) of the FLASH blocks is started according to the erasing address sent by the CSC4 communication control module in a four-stage pipeline.

The data storage module supports data point read operations (CSU2.3.7 FLASH point read) on any cluster of main storage areas and spare areas of the FLASH during debugging.

Reliability measures taken by the data storage module:

1) Error detection and correction coding protection mechanism

Aiming at NAND FLASH bit overturn and single event overturn, an error detection and correction coding protection mechanism is designed. For the data stored in the NAND FLASH main storage area, the RS (256, 252) coding technology with higher performance is selected, namely, the engineering data and the application data are firstly subjected to RS (256, 252) coding before being stored, then written into the main storage area, and when the data are played back, firstly subjected to RS (256, 252) decoding and error correction, and then transmitted to CPU software; for the auxiliary information storage of each page of the spare area of NAND FLASH, a simple and reliable hamming coding technology is selected, namely, hamming coding protection is carried out when file information is stored, and hamming decoding error correction is carried out when the file information is read. By designing the RS (256, 252) codec and hamming codec protection mechanisms, the reliability of data storage is improved.

2) Bad block management mechanism

One of the characteristics of NAND FLASH chips is that a certain proportion of invalid blocks exist at the time of shipment, and the read operation of the invalid blocks is allowed, but the write and erase operations of the invalid blocks are avoided as much as possible. And (3) managing the factory invalid blocks, integrating the factory invalid blocks according to a test manual provided by a manufacturer and a secondary test result of a user, and treating the factory invalid blocks as static bad blocks, wherein the factory invalid blocks are not used in the future.

During the use of the chip, new invalid blocks may be generated, which is specifically shown in the case of program failure or erase failure during the programming or erasing process. The newly added invalid block is managed by software and hardware together as a dynamic bad block, and the specific method is that for the condition of programming failure, normal reading operation can be carried out on a page which is normally programmed in the block, but the data of the page which is in programming failure is rewritten in another valid block, and meanwhile, the block is marked, so that further writing or erasing of the block is avoided. For erasure of a failed block, the block is marked in the system (CSU2.3.6 FLASH marking is invalid), avoiding later writing or erasing of the block. The dynamic bad blocks can be selected to be not used in future, or can be selected to be used again after storage area maintenance.

By designing a bad block management mechanism with cooperation of software and hardware, the storage accuracy and the validity of data can be ensured. Meanwhile, the storage management designs a wear-leveling mechanism to reduce the probability of dynamic bad block generation as much as possible.

When the FPGA is in a 'start data transmission' working mode, the CSU2.4 storage data output module receives delay data played back by the CSU2.3 FLASH control management module; when an RS (252, 256) decoding switch is turned on (a default decoding switch is turned on), the data output sub-module carries out RS decoding while receiving data, and writes the decoded data into a ping-pong FIFO buffer; when the RS (252, 256) decoding switch is closed, the valid data is directly written into the ping-pong FIFO buffer; the two FIFOs of the ping-pong buffer are both set to 8192 x 128 bits; when any ping-pong FIFO is not empty and the receiving FIFO of the type corresponding to the back-end CSC3 data transmitting module is not full, the FIFO corresponding to the CSU2.4 stored data output module is read, and then the data is transmitted to the CSC3 data transmitting module.

The data transmitting module mainly transmits the delay data played back by the data storage module to CARP CPU software. The data transmission module reads data in the corresponding FIFO after arbitration and transmits the playback data to the CPU software of the computer unit through a PCIe transmission interface according to the monitored buffer states of the playback engineering data FIFO and the playback application data FIFO through the same 1-path x4 Lane PCIe link in the physical layer time division multiplexing data receiving module, so that the transmission of the playback data is completed. The call relationship is shown in fig. 11.

The data transmission module comprises an SCI receiving FIFO, an ENG receiving FIFO, a data scheduling module, a PCIe data transmission module and the like.

The SCI receiving FIFO module is used for receiving the application data played back by the CSC2 data storage module and performing cross-clock domain processing.

Setting a SCI receiving FIFO write clock 32MHz, a write depth of 8192 x 128, a read clock 250MHz, a read depth of 16384 x 64, a prog_full signal threshold of 253 x 64 bits (1 packet of data), and providing prog_full signal to a CSU3.3 data scheduling module as a read FIFO trigger condition.

The ENG receiving FIFO module is used for receiving the engineering data played back by the CSC2 data storage module and performing cross-clock domain processing.

Setting an ENG receiving FIFO write clock of 32MHz, a write depth of 8192 x 128, a read clock of 250MHz, a read depth of 16384 x 64, a prog_full signal threshold of 253 x 64 bits (1 packet of data), and providing prog_full signals to a CSU3.3 data scheduling module as a read FIFO trigger condition.

The data scheduling module monitors the prog_full signal states of the CSU3.1 SCI receiving FIFO and the CSU3.2 ENG receiving FIFO, if the prog_full signal is '1', the GPIO signal is set to be effective, the CPU software is informed to read the PCIe bus, and otherwise, the GPIO output high level indicates that PCIe is unreadable.

When the prog_full signals of both the CSU3.1 SCI receive FIFO and the CSU3.2 ENG receive FIFO are valid, the ENG receive FIFO, i.e., the engineering data, is preferentially read.

And the PCIe data transmission module is used for multiplexing 1-path x4 Lane PCIe links which are the same as the CSC1 data receiving module in a physical layer time division manner, and the transmission layer is independently arbitrated and scheduled by the PCIe IP core.

After the CPU software receives that the GPIO signal is effective, a PCIe bus reading request is initiated, the satellite-borne solid-state storage system based on the PCIe bus reads the corresponding SCI receiving FIFO or ENG receiving FIFO according to scheduling, and the data is placed on the AXI bus, read by the PCIe IP core and sent to the CPU software, so that data transmission is completed.

The CSC4 communication control module receives UART protocol data from computer unit CPU software through a UART bus and finishes analysis of UART protocol and command forwarding; buffering the addresses of the storage blocks sent by the CPU software, and respectively buffering the addresses of unused block addresses, addresses of blocks to be played back, addresses of blocks to be erased and the like into different storage spaces of the DPRAM; latching control information such as time code information, RS coding on/off instructions, RS decoding on/off instructions, storage soft reset instructions and the like sent by a computer unit; and organizing and storing the state information such as hardware state word information, BAT table information and the like, organizing data frames according to a UART protocol, and sending the data frames to CPU software to complete data interaction. The call relationship is shown in fig. 12.

The communication control module comprises UART communication management, BAT buffer management, storage address management module and the like.

After the storage hardware is powered up, the BAT cache management module automatically starts FLASH chip reset configuration operation (CSU2.3.1 FLASH reset configuration) based on the PCIe bus on-board solid-state storage system, and after the reset configuration of all FLASH chips of the storage array is completed, a CPU software instruction starts BAT organization operation (CSU2.3.2 to organize BAT).

The UART communication management module monitors the communication state of the UART bus, receives control information according to a UART protocol, and the communication constraint of command frames and data frames between CPU software and a PCIe bus-based satellite-borne solid-state storage system is detailed in the 6-section CSCI data.

The UART communication management module analyzes the received serial input data, if the continuous three bytes are 0xEB A1, the UART communication management module considers that the command frame head is detected, the parameters in the command frame are received and analyzed, otherwise, whether the received data is 0xEB A1 or not is always judged; judging whether the accumulated sum is correct after receiving the complete command frame, if so, executing the corresponding command and returning a correct response; if not, the command is not executed and a corresponding response is returned.

The UART communication management module transmits the analyzed commands or states such as storage soft reset, external data input switch, RS coding switch, RS decoding switch, storage initialization ending, flash chip reset, data transmission state, storage start block count, storage mark invalidation, storage time code and the like to other internal functional modules.

And the UART communication management module respectively finishes data query feedback of hardware status words, BAT information, designated clusters and the like to CPU software according to the instructions of status query, BAT reading, data point reading and the like.

When the BAT is organized in a scanning storage area, 1 BAT item is organized, and 1 BAT item writing CSU4.1.1 BAT cache DPRAM operation is started in the space-borne solid-state storage system based on the PCIe bus. After the BAT items with the required length are organized according to the CPU software instructions, the CPU software starts the BAT item reading operation, and the BAT buffer management module reads out the corresponding BAT items in the CSU4.1.1 BAT buffer DPRAM according to the CPU software instructions and sends the corresponding BAT items to the CPU software, and the operation is repeated until all the BAT items are read out, and then the hardware initialization operation of the storage area is completed.

The storage address management module writes the analyzed multiple storage new block addresses, playback block addresses and erasure block addresses (64 blocks at most) into the DPRAM partition for management, and performs autonomous maintenance of the internal storage addresses according to the storage state information fed back by the storage control module; and the CPU software of the computer unit completes the automatic management and issuing of the storage new block address, the playback block address and the erasing address of the spaceborne solid-state storage system based on the PCIe bus according to the storage hardware status word.

And the UART communication management module performs accumulation and verification on the received command frames, if the accumulation and the accumulation are correct, the instruction analysis is performed or the storage block address receiving cache is started, and if the accumulation and the accumulation are incorrect, the instruction analysis is not performed, namely the command forwarding or the information receiving cache such as the storage block address and the like is not performed, and the frame error information is directly fed back to the CPU software.

When the CSU4.2 UART communication management module receives a command frame of 0x33 storage address management, the state machine jumps to a state of receiving a data frame, a waiting time threshold is set to 20ms in a waiting process (if the host does not receive response data sent by the slave in a set time (20 us to 15 ms), the signal on the channel is considered to be failed in transmission this time), if the valid data frame is not received after timeout, the receiving process of the data frame is automatically received, and frame error information is fed back to CPU software. If the effective data frame is received, the respective DPRAM pointers of the current two channels are firstly latched, then the received storage block address information is written into the DPRAM, and after the data reception is completed, the accumulation and the verification of the data frame are carried out. If the check is passed, the data frame receiving process is ended, if the check is not passed, the DPRAM is restored to the state before the receiving process by using a pre-latched pointer, and the invalid data just received is equivalently erased.

The CSC5 clock management module generates a 200MHz clock signal from an input 100MHz clock signal as an SDRAM logic clock, and generates a 32MHz clock signal as a storage logic clock; processing a Locked signal generated by the DCM and then using the processed signal as a system global reset signal; and supports setting of the CPU status register as a system soft reset signal. The call relationship is shown in fig. 13.

The clock management module comprises a master control clock management module, a reset logic management module and the like.

The master clock management module mainly comprises CSU5.1.1 DCM0, inputs a 100MHz clock provided for an external crystal oscillator, and outputs a 200MHz clock used for SDRAM related logic and a 32MHz clock used for NAND FLASH related logic.

The reset logic management module generates a reset signal used by the communication control module and reset signals used by other modules.

After the LOCKED signal output by the DCM0 is logically bonded, a uart_rst signal is generated and output, and the uart_rst signal is only used for resetting the communication control module.

The DCM0 outputs a generated uart_rst reset signal and a UART instruction from the communication management module to reset a cmd_FPGA_rst signal phase, and then generates a global reset signal sys_rst through BUFG for resetting other modules except the communication control module.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims

1. A PCIe bus-based on-board solid state storage system for use in storage hardware, the system comprising: a data receiving module and a data storage module; wherein,

the data storage module adopts a fixed partition storage mode, performs independent cyclic storage on data according to data types, and takes out delay data to be transmitted to CPU software of a computer unit after receiving a playback instruction;

the data receiving module comprises: the system comprises a PCIe protocol analysis receiving unit, an application layer protocol analysis unit, a scientific data pre-coding FIFO unit and an engineering data pre-coding FIFO unit; wherein,

2. The PCIe bus-based on-board solid state storage system of claim 1 wherein the data storage module comprises: the device comprises an RS coding management unit, a data cache unit, a FLASH control management unit and a stored data output unit; wherein,

3. The PCIe bus-based on-board solid state memory system according to claim 2 wherein the data caching unit is configured to cache engineering data by fixedly partitioning SDRAM memory space, wherein partition I is configured to cache engineering data; the partition II is used for caching application data and then waiting for storage scheduling to be written into the FLASH chip, and specifically comprises the following steps:

when any buffer data amount of the engineering data buffer FIFO or the application data buffer FIFO reaches a threshold value, starting corresponding buffer FIFO reading operation; at this time, if the RS encoding enabling signal is valid, RS encoding is performed on the read data and the read data is written into the asynchronous ping-pong FIFO buffer, and if the RS encoding enabling signal is invalid, the read data is directly written into the asynchronous ping-pong FIFO buffer; recording a corresponding channel number when data is written into the asynchronous ping-pong FIFO;

4. The PCIe bus-based on-board solid state storage system according to claim 2, wherein the completing the logic implementation of the FLASH chip bottom layer driver specifically includes:

5. The PCIe bus-based on-board solid state storage system of claim 1 wherein the system further comprises a data transmission module; the data transmitting module comprises: SCI receive FIFO unit, ENG receive FIFO unit, data dispatch unit and PCIe data transmission unit; wherein,

6. The PCIe bus-based on-board solid state storage system of claim 1 wherein the system further comprises a communication control module; the communication control module includes: UART communication management unit, BAT buffer memory management unit and memory address management unit; wherein,

the UART communication management unit is used for monitoring the communication state of the UART bus and receiving control information according to a UART protocol; analyzing the received serial input data based on communication constraint of command frames and data frames between CPU software and a satellite-borne solid-state storage system based on a PCIe bus, if three continuous bytes are 0xEB A90A 1, considering that a command frame head is detected, starting to receive and analyze parameters in the command frame, otherwise, judging whether the received data is 0xEB A1 or not; judging whether the accumulated sum is correct after receiving the complete command frame, if so, executing the corresponding command and returning a correct response; if not, not executing the command and returning a corresponding response; forwarding the analyzed command or state, including storage soft reset, an external data input switch, an RS coding switch, an RS decoding switch, storage initialization ending, FLASH chip reset, data transmission state, storage start block count, storage mark invalidation and storage time code, to other internal functional modules; the data query is respectively completed according to the instruction, including state query, BAT reading and data point reading, including hardware state words, BAT information and specified clusters, and is fed back to CPU software; the method is also used for accumulating and checking the received command frames, if the accumulated sum is correct, carrying out instruction analysis or starting the storage block address receiving buffer, and if the accumulated sum is incorrect, not carrying out instruction analysis, namely not carrying out command forwarding or storage block address information receiving buffer, and directly feeding back frame error information to CPU software;

7. The PCIe bus-based on-board solid state storage system of claim 6 wherein the system further comprises a clock management module; the clock management module comprises: a master clock management unit and a reset logic management unit;

the master clock management unit comprises CSU5.1.1 DCM0, inputs a clock provided for an external crystal oscillator, and outputs a clock used for SDRAM related logic and a clock used for FLASH related logic;

8. A PCIe bus based on-board solid state storage method implemented based on the system of one of claims 2-7, the method comprising:

after the storage hardware is powered on, the space-borne solid-state storage system based on the PCIe bus automatically starts FLASH chip reset configuration operation, and after the reset configuration of all FLASH chips of the storage array is completed, a CPU software instruction starts BAT organization operation; during the period of traversing the data of all the cluster vacant areas of the storage array, corresponding Hamming decoding operation is carried out, and when BAT information of the storage array FLASH is read by the CPU, the storage system enters a conventional task management state after receiving an initialization ending command;

9. The PCIe bus-based on-board solid state storage method of claim 8, wherein the method further designs an error detection and correction coding protection mechanism and a bad block management mechanism: wherein,

for the data stored in the FLASH main storage area, the RS coding technology with higher performance is selected, namely, the engineering data and the application data are firstly RS coded before being stored and then written into the main storage area, and when the data are replayed, the RS decoding error correction is firstly carried out and then transmitted to the CPU software;

for auxiliary information storage of each page of spare area of FLASH, a simple and reliable Hamming coding technology is selected, namely, hamming coding protection is carried out when file information is stored, and Hamming decoding error correction is carried out when the file information is read;

the bad block management mechanism specifically comprises:

For invalid blocks existing when the FLASH chip leaves the factory, the FLASH chip is treated as a static bad block and is not used any more;