CN115665574A - Novel pixel circuit and noise reduction method - Google Patents

Abstract

The invention discloses a novel pixel circuit and a noise reduction method, relates to photoelectric detection and imaging, and aims to solve the problem of incompatibility of global exposure and column level CDS in the prior art. Including an auxiliary pixel P disposed beside the APS array _G (ii) a Auxiliary pixel P _G The production process and the circuit structure of the APS are the same as those of any APS; at the auxiliary pixel P _G One or more layers of shading masks are arranged on the top; using auxiliary pixels P _G Spatial double sampling and analog and digital signal processing are performed. The pixel has the advantages of high working speed and no limitation on the size of the suspended diffusion capacitor. The array level can realize global exposure, firstly output analog voltage is changed into quantity irrelevant to temperature by adopting a space double sampling technology, FPN caused by dark current can also be reduced to a certain extent, and then the FPN is further eliminated by an image processing method in a digital signal stage. Compared with the traditional active pixel circuit, the pixel circuit has lower noise, higher sensitivity, wider dynamic range and higher speed.

Description

Novel pixel circuit and noise reduction method

Technical Field

The present invention relates to optoelectronic technologies, and in particular, to a novel pixel circuit and a noise reduction method.

Background

At present, most image Sensor chips based on the CMOS process adopt an Active Pixel Sensor (APS) circuit, which has bottlenecks in sensitivity, dynamic range, speed, and the like, and cannot meet the continuously emerging requirements of new applications. In addition, the conventional APS array does not have a good compromise between global exposure and column-level Correlated Double Sampling (CDS). Although some of the existing designs use an in-pixel CDS approach to achieve the combination of both, this can greatly increase the complexity of the pixel circuitry, resulting in a reduction in both the fill factor of the pixel and the resolution of the array.

The active pixel sensor APS is a basic unit of an image sensor chip, and images are formed based on an array of pixel cells each having a photosensitive cell and a plurality of transistors. Among them, the photosensitive cell has the function of realizing photoelectric conversion and converting incident photons into electrons, and a typical current photosensitive cell design is a Pinned Photodiode (PPD). The transistors are used as switches to reset, transmit and select signals and as amplifying devices to amplify signals, and the transistors in the APS are typically Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The active pixel sensor is proposed to solve the disadvantages of large noise, narrow dynamic range, low sensitivity of the passive pixel circuit, and the need to amplify signals outside the array.

The most widely used active pixel circuit at present is a four-transistor structure, called 4T-APS, whose circuit principle and structure are shown in fig. 1 and fig. 2, respectively. The 4T-APS operates on the principle that the reset switch Trst and the transmission gate TX are opened first, and the diffusion capacitor C is suspended _FD Junction capacitance C with PPD _PD The upper voltage is charged to a reset voltage Vrst, and Trst and TX are turned off after the reset is completed. The pixel then begins exposure to light, and the PPD creates photo-generated charges under the light, which electrons and holes move toward the cathode and anode, respectively, to recombine with the reset charges, with the longer the exposure time the more charge recombines. TX is turned on for the second time after exposure is completed, at this time C _PD The charge on, in particular an electron, is directed towards C _FD Transferring to thereby convert C _PD Change of charge to C _FD The voltage on the capacitor changes. Because of C _FD Are generally small, according to V = Q/C, C _FD Will be greater than C _PD The voltage changes, so that the conversion and amplification from photo-generated charges to voltage signals are realized, and the TX is turned off after the conversion is finished. And finally, reading out a voltage signal through a selection switch Tsel, wherein Tsf forms a voltage follower and plays a role of buffer isolation in a circuit. The operation timing diagram of 4T-APS is shown in FIG. 3.

Any solution for converting an electro-optic signal on a pixel sensor array plane suffers from Fixed Pattern Noise (FPN) generated by non-uniform fabrication of the conversion array plane, and the mechanism for generating such Noise on the conversion array plane is not exactly the same for different solutions. Due to the influence of fixed pattern noise, the sensor array can also output a fixed and unchangeable pattern signal under the condition of no light signal irradiation; in the case of optical image illumination, this fixed pattern signal is superimposed on the real image signal. The reason for FPN is the inconsistency in pixel element parameter performance at different coordinate locations across the array. For CMOS image sensor arrays employing APS, the sources of fixed pattern noise mainly include: the active transistor on voltages Vth do not coincide, the transistor on resistances Ron as switches do not coincide, the thermal noise 4KTRon caused by the Ron disparity, the dark current Idark of the photodiode (i.e., the reverse current generated by the photodiode in the case where there is no light at all), and the like. As can be seen from the expression of thermal noise (common general knowledge), FPN is also affected by temperature, and when the temperature of the environment in which the sensor array is located is different, FPN is also different, and increases with increasing temperature.

The main method for eliminating FPN is to use CDS technology, namely, for 4T-APS, C at different time _FD The voltage is sampled twice, then the difference is made to the sampled voltage, and the final output signal is the voltage variation between the two pure sampling moments after the FPN is filtered. Considering the problems of speed and circuit complexity together, the current array basically adopts a row scanning column reading mode, i.e. a column of pixels shares a load current source and a CDS circuit, but the CDS circuit only serves one pixel in one column at the same time, and the CDS circuit is called column level CDS. A schematic diagram of the column level CDS circuit of the 4T-APS is shown in fig. 4. The operation timing diagram of the CDS readout circuit of the 4T-APS array is shown in FIG. 5. When reset is completed, tsel is turned on, but guaranteed at T _SC And is turned off before being turned on. After Tsel turns on, turn on T before TX turns on for the second time _S1 At this time, C can be put _FD The reset voltage on is sampled as the first sampling voltage and stored to C _S1 Turning off T after the first sampling _S1 . T may be turned on after TX is turned on and off for a second time _S2 Will then be C _FD The voltage on is stored as a second sampled voltage to C _S2 And turn off T after sampling is completed _S2 . Finally, T is opened simultaneously _SC1 、T _SC2 And respectively sending the two sampling voltages to the in-phase end and the anti-phase end of the differential amplification circuit for difference and amplification, thereby obtaining an output signal subjected to noise reduction.

Besides FPN, another major factor affecting image quality is image lag, i.e. the information reflected at different locations on the image does not come from the same time instant, which must be avoided for some application scenarios. Therefore, for the pixel array, a global exposure mode is adopted, and for 4T-APS, namely Reset and TX signals of the whole array are completely synchronized before the arrival of the Select signal, image information of different spatial positions is stored in C at the same time _FD Then, the readout is sequentially selected by the Select signal for subsequent processing. In the global exposure mode, the image information obtained by each pixel comes from the same time, so that image lag does not occur. The timing diagram for a 4T-APS array to achieve global exposure is shown in FIG. 6, where Texp is the exposure time, trow is the time for a row of pixels to be fully read out, and x represents the row currently being read out by the array. As can be seen from the principle of global exposure, the column-level circuit cannot implement CDS because one CDS circuit can only process C of one pixel at the same time _FD Sampling is performed. The reset operation of the global exposure is all array-wide, so that it is not possible to perform the first sampling using the column-level CDS, i.e., to read out and store the reset voltage Vrst of all pixels at the same time.

As previously mentioned, global exposure is incompatible with column level CDS, although some circuits have adopted the scheme of intra-pixel CDS, i.e. one CDS circuit is integrated within each pixel to ensure that each CDS circuit serves one pixel individually. This can greatly increase the pixel circuit complexity and can cause degradation in other aspects of the pixel, such as fill factor and spatial resolution.

Summarizing, the disadvantages of the prior art:

1. because of the limitations of the photosensitive element and the exposure mode, the existing indexes such as the sensitivity and the dynamic range (the sensitivity refers to the conversion gain when an optical signal is converted into an electrical signal, and the dynamic range refers to the range between the weakest light and the strongest light which can be detected) of the 4T-APS all reach the bottleneck, although the indexes can be slightly improved by the optimization process, the structure cannot meet some newly emerging application requirements.

2. The existing 4T-APS circuit uses the redistribution of photo-generated charges between the photodiode junction capacitance and the floating diffusion capacitance to achieve photoelectric conversion and signal amplification. However, the photo-generated current of the photodiode is small, so the speed of accumulating charges is slow, and if a higher gain, i.e. a higher sensitivity, is desired, the pixel exposure time is long. The main problem with this pixel circuit is therefore the slow operating speed, which affects the complexity of the array back-end circuit and the frame rate of the readout.

3. The existing 4T-APS is a suspended diffusion capacitor C because of the requirement of sensitivity _FD Must be much smaller than the junction capacitance C of the photodiode _PD But small C _FD Increases the reset noise of the pixel (the noise generated by the Ron of Trst and the associated capacitance at each reset operation is proportional to KT/C, K being the boltzmann constant, T being the temperature, C being the capacitance).

4. The existing active pixel sensor array cannot realize the combination of global exposure and column-level correlated double sampling, so that the existing active pixel sensor array cannot be applied to scenes with high requirements on image tailing and fixed pattern noise.

Prior publications of related art: CN112510058A, PD-photodiode.

Disclosure of Invention

The present invention is directed to a novel pixel circuit and a noise reduction method, so as to solve the problems of the prior art.

The novel pixel circuit comprises: the APS array, the pixel reading unit and the digital processing unit;

further comprising an auxiliary pixel P disposed beside the APS array _G (ii) a What is needed isThe auxiliary pixel P _G The production process and the circuit structure of the APS array are the same as those of any APS in the APS array, and a 4T-APS structure is adopted; at the auxiliary pixel P _G One or more layers of shading masks are arranged on the top;

the pixel reading unit is used for reading the pixel voltage of the APS array pixel by pixel and reading the auxiliary pixel P at the same time of reading the pixel voltage of the APS array each time _G The two voltages are subjected to difference and amplification and then input to the digital processing unit through an ADC;

and the digital processing unit stores the received digital quantization values one by one corresponding to the positions in the APS array to obtain array data with the FPN removed.

Pixels and auxiliary pixels P of the APS array _G PD-MOS is used as the photosensitive element.

And the digital processing unit presets a fixed noise template of the APS array, and the fixed noise template is subtracted from the array data subjected to FPN removal at the pixel reading unit to obtain the final array data subjected to noise reduction.

The fixed noise template is obtained by the following steps: placing the APS array in a dark environment; the pixel reading unit reads pixel voltages of the APS array pixel by pixel, and reads the auxiliary pixel P while reading the APS array pixel voltages each time _G The two voltages are subjected to difference and amplification and then are input into the digital processing unit through the ADC; and the digital processing unit stores the received digital quantization values one by one corresponding to the positions in the APS array to obtain the fixed noise template.

And the digital processing unit updates or resets the fixed noise template according to a user instruction.

The pixel reading unit at least comprises three operational amplifiers and four resistors;

the non-inverting terminal of the operational amplifier OPA1 is externally connected with the auxiliary pixel P _G The inverting terminal of the operational amplifier OPA1 is connected to the output terminal of the operational amplifier OPA1, and the output terminal of the operational amplifier OPA1 is grounded after passing through the resistor R2 and the resistor R3 in sequence;

the in-phase end of the operational amplifier OPA2 is externally connected with the voltage output end of the APS array, the inverting end of the operational amplifier OPA2 is connected with the output end of the operational amplifier OPA2, and the output end of the operational amplifier OPA2 is connected with the input end of the ADC after sequentially passing through a resistor R1 and a resistor R4;

the in-phase end of the operational amplifier OPA3 is connected with the connection point of the resistor R2 and the resistor R3, the inverting end of the operational amplifier OPA3 is connected with the connection point of the resistor R1 and the resistor R4, and the output end of the operational amplifier OPA3 is connected with the input end of the ADC;

and, let the resistance ratio R3/R2= R4/R1= β, where β is the amplification factor of the pixel reading unit.

The noise reduction method of the invention utilizes the novel pixel circuit to reduce noise.

The novel pixel circuit and the noise reduction method have the advantages that the novel exposure mode is adopted to improve the working speed of the pixel, meanwhile, the size of the suspended diffusion capacitor is not limited any more, and C can be supplied to the pixel circuit under the condition of allowable area _FD Additional capacitance is connected in parallel to reduce reset noise. The array level firstly determines that the array level can realize global exposure based on the 4T-APS architecture; for the elimination of FPN, the output analog voltage is first changed to a temperature-independent amount using a spatial double sampling technique, and also FPN caused by dark current can be reduced to some extent, and then FPN is further eliminated by an image processing method at a digital signal stage. Lower noise, higher sensitivity, wider dynamic range and faster speed than conventional active pixel circuits. The spatial double sampling scheme achieves the combination of global exposure and filtering of fixed pattern noise.

Drawings

FIG. 1 is a circuit schematic of a 4T-APS of the prior art;

FIG. 2 is a schematic diagram of a 4T-APS structure in the prior art;

FIG. 3 is a timing diagram of a 4T-APS of the prior art;

fig. 4 is a circuit schematic diagram of a 4T-APS column level CDS in the prior art;

FIG. 5 is a timing diagram of a CDS readout circuit of a 4T-APS array in the prior art;

FIG. 6 is a timing diagram of a prior art 4T-APS array for global exposure;

FIG. 7 is a schematic diagram of a novel pixel circuit according to the present invention;

FIG. 8 is a schematic circuit diagram of the PD-MOS 4T-APS of the present invention;

FIG. 9 is a schematic diagram of the PD-MOS 4T-APS structure of the present invention;

FIG. 10 is a timing diagram of the PD-MOS 4T-APS in the present invention;

FIG. 11 is a timing diagram of global exposure of the PD-MOS 4T-APS array in accordance with the present invention;

FIG. 12 is a schematic circuit diagram of the phase of performing spatial double sampling on analog signals by the PD-MOS 4T-APS according to the present invention;

FIG. 13 is a timing diagram of the PD-MOS 4T-APS performing spatially double sampling of analog signals in accordance with the present invention;

fig. 14 is a schematic diagram of the working principle of the PD-MOS 4T-APS performing the phase of spatially double sampling digital signals according to the present invention.

Detailed Description

The noise reduction method is realized by utilizing the novel pixel circuit under the specific working requirement.

The specific structure and operation principle of the novel pixel circuit of the present invention are shown in fig. 7 to 14.

In this embodiment, based on the conventional 4T-APS architecture, the photosensitive element employs a novel photoelectric conversion device PD-MOS, which indirectly converts incident light into drain-source current of MOSFET by utilizing the photo-induced substrate bias effect, and has better sensitivity and dynamic range than the conventional photodiode, which is described in the document with publication number CN 112510058A. The PD-MOS is only a preferred option and should not be taken as a specific limitation for the selection of the photosensitive element of the present invention.

Fig. 8 and fig. 9 are a device structure diagram and an equivalent circuit diagram of a PD-MOS, respectively, holes generated by a reverse biased PD under an illumination condition are diffused to a substrate of an adjacent MOS transistor through an anode, and a drain-source current is further changed by changing a substrate voltage to change a threshold voltage of the MOS transistor. When illumination is different, drain-source current is different, so the PD-MOS is actually a light-controlled current source. In addition, the device can adjust the gain by controlling the grid voltage of the MOS tube. Thus, a novel pixel PD-MOS 4T-APS is formed, in which the output signal can fully inherit the characteristics of the PD-MOS, and therefore, the pixel can obtain high sensitivity and wide dynamic range.

Since the substrate voltage of the PD-MOS varies with the illumination, it should be isolated from the substrates of other transistors, which is achieved here using a deep N-well (DNW) process. The drain electrode of the PD-MOS is connected to the left end of the transmission gate, the source electrode is grounded, and the pixel circuit works in three stages of resetting, integrating and reading. The reset, i.e. the turn-on of Trst, is first performed to charge the FD point voltage to a fixed value, a process similar to 4T-APS, but where the transfer gate Ttx is guaranteed to be closed. After the reset is completed, ttx can be turned on to utilize the drain-source current pair C of the PD-MOS _FD The integration is performed, i.e. it is discharged. Because the drain-source current of the PD-MOS is different under different illumination, the discharge degree is also different. At C _FD Ttx is turned off before the charge stored in it is discharged, at which time V _FD When the voltage value is stabilized to a certain voltage value, the voltage is different when the illumination is different, and the integration process is the process of pixel exposure. Finally, V is paired through TSel according to time sequence _FD The readout is performed, and the operation timing chart of the entire pixel internal circuit is shown in fig. 10.

The integration process, i.e. the exposure, is completely different from the conventional APS exposure, and the exposure time is much shorter than that of the conventional APS exposure, so that the novel APS exposure determines that the pixel can have a fast operating speed. Because of the extremely high response speed of a single pixel, the array can adopt a mode of row scanning and parallel column reading, namely, a column selection switch is added to each column, all columns share a back-end processing circuit, and the output voltage of a certain pixel in the current column is selected and transmitted by controlling the column selection switch in a time sequence mode. This approach would greatly reduce the complexity of the back-end analog circuitry, allowing more pixels to be integrated in the same area, i.e., increasing the resolution of the array. Furthermore, this high speed feature also increases the array readout frame rate.

Because of exposure toDifference in light pattern, C _FD Is no longer limited by the sensitivity requirements, C can be increased by process tuning _FD Thereby reducing reset noise.

On the array level, the PD-MOS 4T-APS-based array can realize global exposure, and the principle of the array is the same as that of the traditional APS array, namely, the opening time of all pixels Trst of the array is synchronous, the opening time of Ttx is synchronous, and then Tsel is sequentially opened to read out voltage signals. The timing diagram is shown in fig. 11.

And removing fixed pattern noise on the basis of realizing global exposure by adopting a space double-sampling mode. The method is divided into an analog processing stage and a digital processing stage.

And (3) a simulation treatment stage: the schematic diagram is shown in FIG. 12, wherein P _A Representing a pixel, P, within an APS array _G The auxiliary pixel which is manufactured at the adjacent position of the APS array and has the same process with the pixel in the APS array is manufactured, but the auxiliary pixel needs to be subjected to shading treatment. Since the light shielding process is performed, the output voltage of the auxiliary pixel is caused only by the dark current of the PD-MOS at any time. In addition, the auxiliary pixel P _G Reset and TX timing of and pixel P _A Identical, but different in Select timing. Auxiliary pixel P when the Select signal of each pixel in APS array comes _G Tsel of (a) is turned on once, i.e. how many pixels P of the APS array _A Auxiliary pixel P _G How many pulses the Select signal has in a cycle. Vout0 is the auxiliary pixel P _G An output completely affected by the dark current of the PD-MOS, that is, background noise of the pixel; vout1 is the output of the pixels of the APS array under illumination. The operational amplifier OPA1 and the operational amplifier OPA2 are two voltage followers, play a role in buffering and isolating, and avoid the influence of a back-end circuit on output signals. The resistor R1, the resistor R2, the resistor R3, the resistor R4 and the operational amplifier OPA3 form a difference calculating circuit; if the resistance ratio R3/R2= R4/R1= β, where β is the amplification factor of the pixel reading unit, there is Vout = β · (Vout 1-Vout 0), so that different amplification factors can be obtained by adjusting the resistance value. Timing diagram of operation of spatial double-sampling analog-end circuit is shown in FIG. 13Shown in the figure. Since only one pixel in the APS array is taken as an example here, P _G And P _A The same signal is obtained from the selection, and those skilled in the art can clearly understand that there are N P in the above technical analysis _A Only need to put P in the timing chart _G Set the frequency of the Select signal to P _A Is N times. The main function is to filter background noise caused by dark current in APS array, although P _G And P _A The noise caused by the dark current is not exactly the same, but this way will improve the effect of the noise caused by the dark current well for the case of large dark current. In addition to reducing the effect of dark current, the temperature dependence of noise in the output signal after differencing is weak because P _G And P _A In exactly the same temperature environment. After the difference is found, the difference between the noise (reset noise and thermal noise) related to the temperature is almost only related to the deviation of the process parameters such as the load capacitance and the on-resistance, and is basically not related to the temperature change. After the dynamic part of the noise is substantially solved, the remaining noise in the output signal can be approximated as a fixed noise, which can be solved in the digital processing stage.

A digital processing stage: the signal processed in the analog processing stage can be sent to an ADC to obtain digital quantized values corresponding to different output voltages, wherein the quantized values comprise residual fixed noise after the analog end processing. The fixed noise template of the APS array is obtained once and pre-stored in the digital processing unit after the circuit is fixed on the circuit board or each APS is fixed on the chip. And obtaining array data after analog processing in each subsequent time, and then subtracting the fixed noise template to obtain a final denoising array signal.

In order to obtain the fixed noise template, the whole APS array can be placed in a completely dark environment, the temperature factor is weakened by the analog processing mode, the output digital signal is completely caused by fixed noise, the fixed noise can not change along with the change of the external environment and time completely for a sensor array prepared and processed by adopting a stable process, and the output digital signal can not change. Therefore, the image information of the frame under the dark condition can be used as a template to be stored, and the purpose of filtering fixed noise can be achieved by subtracting the information of the frame when each frame of image is processed subsequently.

To demonstrate the effect of the fixed noise template, the theoretical situation is shown in fig. 14. When uniform light is irradiated onto the APS array, and processed by the pixel reading unit and the ADC, the obtained ideal image information should be the same gray scale value of each pixel. However, in the image information obtained by the presence of the stationary noise, as shown in fig. 14 (a), the gradation values of the respective pixels do not completely match. FIG. 14 (b) shows the fixed noise template, wherein a _mn Represents the output noise caused by the fixed deviation of PA and PG under dark condition, and n and m represent the row and column numbers of the pixels respectively. While fig. 14 (c) is the output image after being processed by the digital processing unit, although the noise can not be filtered by hundreds percent, the noise reduction effect will be obvious.

In some special cases, for example, when the fixed noise template is initially manufactured, the shading effect is poor, and other subsequent physical factors cause a physical change of a certain pixel, and the denoising effect is poor for artificial visual perception, and the like, when the fixed noise template needs to be adjusted or updated, all pixels or any pixel can be changed according to the user requirements. This is dependent on the fact that the fixed noise template is stored digitally and can be adjusted/updated to the handset processing unit at any time.

It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.

Claims (7)

1. A novel pixel circuit, comprising: the APS array, the pixel reading unit and the digital processing unit;

it is characterized in that the preparation method is characterized in that,

further comprising an auxiliary pixel P disposed beside the APS array _G (ii) a The auxiliary pixel P _G The production process and the circuit structure of the APS array are the same as those of any APS in the APS array, and 4T is adopted-an APS structure; at the auxiliary pixel P _G One or more layers of shading masks are arranged on the top;

the pixel reading unit is used for reading the pixel voltage of the APS array pixel by pixel and reading the auxiliary pixel P at the same time of reading the pixel voltage of the APS array each time _G The two voltages are subjected to difference and amplification and then input to the digital processing unit through an ADC;

and the digital processing unit stores the received digital quantization values one by one corresponding to the positions in the APS array to obtain array data with the FPN removed.

2. A novel pixel circuit according to claim 1, characterized in that the pixels of the APS array and the auxiliary pixel P _G PD-MOS is used as the photosensitive element.

3. The novel pixel circuit according to claim 1, wherein the digital processing unit presets a fixed noise template of the APS array, and the fixed noise template is subtracted from the array data after the FPN removal by the pixel reading unit to obtain the final de-noised array data.

4. A novel pixel circuit according to claim 3, wherein the fixed noise template is obtained by: placing the APS array in a dark environment; the pixel reading unit reads pixel voltages of the APS array pixel by pixel, and reads the auxiliary pixel P while reading the APS array pixel voltages each time _G The two voltages are subjected to difference and amplification and then are input to the digital processing unit through the ADC; and the digital processing unit stores the received digital quantization values one by one corresponding to the positions in the APS array to obtain the fixed noise template.

5. The novel pixel circuit of claim 4, wherein the digital processing unit updates or resets the fixed noise template according to a user instruction.

6. The novel pixel circuit according to claim 1, wherein the pixel reading unit comprises at least three operational amplifiers and four resistors;

the non-inverting terminal of the operational amplifier OPA1 is externally connected with the auxiliary pixel P _G The inverting terminal of the operational amplifier OPA1 is connected to the output terminal of the operational amplifier OPA1, and the output terminal of the operational amplifier OPA1 is grounded after passing through the resistor R2 and the resistor R3 in sequence;

the in-phase end of the operational amplifier OPA2 is externally connected with the voltage output end of the APS array, the inverting end of the operational amplifier OPA2 is connected with the output end of the operational amplifier OPA2, and the output end of the operational amplifier OPA2 is connected with the input end of the ADC after sequentially passing through a resistor R1 and a resistor R4;

the in-phase end of the operational amplifier OPA3 is connected with the connection point of the resistor R2 and the resistor R3, the inverting end of the operational amplifier OPA3 is connected with the connection point of the resistor R1 and the resistor R4, and the output end of the operational amplifier OPA3 is connected with the input end of the ADC;

and, let the resistance ratio R3/R2= R4/R1= β, where β is the amplification factor of the pixel reading unit.

7. A noise reduction method, characterized in that noise reduction is performed by using a novel pixel circuit according to any one of claims 1 to 6.

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