CN115641818A

CN115641818A - Shift register unit, scanning driving circuit, display panel and display device

Info

Publication number: CN115641818A
Application number: CN202211319041.8A
Authority: CN
Inventors: 叶嘉辉
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2022-10-26
Filing date: 2022-10-26
Publication date: 2023-01-24

Abstract

The application discloses a shift register unit, a scanning driving circuit, a display panel and a display device. The shift register unit includes: an input signal transmission module for transmitting an input signal to a first node in response to a first clock signal; the first output control module is used for responding to the second clock signal and outputting a first control signal when the first node is an effective signal; the first clock signal and the second clock signal are alternately active; the second output control module is used for responding to the invalid signal of the second clock signal and converting the first control signal into a second control signal; the output module is used for responding to the first control signal and transmitting the first voltage signal to the signal output end; or, in response to a second control signal, transmitting a second voltage signal to the signal output terminal; the first voltage signal and the second voltage signal are stable voltage signals. According to the embodiment of the application, the parasitic capacitance connected with the clock signal line can be reduced, and the driving power consumption of the shift register unit is reduced.

Description

Shift register unit, scanning driving circuit, display panel and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a shift register unit, a scanning drive circuit, a display panel and a display device.

Background

Currently, a display panel is generally composed of a plurality of light emitting pixels arranged in an array, and the light emitting pixels are composed of pixel circuits and light emitting elements. The pixel circuit is generally composed of a TFT (Thin Film Transistor) and a capacitor. The Light Emitting element may generally include an OLED (Organic Light-Emitting Diode) or other Light Emitting devices.

In the operation process of the pixel circuits, scanning signals are generally written into corresponding scanning signal lines row by row through a plurality of cascaded shift registers, so that each row of pixel circuits controls the light-emitting elements to emit light under the driving of the scanning signals.

In a conventional pixel circuit, a TFT which is active low is generally used. To provide an active low scan signal, one of the two input signals to the shift register is typically a clock signal. Because the clock signal will generate a certain power loss in the jumping process, when the clock signal line is communicated with the scanning signal line, the power consumption of the clock signal in the jumping process can be further increased due to the influence of the parasitic capacitance on the scanning signal line, so that the driving power consumption of the display panel is high.

Disclosure of Invention

The embodiment of the application provides a shift register unit, a scanning drive circuit, a display panel and a display device, and can solve the technical problem of large drive power loss when a clock signal is used as a scanning signal.

In a first aspect, an embodiment of the present application provides a shift register unit, including:

the input signal transmission module is used for responding to a first clock signal and transmitting an input signal to a first node;

the first output control module is used for responding to the second clock signal and outputting a first control signal when the first node is an effective signal; the first clock signal and the second clock signal are alternately active;

the second output control module is used for responding to the invalid signal of the second clock signal and converting the first control signal into a second control signal;

the output module is used for responding to the first control signal and transmitting the first voltage signal to the signal output end; or, in response to a second control signal, transmitting a second voltage signal to the signal output terminal; the first voltage signal and the second voltage signal are stable voltage signals.

In a second aspect, an embodiment of the present application provides a scan driving circuit, including a first clock signal line, a second clock signal line, a first voltage signal line, a second voltage signal line, and a plurality of cascaded shift register units, where the shift register units are shift register units in the foregoing embodiment; the scanning drive circuit also comprises a starting signal line;

in the cascaded shift register units, the signal input end of the first shift register unit is connected with the initial signal line, and the signal input ends of the other shift register units except the first shift register unit are respectively connected with the signal output end of the shift register unit of the previous stage.

In a third aspect, an embodiment of the present application provides a display panel including the scan driving circuit in the above embodiments.

In a fourth aspect, an embodiment of the present application provides a display device, including the display panel in the above embodiments.

Compared with the prior art, the shift register unit, the scanning drive circuit, the display panel and the display device provided by the embodiment of the application have the advantages that the clock signal is set to serve as the control signal of the shift register unit, the stable voltage signal serves as the input signal of the shift register unit, and the two paths of input signals can be driven by the two paths of clock signals to be respectively used as the output signals to be output. The stable voltage signal with fixed potential can not generate signal jump, so the parasitic capacitance on the signal wire connected with the signal output end can not generate larger power loss due to the signal jump. The two paths of clock signals are only used as control signals and are not communicated with other signal lines, so that parasitic capacitance electrically connected with the clock signal lines can be greatly reduced, and when the clock signals generate signal jump, the power loss generated by charging and discharging of the parasitic capacitance during the signal jump can be reduced. The driving power consumption of the shift register unit can be reduced by reducing the driving power consumption of the clock signal line and reducing the power loss of the parasitic capacitor on the signal line connected with the signal output end, and further the overall power consumption of the display panel is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a shift register unit according to an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 4 is a schematic circuit diagram of a shift register unit according to still another embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a shift register unit according to another embodiment of the present application;

FIG. 6 is a schematic circuit diagram of a shift register unit according to still another embodiment of the present disclosure;

FIG. 7 is a schematic circuit diagram of a shift register unit according to another embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a shift register unit according to still another embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present application;

FIG. 10 is a signal timing diagram of a scan driving circuit according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present application.

In the drawings:

100. a shift register unit; 10. an input signal transmission module; 11. a first potential maintaining module; 20. a first output control module; 21. a second node control module; 22. a third node control module; 30. a second output control module; 40. an output module; OUT, a signal output terminal; n1, a first node; n2, a second node; n3, a third node; n4, a fourth node; CK. A first clock signal; XCK, second clock signal; STV, input signal line; VGL, first voltage signal; VGH, second voltage signal; CK1, first clock signal line; CK2, second clock signal line; m1, a first transistor; m1a, a first sub-transistor; m1b, a second sub-transistor; m2, a second transistor; m3, a third transistor; m4, a fourth transistor; m5, a fifth transistor; m6, a sixth transistor; m7, a seventh transistor; m8, an eighth transistor; m9, a ninth transistor; c1, a first capacitor; c2, a second capacitor; c3, and a third capacitor.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.

In a conventional pixel circuit, TFTs which are active at a low level are generally used. To provide an active low scan signal, one of the two input signals to the shift register is typically a clock signal. Because the clock signal will generate a certain power loss in the jump process, when the clock signal line is communicated with the scanning signal line, the power consumption of the clock signal in the jump process will be further increased under the influence of the parasitic capacitance on the scanning signal line, so that the driving power consumption of the display panel is high.

In order to solve the above technical problem, an embodiment of the present application provides a shift register unit, a scan driving circuit, a display panel and a display device. The following first describes a display panel provided in an embodiment of the present application.

Fig. 1 illustrates a schematic structural diagram of a shift register unit according to an embodiment of the present application. The shift register unit includes an input signal transmission module 10, a first output control module 20, a second output control module 30, and an output module 40.

The input signal transmission module 10 can transmit an input signal to the first node N1 upon receiving the first clock signal CK in response to the first clock signal CK.

The first output control module 20 can respond to the second clock signal XCK, and the first output control module 20 can output the first control signal when the second clock signal XCK is received and the first node N1 is the valid signal.

The first clock signal CK and the second clock signal XCK are alternately active signals. That is, the input signal transmission module 10 can transmit the input signal to the first node N1 when the first clock signal CK is active. When the second clock signal XCK is asserted, if the input signal transmitted to the first node N1 changes the level of the first node N1 into an active signal, the first output control module 20 may output the first control signal. On the contrary, when the second clock signal XCK is asserted, if the input signal transmitted to the first node N1 changes the level of the first node N1 to the inactive signal, the first output control module 20 does not output the first control signal.

It should be understood that the first clock signal CK and the second clock signal XCK are alternatively valid signals, which means that at most one of the first clock signal CK and the second clock signal XCK is valid at the same time. The active signal interval of the first clock signal CK and the active signal interval of the second clock signal XCK may have a certain time interval.

The second output control module 30 is capable of responding to an inactive signal of the second clock signal XCK and converting the first control signal into the second control signal.

When the second clock signal XCK is an active signal and the first node N1 is an active signal, the first output control module 20 can output the first control signal. The second output control module 30 can convert the first control signal into the second control signal when the second clock signal XCK becomes the inactive signal.

The output module 40 may be responsive to the first control signal or the second control signal. When the output module 40 receives the first control signal, the first voltage signal VGL may be transmitted to the signal output terminal OUT; when the output module 40 receives the second control signal, the second voltage signal VGH may be transmitted to the signal output terminal OUT. The first voltage signal VGL and the second voltage signal VGH are both stable voltage signals. The first voltage signal VGL and the second voltage signal VGH alternately output by the output module 40 may be output to the scan signal line through the signal output terminal OUT and serve as the scan signal. The pixel circuit connected to the scanning signal line can supply a driving current to the corresponding light emitting element under the driving of the scanning signal, so that the light emitting element emits light.

When the conventional display panel provides a scan signal with an effective low level, two input signals of the shift register are generally a high level signal and a clock signal, respectively. Namely, one of the two input signals is a stable voltage signal, and the other input signal is a jump signal. When the shift register outputs the clock signal, the clock signal terminal is electrically connected to the scanning signal line. The scanning signal line has a large parasitic capacitance, and when the voltage jump occurs at the clock signal end, the parasitic capacitance on the scanning signal line is charged and discharged, so that a large amount of unnecessary power loss is generated.

By using the two stable voltage signals as the two input signals of the shift register, when the two input signals are communicated with the scanning signal line by the shift register, the parasitic capacitor on the scanning signal line receives the stable voltage signals, the charging and discharging times of the parasitic capacitor are greatly reduced, and the generated power loss is also greatly reduced. Meanwhile, the clock signal is only used as a control signal and is not electrically connected with the scanning signal line, so that parasitic capacitance electrically connected with the clock signal line is greatly reduced when the voltage of the clock signal jumps, and the driving power consumption of the clock signal line when the signal jumps is reduced.

In this embodiment, by setting the first clock signal CK and the second clock signal XCK as control signals of the shift register unit and the first voltage signal VGL and the second voltage signal VGH as input signals of the shift register unit, the first voltage signal VGL and the second voltage signal VGH can be alternately output as output signals under the control of the first clock signal CK and the second clock signal XCK. When the clock signal is only used as a control signal, the clock signal is not communicated with the signal output end OUT, and the parasitic capacitance connected to the clock signal wire is greatly reduced, so that the driving power loss of the clock signal wire when the signal jumps is reduced. The signal output end OUT is only communicated with the two paths of stable voltage signals, so that the charging and discharging times of a parasitic capacitor connected with the signal output end OUT under the driving of the stable voltage signals are greatly reduced compared with the charging and discharging times under the driving of clock signals, and the power loss generated during the charging and discharging of the parasitic capacitor is reduced. The driving power consumption of the shift register unit can be reduced by reducing the driving power consumption of the clock signal line and reducing the power consumption of the parasitic capacitor on the signal line connected with the signal output end OUT, and the overall power consumption of the display panel is further reduced.

In some embodiments, the input signal transmission module 10 may include a first transistor M1.

A first pole of the first transistor M1 is connected to the input signal line STV, a second pole of the first transistor M1 is connected to the first node N1, and a gate of the first transistor M1 is connected to the first clock signal terminal.

When the first clock signal CK output from the first clock signal terminal alternates between an active signal and an inactive signal, the first transistor M1 can be turned on upon receiving the active signal of the first clock signal CK to connect the input signal line STV with the first node N1, and transmit the input signal on the input signal line STV to the first node N1.

It is understood that, when the first clock signal CK is an active signal, if the input signal is at a high level, the first transistor M1 can transmit a high level signal to the first node N1; if the input signal is at a low level, the first transistor M1 can transmit a low level signal to the first node N1.

It is understood that, in the plurality of cascaded shift register units, the signal input terminal of the first shift register unit may be connected to the start signal line and receive the start signal STV as an input signal. The signal input ends of the other shift register units may be connected to the signal output end OUT of the shift register unit of the previous stage, and receive the output signal of the shift register unit of the previous stage as an input signal.

Referring to fig. 2, in some embodiments, the first transistor M1 may include a first sub-transistor M1a and a second sub-transistor M1b.

A first pole of the first sub-transistor M1a is connected to the input signal line STV, a second pole of the first sub-transistor M1a is connected to a first pole of the second sub-transistor M1b, a second pole of the second sub-transistor M1b is connected to the first node N1, and a gate of the first sub-transistor M1a and a gate of the second sub-transistor M1b are connected to the first clock signal terminal.

The first and second sub-transistors M1a and M1b may form a double gate transistor connected in series, and gates of the first and second sub-transistors M1a and M1b are connected to the first clock signal terminal. That is, when the first clock signal CK is an active signal, the first sub-transistor M1a and the second sub-transistor M1b are turned on synchronously.

When the input signal line STV is connected to the first node N1 through the first sub-transistor M1a and the second sub-transistor M1b, the voltage signal received by the first node N1 is a signal voltage formed by the signal voltage of the input signal through the turn-on voltage drops of the two sub-transistors. By providing two sub-transistors between the input signal and the first node N1, the voltage drop of the input signal can be increased, thereby pulling down the signal voltage received by the first node N1.

The above-described embodiment can be applied to the active signal of the first node N1 being a low level signal. That is, when the input signal is a low level signal, the input signal can be further pulled low by providing the two sub-transistors, so that the first node N1 receives a lower effective low level signal.

It is understood that the first transistor M1 may also be formed by three or more sub-transistors connected in series, and a corresponding number of the sub-transistors may be arranged according to the signal voltage of the input signal and the voltage range of the effective signal of the first node N1, so as to sufficiently pull down the signal voltage of the input signal through the conduction voltage drops of the sub-transistors, so that the signal voltage received by the first node N1 is stabilized within the effective signal range.

Referring to fig. 3, in some embodiments, the input signal transmission module 10 may further include a first potential maintaining module 11, a first end of the first potential maintaining module 11 is connected to the first node N1, and a second end of the first potential maintaining module 11 is connected to the first voltage signal line.

When the first transistor M1 is turned on, the input signal line STV communicates with the first node N1, and the input signal is coupled to the first node N1.

When the first clock signal CK changes from the active signal to the inactive signal, the first transistor M1 is turned off under the inactive signal of the first clock signal CK. At this time, the voltage of the first node N1 is the signal voltage of the input signal when the first transistor M1 is turned on.

During the time interval when the first transistor M1 is turned off, the first potential maintaining module 11 can maintain the potential of the first node N1, so that the voltage of the first node N1 is maintained at the signal voltage of the input signal.

With continued reference to fig. 3, in some embodiments, the first voltage sustaining module 11 may include a first capacitor C1.

Both ends of the first capacitor C1 are respectively connected to the first voltage signal line and the first node N1, and when the first transistor M1 is turned off, the first capacitor C1 can maintain the potential of the first node N1 through capacitive coupling.

Referring to fig. 4, in some embodiments, the output module 40 may include a second transistor M2 and a third transistor M3.

A first pole of the second transistor M2 is connected to the first voltage signal line, a second pole of the second transistor M2 is connected to the signal output terminal OUT, and a gate of the second transistor M2 is connected to the second node N2. A first pole of the third transistor M3 is connected to the second voltage signal line, a second pole of the third transistor M3 is connected to the signal output terminal OUT, and a gate of the third transistor M3 is connected to the third node N3.

The first output control module 20 outputs the first control signal that the second node N2 is at the on-potential and the third node N3 is at the off-potential. Under the first control signal, the second transistor M2 is turned on, the third transistor M3 is turned off, and the first voltage signal line is connected to the signal output terminal OUT, and outputs the first voltage signal VGL through the signal output terminal OUT.

The second output control module 30 outputs a second control signal that the second node N2 is at an off potential and the third node N3 is at an on potential. Under the second control signal, the second transistor M2 is turned off, the third transistor M3 is turned on, and the second voltage signal line is connected to the signal output terminal OUT, so that the second voltage signal VGH is output through the signal output terminal OUT.

The output module 40 may communicate the first voltage signal line or the second voltage signal line with the signal output terminal OUT by receiving the first control signal and the second control signal which are alternately output, so as to output the first voltage signal VGL or the second voltage signal VGH through the signal output terminal OUT.

When the shift register unit provides the pixel circuit with the scanning signal, the scanning signal can be generated by the first voltage signal VGL and the second voltage signal VGH which are alternately output, so as to drive the pixel circuit to provide the light-emitting element with the driving current, and the light-emitting element emits light.

It is understood that the first voltage signal VGL may be a low level signal, the second voltage signal VGH may be a high level signal, and the scan signal may be active low. The signal output end OUT of the shift register unit is electrically connected with the scanning signal line, and each pixel circuit receives the scanning signal output by the shift register unit through the scanning signal line.

Parasitic capacitance exists on the scanning signal line, when the signal output end OUT of the shift register unit is communicated with the scanning signal line, the parasitic capacitance on the scanning signal line can be charged and discharged when a voltage signal jumps, certain power loss can be generated in the charging and discharging process of the parasitic capacitance, and therefore the driving power consumption of the shift register unit is increased. Through setting up two steady voltage signals, first voltage signal VGL and second voltage signal VGH are as output signal promptly, when first voltage signal line or second voltage signal line and scanning signal line intercommunication, because first voltage signal VGL and second voltage signal VGH are steady voltage signal, in the time quantum that corresponding signal line and scanning signal line communicate, steady voltage signal can not take place the voltage jump, thereby make parasitic capacitance on the scanning signal line can't carry out the charge-discharge at the jump in-process, and then reduced parasitic capacitance's charge-discharge loss.

Referring to fig. 5, in some embodiments, the first output control module 20 may include a second node control module 21 and a third node control module 22.

A first end of the second node control module 21 is connected to the first node N1, and a second end of the second node control module 21 is connected to the second node N2. A first end of the third node control module 22 is connected to the first node N1, and a second end of the third node control module 22 is connected to the third node N3.

The second node control module 21 may transmit a turn-on signal to the second node N2 when the first node N1 is the active signal, so that the second node N2 becomes a turn-on potential. The third node control module 22 may transmit an off signal to the third node N3 when the first node N1 is an active signal, so that the third node N3 becomes an off potential.

When the input signal is an active signal, the input signal transmission module 10 may transmit the input signal to the first node N1 when the first clock signal CK is an active signal, so that the first node N1 becomes an active signal.

When the first node N1 is an active signal, the second node control module 21 of the first output control module 20 may transmit a turn-on signal to the second node N2 in response to the second clock signal XCK; the third node control module 22 of the first output control module 20 may transmit a disable signal to the third node N3 in response to the second clock signal XCK. That is, when the first node N1 is an active signal, the second clock signal XCK may drive the first output control module 20 to set the potential of the second node N2 to an on potential and the potential of the third node N3 to an off potential. When the second node N2 is at the on-potential and the third node N3 is at the off-potential, it is equivalent to the first output control module 20 outputting the first control signal.

Referring to fig. 6, in some embodiments, the second node control module 21 may include a fourth transistor M4 and a fifth transistor M5.

A first pole of the fourth transistor M4 is connected to the first voltage signal line, and a gate of the fourth transistor M4 is connected to the first node N1. A first pole of the fifth transistor M5 is connected to a second pole of the fourth transistor M4, a second pole of the fifth transistor M5 is connected to the second node N2, and a gate of the fifth transistor M5 is connected to the second clock signal terminal.

When the first node N1 is an active signal, the fourth transistor M4 is turned on, and the first electrode of the fifth transistor M5 is connected to the first voltage signal line through the fourth transistor M4. When the second clock signal XCK output from the second clock signal terminal is an active signal, the fifth transistor M5 is turned on, the second node N2 is connected to the first voltage signal line through the fifth transistor M5 and the fourth transistor M4, and the second node N2 receives the first voltage signal VGL.

It can be understood that when the second node N2 receives the first voltage signal VGL, the second node N2 is at the on-potential. That is, the fourth transistor M4 and the fifth transistor M5 connect the second node N2 to the first voltage signal line, and set the potential of the second node N2 to the potential of the on signal.

In some embodiments, the second node control module 21 may further include a second capacitor C2.

A first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the signal output terminal OUT.

When the third node control module 22 transmits the off signal to the third node N3, the output module 40 receives the off potential of the third node N3, and may disconnect the second voltage signal line from the signal output terminal OUT. When the second voltage signal line is disconnected from the signal output terminal OUT, the second capacitor C2 couples the signal output terminal OUT and the second node N2, so that the voltage of the second node N2 is stabilized within the voltage range of the on-potential, and the output module 40 connects the first voltage signal line to the signal output terminal OUT when the second node N2 is the on-potential.

In an alternative embodiment, taking the first voltage signal VGL as a low level and the second voltage signal VGH as a high level as an example, when the second voltage signal line is disconnected from the signal output terminal OUT, the voltage of the signal output terminal OUT is decreased from the high level signal. In the process of the voltage drop of the signal output terminal OUT, the voltage of the second node N2 is also dropped by the second capacitor C2 through capacitive coupling, so that the voltage of the second node N2 is effectively pulled down, and the voltage of the second node N2 is reduced to the voltage range of the on-potential.

Referring to fig. 7, in some embodiments, the third node control module 22 may include a sixth transistor M6 and a seventh transistor M7.

A first pole of the sixth transistor M6 is connected to the first node N1, and a gate of the sixth transistor M6 is connected to the second clock signal terminal. A gate of the seventh transistor M7 is connected to the second pole of the sixth transistor M6, a first pole of the seventh transistor M7 is connected to the second voltage signal line, and a second pole of the seventh transistor M7 is connected to the third node N3.

When the second clock signal XCK is an active signal, the sixth transistor M6 is turned on to connect the first node N1 to the gate of the seventh transistor M7. When the first node N1 is an active signal, the gate of the seventh transistor M7 receives the active signal of the first node N1 and is turned on, so as to connect the second voltage signal line to the third node N3, and the third node N3 receives the second voltage signal VGH.

It can be understood that, when the third node N3 receives the second voltage signal VGH, the third node N3 is at an off potential. That is, the sixth transistor M6 and the seventh transistor M7 connect the third node N3 to the second voltage signal line, and set the potential of the third node N3 to the potential of the off signal.

Referring to fig. 8, in some embodiments, the second output control module 30 may include a third capacitor C3, an eighth transistor M8 and a ninth transistor M9.

A first end of the third capacitor C3 is connected to the fourth node N4, and a second end of the third capacitor C3 is connected to the second clock signal end. A gate of the eighth transistor M8 is connected to the fourth node N4, a first pole of the eighth transistor M8 is connected to the first voltage signal line, and a second pole of the eighth transistor M8 is connected to the third node N3. A gate of the ninth transistor M9 is connected to the third node N3, a first pole of the ninth transistor M9 is connected to the second voltage signal line, and a second pole of the ninth transistor M9 is connected to the second node N2.

When the second clock signal XCK output from the second clock signal terminal changes from an active signal to an inactive signal, the third capacitor C3 can pull the voltage of the fourth node N4 low or high through capacitive coupling. Taking the active signal of the second clock signal XCK as a low level signal, the third capacitor C3 can pull up the voltage of the fourth node N4 to a high level through coupling when the second clock signal XCK changes to a high level signal.

After the third capacitor C3 adjusts the voltage of the fourth node N4 through capacitive coupling, the gate of the eighth transistor M8 may receive the adjusted voltage of the fourth node N4 and be turned on, so as to connect the third node N3 with the first voltage signal line. When the third node N3 receives the first voltage signal VGL, the third node N3 is at a conducting potential.

When the third node N3 receives the first voltage signal VGL and changes to the on-potential, the gate of the ninth transistor M9 receives the on-potential of the third node N3, and connects the second voltage signal line to the second node N2. When the second node N2 receives the second voltage signal VGH, the second node N2 is at the off-potential.

In the second output control module 30, the third capacitor C3 and the eighth transistor M8 may connect the third node N3 with the first voltage signal line, so as to change the third node N3 to the on-potential. When the third node N3 is at the on potential, the ninth transistor M9 may connect the second voltage signal line to the second node N2 to turn the second node N2 to the off potential. When the third node N3 is at the on-potential and the second node N2 is at the off-potential, it is equivalent to the second output control module 30 outputting the second control signal.

In some embodiments, as shown in fig. 8, the fourth node N4 may be a common node between the gate of the seventh transistor M7 and the second pole of the sixth transistor M6.

When the second clock signal XCK is an active signal, the sixth transistor M6 is turned on, and the fourth node N4 is connected to the first node N1. When the second clock signal XCK is an inactive signal, the sixth transistor M6 is turned off, and the voltage of the fourth node N4 is coupled through the third capacitor C3, so that the eighth transistor M8 is turned on. It is to be understood that when the fourth node N4 is communicated with the first node N1, the eighth transistor M8 should be in an off state. That is, the eighth transistor M8 is turned off by the active signal of the first node N1.

In an alternative embodiment, the active signal of the first node N1 is a low level signal, and the active signals of the first clock signal CK and the second clock signal XCK are also low level signals. The eighth transistor M8 is turned off by the active signal of the first node N1, and the eighth transistor M8 may be configured as an N-type transistor. The other transistors are turned on by the active signal of the first node N1, the first clock signal CK, or the second clock signal XCK, and the other transistors may be P-type transistors.

It will be appreciated that the N-type transistor may generally be an oxide transistor, and may for example be an IGZO (Indium gallium zinc oxide) transistor. The P-type transistor may be generally a LTPS (Low Temperature polysilicon) transistor. When the eighth transistor M8 is connected to the third node N3 and the first voltage signal line, the drain current of the oxide transistor is smaller than that of the low-temperature polysilicon transistor, so that the first voltage signal VGL on the first voltage signal line can be prevented from flowing into the third node N3 and affecting the potential of the third node N3.

Referring to fig. 8, in some embodiments, the eighth transistor M8 may be a top-bottom double-gate N-type transistor, a top gate of the eighth transistor M8 is connected to the fourth node N4, and a bottom gate of the eighth transistor M8 is connected to the first gate of the eighth transistor M8.

The eighth transistor M8 may be configured as a top-bottom dual-gate transistor in which a voltage signal received by a bottom gate is used to adjust a threshold voltage Vth of the transistor, and a voltage signal received by a top gate is used to drive the transistor on or off. The bottom gate of the eighth transistor M8 is connected to the first electrode of the eighth transistor M8, so that the bottom gate can be electrically connected to the first voltage signal VGL, and the threshold voltage of the eighth transistor M8 can be adjusted to a suitable range by adjusting the signal magnitude of the first voltage signal VGL, so that when the second clock signal XCK becomes an invalid signal, the voltage signal obtained by coupling the fourth node N4 through the third capacitor C3 can be greater than the threshold voltage of the eighth transistor M8, and thus the eighth transistor M8 is stably turned on.

Referring to fig. 9, an embodiment of the present invention further provides a scan driving circuit, which includes a first clock signal line CK1, a second clock signal line CK2, a first voltage signal line, a second voltage signal line, and a plurality of shift register units 100 connected in cascade. The shift register unit 100 is the shift register unit in the above embodiment. The scan driving circuit further includes a start signal line.

IN the cascade-connected shift register units 100, the signal input terminal IN of the first shift register unit 100 is connected to a start signal line, and the start signal STV provided by the start signal line can be used as an input signal. The signal input ends IN of the other shift register units 100 except the first shift register unit 100 are respectively connected to the signal output end OUT of the shift register unit 100 of the previous stage, and the output signal of the shift register unit 100 of the previous stage can be used as the input signal of the shift register unit 100 of the next stage, so that the shift register units 100 can output the scanning signal line by line.

Referring to fig. 9, in some embodiments, any two adjacent shift register units 100 are provided. If the first clock signal terminal of one of the shift register units 100 is connected to the first clock signal line CK1, and the second clock signal terminal is connected to the second clock signal line CK 2; the first clock signal terminal of the other shift register unit 100 is connected to the second clock signal line CK2, and the second clock signal terminal is connected to the first clock signal line CK 1.

That is, when two adjacent shift register units 100 are accessed, the first clock signal line CK1 is connected to the first clock signal terminal of one of the shift register units 100 and to the second clock signal terminal of the other shift register unit 100. Similarly, when two adjacent shift register units 100 are accessed, the second clock signal line CK2 is connected to the first clock signal terminal of one shift register unit 100 and to the second clock signal terminal of the other shift register unit 100.

In an alternative embodiment, the input signal, the first clock signal and the second clock signal are all active low. Referring to fig. 8 to 10, IN the cascaded shift register units, the signal input terminal IN of the first shift register unit receives the start signal STV, the first clock signal terminal receives the first clock signal CK, and the second clock signal terminal receives the second clock signal XCK.

In the t1 phase, the STV signal and the CK signal are active signals, the first sub-transistor M1a and the second sub-transistor M1b are turned on, and the STV low level active signal is connected to the first node N1. The potential of the first node N1 can be maintained by the first capacitor C1.

In the period t2, the XCK signal is an active signal, the low level signal of the first node N1 drives the fourth transistor M4 to be turned on, the XCK signal drives the fifth transistor M5 to be turned on, at this time, the second node N2 is electrically connected to the first voltage signal VGL through the fourth transistor M4 and the fifth transistor M5, and the second node N2 becomes a low level.

The XCK signal also drives the sixth transistor M6 to turn on, the gate of the seventh transistor M7 receives the low level signal of the first node N1, the seventh transistor turns on, and at this time, the third node N3 is electrically connected to the second voltage signal VGH through the seventh transistor, and the third node N3 becomes a high potential.

When the second node N2 is at a low potential and the third node N3 is at a high potential, the second transistor M2 is turned on and the third transistor M3 is turned off, and the signal output terminal of the shift register unit outputs a first voltage signal, i.e., OUT1 outputs a low level signal.

In the period t3, the XCK signal is an inactive signal, and the fifth transistor M5 and the sixth transistor M6 are turned off. When the XCK signal is pulled up to be a high level signal, the third capacitor C3 pulls up the voltage of the fourth node N4 through capacitive coupling, the eighth transistor M8 is turned on when the fourth node N4 is a high level, the third node N3 is electrically connected to the first voltage signal VGL, and at this time, the third node N3 becomes a low potential.

When the third node N3 becomes a low potential, the ninth transistor M9 is turned on to electrically connect the second node N2 with the second voltage signal VGH, and at this time, the second node N2 becomes a high potential.

When the second node N2 is at a high potential and the third node N3 is at a low potential, the second transistor M2 is turned off, the third transistor M3 is turned on, and the signal output terminal of the shift register unit outputs a second voltage signal, i.e., the signal output terminal OUT1 outputs a high level signal.

When the shift register unit outputs the OUT1 signal, the OUT1 signal can also be used as an input signal of a shift register unit of a next stage. When the OUT1 signal is a low-level signal, the shift register unit of the next stage may use the OUT1 low-level signal as an input signal. It is understood that when the shift register unit receives the STV signal in the time period t1, the shift register unit may output a low level signal of OUT1 in the time period t 2. And when the shift register unit of the next stage receives the low-level signal of OUT1 in the time period t2, the shift register unit of the next stage can output the low-level signal of OUT2 in the time period t 3. Likewise, the shift register unit of the next stage may output a low level signal of OUT3 in the t4 period. Through the plurality of shift register units which are cascaded in sequence, low-level signals of OUT1, OUT2, OUT3,. And OUTN can be output in sequence, so that scanning signal lines corresponding to the shift register units sequentially receive effective scanning signals which are output row by row.

The embodiment of the present application further provides a display panel, which may include the scan driving circuit in the above embodiments of the present application.

An embodiment of the present application further provides a display device, please refer to fig. 11, where the display device may be a PC, a television, a display, a mobile terminal, a tablet computer, a wearable device, and the like, and the display device may include the display panel provided in the embodiment of the present application.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The principles and embodiments of the present application are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present application. It should be noted that there are no specific structures in the above description, and it will be apparent to those skilled in the art that various modifications, decorations, or changes can be made without departing from the principle of the present application, and the technical features can be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the present invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.

Claims

1. A shift register unit, comprising:

an input signal transmission module for transmitting an input signal to a first node in response to a first clock signal;

the first output control module is used for responding to a second clock signal and outputting a first control signal when the first node is an effective signal; the first clock signal and the second clock signal are alternately active;

the second output control module is used for responding to an invalid signal of a second clock signal and converting the first control signal into a second control signal;

2. The shift register unit according to claim 1, wherein the input signal transmission module comprises:

and a first electrode of the first transistor is connected with an input signal line, a second electrode of the first transistor is connected with the first node, and a grid electrode of the first transistor is connected with the first clock signal end.

3. The shift register cell according to claim 2, wherein the first transistor includes a first sub-transistor and a second sub-transistor;

a first pole of the first sub-transistor is connected to the input signal line, a second pole of the first sub-transistor is connected to a first pole of the second sub-transistor, a second pole of the second sub-transistor is connected to the first node, and a gate of the first sub-transistor and a gate of the second sub-transistor are connected to the first clock signal terminal.

4. The shift register unit according to claim 2, wherein the input signal transmission module further comprises:

and a first end of the first potential maintaining module is connected with the first node, and a second end of the first potential maintaining module is connected with a first voltage signal wire.

5. The shift register unit according to claim 4, wherein the first potential maintaining module comprises a first capacitor.

6. The shift register unit according to claim 1, wherein the output module comprises:

a first pole of the second transistor is connected with a first voltage signal line, a second pole of the second transistor is connected with a signal output end, and a grid electrode of the second transistor is connected with a second node;

a third transistor, a first electrode of which is connected to a second voltage signal line, a second electrode of which is connected to a signal output terminal, and a gate of which is connected to a third node;

the first control signal is that the second node is an on potential and the third node is an off potential; the second control signal is that the second node is an off potential and the third node is an on potential.

7. The shift register unit according to claim 6, wherein the first output control module comprises:

a second node control module, a first end of the second node control module being connected to the first node, a second end of the second node control module being connected to the second node; the second node control module is configured to transmit a turn-on signal to the second node when the first node is an active signal;

a third node control module, a first end of the third node control module being connected to the first node, and a second end of the third node control module being connected to the third node; the third node control module is configured to transmit a cutoff signal to the third node when the first node is a valid signal.

8. The shift register unit of claim 7, wherein the second node control module comprises:

a fourth transistor, a first pole of which is connected to a first voltage signal line, and a gate of which is connected to the first node;

a fifth transistor, a first pole of the fifth transistor is connected to a second pole of the fourth transistor, a second pole of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to a second clock signal terminal.

9. The shift register unit of claim 8, wherein the second node control module further comprises:

and a first end of the second capacitor is connected with the second node, and a second end of the second capacitor is connected with the signal output end.

10. The shift register unit according to claim 7, wherein the third node control module comprises:

a sixth transistor, a first pole of which is connected to the first node, and a gate of which is connected to a second clock signal terminal;

a seventh transistor, a gate of which is connected to a second pole of the sixth transistor, a first pole of which is connected to a second voltage signal line, and a second pole of which is connected to the third node.

11. The shift register unit according to claim 10, wherein the second output control module comprises:

a first end of the third capacitor is connected with a fourth node, and a second end of the third capacitor is connected with a second clock signal end;

a gate of the eighth transistor is connected to a fourth node, a first electrode of the eighth transistor is connected to a first voltage signal line, and a second electrode of the eighth transistor is connected to the third node;

a ninth transistor, a gate of which is connected to the third node, a first pole of which is connected to a second voltage signal line, and a second pole of which is connected to the second node.

12. The shift register unit according to claim 11, wherein the fourth node is a common node between the gate of the seventh transistor and the second pole of the sixth transistor.

13. The shift register cell of claim 11, wherein the eighth transistor is a top-bottom double-gate N-type transistor, a top gate of the eighth transistor is connected to the fourth node, and a bottom gate of the eighth transistor is connected to the first gate of the eighth transistor.

14. A scan driving circuit, comprising a first clock signal line, a second clock signal line, a first voltage signal line, a second voltage signal line, and a plurality of cascaded shift register units, wherein the shift register units are the shift register units according to any one of claims 1 to 13; the scanning driving circuit also comprises a starting signal line;

15. The scan driving circuit according to claim 14, wherein in any two adjacent shift register units, a first clock signal terminal of one shift register unit is connected to the first clock signal line, and a second clock signal terminal of the one shift register unit is connected to the second clock signal line; and the first clock signal end of the other shift register unit is connected with the second clock signal line, and the second clock signal end is connected with the first clock signal line.

16. A display panel comprising the scan driver circuit according to claim 14 or 15.

17. A display device characterized by comprising the display panel according to claim 16.