CN115630408A

CN115630408A - Safe extraction structure of PCB-chip mixed fingerprint

Info

Publication number: CN115630408A
Application number: CN202211645502.0A
Authority: CN
Inventors: 贺章擎; 胡成昆; 鲁犇; 马丹; 朱昕蕊; 张寅�
Original assignee: Hubei University of Technology
Current assignee: Hubei University of Technology
Priority date: 2022-12-21
Filing date: 2022-12-21
Publication date: 2023-01-20
Anticipated expiration: 2042-12-21
Also published as: CN115630408B

Abstract

The invention provides a safe extraction structure of a PCB-chip mixed fingerprint, which is characterized in that: the PUF circuit is arranged in the chip, the printed circuit board comprises a bottom printed circuit board and a top printed circuit board, and the fingerprint extraction circuit comprises a discrete resistor and an embedded capacitor; the fingerprint extraction circuit is connected in series with the PUF circuit inside the chip through the port of the chip. The safety extraction structure realizes the safety protection of the information key in the chip by extracting the delay signal mixed in the chip and the circuit board level, and has good anti-tampering and anti-counterfeiting effects.

Description

Safe extraction structure of PCB-chip mixed fingerprint

Technical Field

The invention belongs to the field of integrated circuit design and hardware security anti-counterfeiting, and particularly relates to a PCB-chip mixed fingerprint security extraction structure.

Background

Hardware is a foundation stone for constructing a chip information system, but at present, an attacker can directly acquire key data or even a digital key stored in a chip through hardware attack technologies such as physical detection, intrusive type and semi-intrusive type, so that certain hidden dangers exist in hardware safety, and therefore, the technology for strengthening the hardware safety is very important. A Physical Unclonable Function (PUF) is a promising hardware security primitive that generates a device-unique fingerprint by extracting process variations that are inevitable during the manufacturing process of a circuit, and when the PUF receives an input stimulus (Challenge), it can generate a Response (Response) corresponding to the input stimulus. It can be used to provide a unique identity or to generate and store encryption keys to prevent tampering attacks of the physical device.

Currently, device fingerprint information can be extracted from a chip or from a Printed Circuit Board (PCB). The chip-level fingerprint information sources mainly include delay, frequency and power consumption of input signals on a transmission path. The information can be used for encryption, authentication, identity recognition and other applications of the equipment of the Internet of things. However, new research finds that the mapping relation of the PUF is not changed due to the fact that the chip is not affected by invasion operations such as chip unsoldering and unpacking, and the like, and the PUF can be attacked by semi-invasive physics such as photons and electromagnetic radiation analysis. The fingerprint technology based on the Printed Circuit Board (PCB) generates a unique fingerprint by extracting the randomness difference of the PCB in the manufacturing process, comprises the steps of extracting parameters such as trace impedance, output change of a specific circuit and the like and quantizing the parameters into digital response, and is mainly used for anti-counterfeiting authentication of the circuit board. However, PCB fingerprinting cannot detect tampering and counterfeiting of the chip, while also being easily detected by an attacker.

And the safety protection of the prior PUF technology only aims at the chip, if the external circuit of the chip is damaged or changed, the response of the internal PUF cannot be changed along with the chip, namely, the PUF technology cannot effectively deal with physical attacks such as tampering attack, unsoldering and the like of the external PCB circuit at present, and thus a new way needs to be found for the authentication of the external printed circuit board.

In order to solve the above problems, the present application proposes to provide a "PCB-chip" hybrid fingerprint security extraction structure, which generates a physical characteristic signal through an RC delay circuit on a circuit board and introduces the signal into a chip, couples the physical characteristic signal with a PUF circuit inside the chip to quantize the physical characteristic signal into a hybrid digital fingerprint, and extracts a stable and high-entropy key therefrom. The intrusion protection of the chip level and the detection of the circuit board level tampering are realized. The structure has the characteristic of unclonable on the whole, and further ensures the safety and the credibility of a hardware system.

Disclosure of Invention

The chip-level PUF circuit is easy to be attacked in an invasive way and is easy to be falsified and forged based on a printed circuit board PUF. The invention provides a hybrid fingerprint extraction structure oriented to PCB and chip safety. The method aims to extract the delay signals mixed in the chip and the circuit board, thereby realizing the safety protection of the information key in the chip and simultaneously achieving the aim of preventing the circuit board from being falsified and forged.

The technical scheme adopted for solving the problems in the prior art is as follows:

a safe extraction structure of a PCB-chip mixed fingerprint comprises a Printed Circuit Board (PCB) and a fingerprint extraction circuit arranged in the PCB, wherein a chip 1 is arranged above the PCB, a PUF circuit 2 is arranged inside the chip 1, the PCB comprises a bottom printed circuit board 13 and a top printed circuit board 10, and the fingerprint extraction circuit comprises a discrete resistor 9 and an embedded capacitor; the fingerprint extraction circuit is connected in series with the PUF circuit 2 in the chip through a port of the chip 1.

The chip 1 is packaged by adopting a Ball Grid Array (BGA) technology, and a plurality of chip pins are arranged outside the chip 1.

The chip pins are connecting pins of the PUF circuit inside the chip and the top-layer printed circuit board 10.

The PUF circuit 2 includes but is not limited to a common PUF circuit implementation using arbiters, ROs, and the like.

The fingerprint extraction circuit comprises two discrete resistors 9 and two embedded double-layer sawtooth capacitors 5, the two double-layer sawtooth capacitors 5 are respectively connected with the two discrete resistors 9 in series, and the fingerprint extraction circuit formed by each double-layer sawtooth capacitor 5 and the discrete resistor 9 is communicated with the chip 1 through pins of the chip 1.

The top layer printed circuit board 10 is provided with a through hole A4, and the fingerprint extraction circuit is communicated with the chip pins through the through hole A4 and further connected with the PUF circuit in the chip.

The double-layer sawtooth capacitor 5 comprises a two-layer structure arranged in parallel, and comprises an upper-layer capacitor circuit board and a lower-layer capacitor circuit board, wherein a plurality of upper-layer printed copper traces 6 are arranged on the upper-layer capacitor circuit board, a lower-layer printed copper trace 7 is arranged on the lower-layer capacitor circuit board, and the upper-layer printed copper traces and the lower-layer printed copper traces respectively comprise a plurality of copper traces which are attached to the surface of the capacitor circuit board and distributed in a sawtooth shape.

The bottom layer printed circuit board 13 is provided with a substrate 8, the double-layer sawtooth capacitor 5 is arranged on the substrate 8, and the discrete resistor 9 is arranged between the printed circuit board and the double-layer sawtooth capacitor 5.

And the double-layer sawtooth capacitor 5 is provided with a through hole B11 which penetrates through the capacitor, the substrate 8 and the bottom printed circuit board 13, and the double-layer sawtooth capacitor 5 is grounded through the through hole B11.

And the double-layer sawtooth capacitor 5 is provided with a through hole C12 for penetrating the capacitor, and the double-layer sawtooth capacitor 5 is in circuit connection with the discrete resistor 9 through the through hole C12.

The RC delay circuit structure on the Printed Circuit Board (PCB) is composed of a capacitor and a discrete resistor. For a first-order RC delay circuit on a board, a double-layer sawtooth capacitor is designed by using a metal copper trace, as shown in figure 2, an upper-layer printed copper trace 6 printed on an upper-layer capacitor circuit board and a lower-layer printed copper trace 7 printed on a lower-layer capacitor circuit board form a double-layer sawtooth capacitor 5, the upper-layer copper trace and the lower-layer copper trace are all attached to the capacitor circuit board and are distributed in a sawtooth shape, a transverse and vertical superposed capacitor is formed in the double-layer sawtooth capacitor 5, and a transverse electric field and a vertical electric field can be generated in the double-layer sawtooth capacitor during charging.

Each group of discrete resistors and embedded capacitors are connected in series to form a PCB deviation extraction circuit, and the structure is embedded into an inner layer of a printed circuit board and is arranged below a chip 1, as shown in fig. 1. The PCB fingerprint characteristic signal is introduced into the PUF circuit inside the chip through the connection of the through holes and the pins of the chip. In the time delay circuit, the main time delay characteristic is contributed by capacitance, and the sawtooth copper trace structure of the double-layer sawtooth capacitor can obtain enough capacitance density so as to realize difficult-to-imitate process manufacturing deviation. Due to the random process difference of the PCB in the manufacturing process, the capacitance delay characteristic can be regarded as the unique fingerprint information of each PCB, and different PCBs can generate different delay characteristics due to the manufacturing deviation of the capacitance. When an RC circuit is introduced into the on-chip PUF through the pins, it is equivalent to splicing off the internal disconnected delay paths, and these new delay chains contain both PCB-level and chip-level delay information. When the signal in the chip reaches the output I/O port, the signal is converted into the input voltage of the RC circuit, the delay effect is achieved by charging the capacitor, and finally the signal returns to the internal circuit of the chip through the chip pin. Thereby coupling the PCB-specific fingerprint information in series with the chip internal PUF circuit to produce a digital response 1 or 0. The whole hybrid PUF structure is completely realized based on digitization, a required delay effect can be achieved without an additional analog circuit, and meanwhile the hybrid PUF structure reflects PCB trace delay and changes of impedance, a capacitor, resistance, I/O and IC processes.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a 'PCB-chip' mixed fingerprint security extraction structure, which comprises a PCB fingerprint extraction circuit structure on a Printed Circuit Board (PCB) and an on-chip PUF circuit structure inside a chip. The PCB fingerprint extraction circuit can extract the random difference of the PCB in the manufacturing process through a delay circuit formed by the RC, the on-chip PUF circuit structure in the chip can extract the random difference of the chip in the manufacturing process, the two are coupled and connected in series through a chip port, and finally, a digital response containing the specific information of each PCB is generated. In general, the PUF circuit converts random differences between a chip and a circuit board during manufacturing into unique input-output correspondences.

Compared with the prior art, the double-layer sawtooth capacitor is embedded into the PCB inner layer below the chip and is combined with the discrete resistor and the BGA packaged pin, an attacker cannot perform any detection on a signal on the pin and cannot forge the signal even if the signal is detected, and any attempt of changing the physical environment of an external circuit board can cause the output result to be permanently invalid and cannot be reconstructed, so that the double-layer sawtooth capacitor has good anti-tampering and anti-counterfeiting effects. Moreover, the double-layer sawtooth capacitor structure not only can increase the capacitor density, but also can obtain enough manufacturing errors, so that the unique fingerprint information of the PCB is more difficult to imitate. The chip and the PCB are completely coupled into a complete and inseparable whole, so that the structure can realize the characteristics of tamper resistance and detection resistance, and above all, the structure can prevent intrusion attack damage, further realize complete semi-intrusion attack protection and realize the safety and credibility of a hardware system level.

Drawings

FIG. 1 is a diagram of an embedded capacitor architecture in combination with a BGA package chip;

FIG. 2 is a schematic perspective view of a double-layer sawtooth capacitor;

FIG. 3 is a coupling structure of the Arbiter PUF delay circuit and the RC delay circuit of the PCB;

wherein: 1-chip, 2-PUF circuit, 3-chip pin, 4-through hole A, 5-double-layer sawtooth capacitor, 6-upper printed copper trace, 7-lower printed copper trace, 8-substrate, 9-discrete resistor, 10-top printed circuit board, 11-through hole B, 12-through hole C, 13-bottom printed circuit board.

Detailed Description

The technical solution of the present invention is further specifically described below by embodiments with reference to the accompanying drawings, and as shown in fig. 1-2, the present invention provides a hybrid fingerprint extraction architecture based on the security of a PCB and a chip, the hybrid fingerprint extraction architecture mainly includes a PCB fingerprint extraction circuit structure on a Printed Circuit Board (PCB) and an on-chip PUF circuit structure inside the chip, as shown in fig. 1. The PCB fingerprint extraction circuit structure consists of an RC delay circuit; the PUF circuit inside the chip includes, but is not limited to, conventional PUF circuits implemented using arbiters, ROs, and the like. In the structure, a double-layer sawtooth capacitor is embedded in an inner layer of a PCB below a chip and is combined with a discrete resistor and a Pad pin of a BGA package, so that physical characteristics of an external PCB circuit board are coupled into a PUF circuit. By the mode, the coupling and corresponding relation between the state output of the PUF circuit and the integrity of the fingerprint extraction circuit of the PCB can be established, and any behavior of trying to forge, such as detaching the chip or destroying an external circuit, can destroy the relation between the chip and the PCB, so that the PUF output is permanently changed.

For first order RC delay circuits on printed circuit boards, the basic requirement is that they exhibit sufficient PCB manufacturing variations, and the capacitance values also need to be controlled within a reasonable range in view of matching with the on-chip delay signal. Larger capacitances cause the external delay circuit to have more significant delay variations than the internal PUF, which results in rapid degradation of response bias and increased PCB area consumption, and smaller capacitances make it difficult to extract sufficient PCB fingerprint features.

Therefore, we use metal copper to design a double layer saw-tooth capacitor 5, as shown in fig. 2. Copper wires are respectively attached to the double-layer capacitor circuit board, and have terminals so that they form a capacitor which is horizontally and vertically stacked, and a horizontal electric field and a vertical electric field are generated in the capacitor when the capacitor is charged. The copper wires are distributed in a zigzag shape and they surround each other in a small area. There are three such purposes: 1) Obtaining sufficient manufacturing tolerances; 2) The capacitance density is increased; 3) Increasing the difficulty of imitation. For resistors, discrete resistors are used because of their typically high manufacturing accuracy.

The capacitors and resistors constitute a PCB deviation extraction circuit, the main external deviation of which is contributed by the double layer saw tooth capacitance 5. It is embedded in the inner layer of the PCB board and laid out under the chip as shown in fig. 1. The through hole is connected with the pin of the chip, so that the PCB fingerprint characteristic signal is introduced into the chip, and the PUF is prevented from being attacked by chip intrusion and the operations of circuit board cloning, tampering and the like

The working process of the specific example is as follows:

the on-chip PUF adopted by the invention takes an Arbiter PUF circuit as an example to explain the security extraction structure of the mixed fingerprint. As shown in fig. 3, the Arbiter PUF circuit inside the chip is composed of an N-stage switch delay module and an Arbiter module; the switch delay module can be but is not limited to N (N is a positive integer greater than 1)Number) two-out-of-two multi-way switches are cascaded, and the N multi-way switches form two delay paths under the control of the N-bit excitation signal b, wherein the two delay paths comprise a delay path 1 and a delay path 2. Two paths pass through chip pins Pad ₀ ，Pad ₁ ，Pad ₂ And Pad ₃ The capacitor structure can obtain enough capacitance density, and further realize the process manufacturing deviation which is difficult to imitate. This allows a close coupling of the chip to the PCB board to be established, which in turn allows for a unique stimulus-response correspondence.

The specific working process is as follows: as shown in fig. 3, when an N-bit excitation signal b is input, the N multi-way switches form two delay paths, i.e., a delay path 1 and a delay path 2, under the control of the N-bit excitation signal b. Because the chip has unavoidable process deviation in the manufacturing process, delay signals generated by two delay paths which should be symmetrical under ideal conditions have certain deviation under working conditions, and thus two paths of different on-chip delay signals are generated. The PCB double-layer sawtooth capacitor is embedded into the PCB inner layer below the chip, and is combined with a discrete resistor and a chip pin of a Ball Grid Array (BGA) to form an RC delay circuit, and the RC delay circuit is respectively connected into a delay path 1 and a delay path 2 in the chip through the chip pin. N-stage switch delay module inside chip through chip pin Pad ₀ And Pad ₁ And the delay path 1 is formed by connecting the external RC delay circuit module. Through chip pin Pad ₂ And Pad ₃ And the delay path 2 is formed by connecting with an external RC delay circuit module. Due to the random process difference of a Printed Circuit Board (PCB) in the manufacturing process, two RC delay modules which are completely the same in design are different after being manufactured, two paths of different RC delay signals can be generated, the RC delay signals are superposed on the on-chip Arbiter PUF circuit delay signals, finally, the total delay signals are input to an Arbiter module in a chip, and the Arbiter module generates a digital response 0 or 1 according to the size of the total delay signals on two delay paths. Only 4 Pad pins and 2 external extensions are requiredA late line, 2 can be generated ^N And the consumption of external pins and resources is small for each excitation response pair.

The protective scope of the present invention is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present invention by those skilled in the art without departing from the scope and spirit of the present invention. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. The utility model provides a PCB-chip mixes safe extraction structure of fingerprint which characterized in that: the PUF circuit is arranged in the chip, the printed circuit board comprises a bottom printed circuit board and a top printed circuit board, and the fingerprint extraction circuit comprises a discrete resistor and an embedded capacitor; the fingerprint extraction circuit is connected in series with the PUF circuit inside the chip through the port of the chip.

2. The structure of claim 1, wherein the structure comprises: the chip is packaged by adopting a ball grid array packaging technology, and a plurality of chip pins are arranged outside the chip.

3. The structure for safely extracting the PCB-chip mixed fingerprint as claimed in claim 2, wherein: and the chip pins are connecting pins of the PUF circuit inside the chip and the top-layer printed circuit board.

4. A security extraction structure of PCB-chip hybrid fingerprint as claimed in claim 2, wherein: the top layer printed circuit board is provided with a through hole A, and the fingerprint extraction circuit is communicated with the chip pins through the through hole A and further connected with the PUF circuit in the chip.

5. The structure of claim 1, wherein the structure comprises: the PUF circuit is realized by an Arbiter or RO circuit.

6. The structure for safely extracting the PCB-chip mixed fingerprint as claimed in claim 2, wherein: the fingerprint extraction circuit comprises two discrete resistors and two embedded double-layer sawtooth capacitors, the two double-layer sawtooth capacitors are respectively connected with the two discrete resistors in series, and the fingerprint extraction circuit formed by each double-layer sawtooth capacitor and the discrete resistors is communicated with the chip through chip pins.

7. The structure of claim 6, wherein the structure comprises: the double-layer sawtooth capacitor comprises a two-layer structure arranged in parallel, and comprises an upper-layer capacitor circuit board and a lower-layer capacitor circuit board, wherein a plurality of upper-layer printed copper traces are arranged on the upper-layer capacitor circuit board, a lower-layer printed copper trace is arranged on the lower-layer capacitor circuit board, and the upper-layer printed copper traces and the lower-layer printed copper trace respectively comprise a plurality of copper traces which are attached to the surface of the capacitor circuit board and distributed in a sawtooth shape.

8. The structure of claim 6, wherein the structure comprises: the bottom layer printed circuit board is provided with a substrate, the double-layer sawtooth capacitor is arranged on the substrate, and the discrete resistor is arranged between the printed circuit board and the double-layer sawtooth capacitor.

9. The structure of claim 8, wherein the structure comprises: and the double-layer sawtooth capacitor is provided with a through hole B which penetrates through the capacitor, the substrate and the bottom printed circuit board, and is grounded through the through hole B.

10. The structure of claim 6, wherein the structure comprises: and the double-layer sawtooth capacitor is provided with a through hole C for penetrating the capacitor, and is connected with the discrete resistor circuit through the through hole C.