CN115623786A

CN115623786A - One-time programmable memory cell

Info

Publication number: CN115623786A
Application number: CN202210819607.7A
Authority: CN
Inventors: L·马索罗; P·卡伦佐
Original assignee: STMicroelectronics Rousset SAS
Current assignee: STMicroelectronics Rousset SAS
Priority date: 2021-07-13
Filing date: 2022-07-12
Publication date: 2023-01-17
Also published as: CN218244271U

Abstract

Embodiments of the present disclosure relate to one-time programmable memory cells including a transistor coupled to a capacitor. The transistor comprises at least one first conductive gate element arranged in at least one first trench formed in the semiconductor substrate; and at least one first channel portion buried in the substrate and extending at least at a first lateral surface level of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.

Description

One-time programmable memory cell

Cross Reference to Related Applications

The present application claims priority from french patent application No. 2107602, filed on 13/7/2021, the contents of which are incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic devices and more particularly to one-time programmable memories.

Background

Certain types of memory devices, particularly one-time programmable memory devices (OTP), operate by associating a transistor with a capacitive element. The memory cell (the oxide of the dielectric forming the capacitive element) comprises a natural state (after fabrication) with a given resistance, the relatively high given resistance defining a first state (arbitrarily 0). During the step of programming the cell to the second state (any 1), the transistor sends a signal that enables the oxide to be broken down, thereby making it conductive at a given resistance that is relatively low.

Current OTP memories occupy a table area of hundreds of square microns on the substrate of an electronic chip.

Furthermore, the resistance of the oxide of a "broken down" OTP memory cell is difficult to control. This may generate dispersion of resistance values between different memories of the same batch, which is not satisfactory.

There is a need for an OTP memory that can overcome, at least in part, one or more of the shortcomings of prior devices, such as the size of the OTP memory and/or the resistance dispersion of the oxide when it is damaged.

Disclosure of Invention

One embodiment can ultimately reduce the size of an OTP memory in part while using buried gate transistors. This results in an OTP memory cell of small size, e.g. less than 30 μm ² 。

One embodiment can at least partially improve the resistance dispersion of the oxide once broken down by concentrating the charge originating from the transistor during programming of the second state towards a specific location of the oxide of the capacitive element.

One embodiment provides a one-time programmable memory cell having: a transistor, comprising: at least a first conductive gate element disposed in at least a first trench formed in a semiconductor substrate; at least a first channel portion buried in the substrate and extending at the level of at least a first side surface of the first conductive gate element; and a capacitance element forming a memory element; the first channel portion is coupled to an electrode of a capacitive element.

In one embodiment, the first channel portion is formed according to a first doping type.

In one embodiment, the first channel portion is separated from the first conductive gate element by a first insulator layer.

In one embodiment, the capacitive element includes: a second insulator layer disposed on the first surface of the substrate; at least one second conductive element formed on the second insulator layer; and an electrode formed in the substrate according to the first doping type and preceding at least a portion of the second conductive element, the second insulator layer being at least partially disposed between the electrode and the second conductive element.

In one embodiment, the capacitive element includes a second portion formed in the substrate in contact with the second insulator and disposed between the electrode of the capacitive element and the first channel portion of the transistor, the second portion being formed according to a second doping type having a dopant concentration greater than a dopant concentration of the substrate.

In one embodiment, the transistor includes at least a channel bias portion disposed in contact with the first channel portion, the channel bias portion being formed according to a first doping type having a doping concentration greater than a doping concentration of the first channel portion, and the channel bias portion being separated from the first conductive gate element by a first insulator layer.

In one embodiment, the transistor includes at least one source formed in the substrate and disposed in contact with the first channel portion, the source being formed according to the second doping type and separated from the first conductive gate element by the first insulator layer.

In one embodiment, the memory cell further includes a third conductive element electrically insulated from the first conductive gate element and the substrate and at least partially disposed in the at least one first trench.

In one embodiment, the third conductive element is further arranged in the substrate and surrounds the at least one component formed by the transistor and the capacitive element.

In one embodiment, the third conductive element is coupled to an electrical ground.

In one embodiment, the first conductive gate element is further arranged in at least one second trench formed in the substrate, the first channel portion extending at least between the first trench and the second trench.

In one embodiment, the first channel portion further extends at the level of at least one second side surface of the first conductive gate element.

Additional embodiments provide an electronic device, comprising: at least such memory cells; and a control circuit configured to: a first voltage in the range of 5 to 15 volts is applied between the first conductive gate element and the source, and a second voltage in the range of 5 to 15 volts is applied between the first conductive gate element and the channel biasing portion.

In one embodiment, the control circuit is configured to apply a voltage greater than 5 volts between the second conductive element and the electrode of the capacitive element.

Drawings

The above features and advantages, and other features and advantages, are described in detail in the following description of specific embodiments, which is given by way of illustration and not of limitation with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates a circuit of an OTP memory cell in accordance with one embodiment;

FIG. 2 is a top view of an OTP memory cell according to one embodiment;

FIG. 3 is a perspective view of an OTP memory cell at the level of region A of FIG. 2;

FIG. 4 is a perspective view of an OTP memory cell at the level of region B of FIG. 2; and

FIG. 5 is a top view of an electronic device including four OTP memory cells according to one embodiment.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features that are common in the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional and material properties.

For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

Unless otherwise stated, when two elements connected together are referred to, this means directly connected without any intervening elements other than a conductor, and when two elements coupled together are referred to, this means that the two elements may be connected or they may have one or more other elements coupled.

In the following description, when referring to terms defining an absolute position, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or terms defining a relative position, such as the terms "above", "below", "upper", "lower", etc., or terms defining a direction, such as the terms "horizontal", "vertical", etc., it is referred to the orientation of the drawing sheet or the conventionally used position.

Unless otherwise indicated, the expressions "about", "substantially" and "approximately" mean within 10%, preferably within 5%.

Fig. 1 schematically shows an OTP memory cell.

The OTP memory cell includes a transistor 10 and a capacitive element 30 (forming a memory element) coupled in series between power supply voltage rails. Transistor 10 is, for example, a MOS transistor that includes source, drain, gate, and substrate contacts. The source of the transistor 10 is coupled, for example, to a first voltage rail, which is, for example, at a reference potential V _S Such as ground. The substrate contact is also coupled to the source, for example. Thus, the substrate potential V _B For example equal to ground potential. The transistor drain is for example coupled to an intermediate node 20 between the transistor 10 and the capacitive element 30, for example to pass the output voltage V of the OTP _{OTP_OUT} . The capacitive element 30 for example comprises a first electrode coupled to the intermediate node 20 and a second electrode coupled to a second voltage rail, for example at a supply potential V of the OTP memory cell _CAPA 。

Before the step of breaking down the oxide of the capacitive element, the gate, the source and the channel bias range of the transistor 10 are for example all at the same potential, for example 0 volt, i.e. ground. In other words, the voltage V _G 、V _S And V _B For example equal to 0 volts with respect to ground. Applied across the capacitive element, i.e. at V _CAPA The voltage between the intermediate node 20 and the intermediate node is also kept at zero, for example.

In one example, to be able to break down the oxide of the capacitive element 30, the voltage V is applied _CAPA Taking a programmed value, e.g. equal to or greater than 5 volts, the voltage V _G Taken as the activation value of the transistor 10, which is for example greater than 5 volts and in the range from 5 volts to 15 volts, and the voltage V _S And V _B Held at, for example, 0 volts.

For example, the read-out phase comprises a measurement terminal V _CAPA And V _{OTP_OUT} The resistance between. If no breakdown step occurs, the resistance is higher. If a breakdown step occurs, the resistance is lower. For example, the voltage V _CAPA Is taken to a read value, for example equal to 2 volts, and by activating transistor 10, voltage V _{OTP_OUT} Level and terminal V _CAPA And V _{OTP_OUT} And thus the programmed state of the OTP cell.

FIG. 2 is a top view of an embodiment of an OTP memory cell, e.g., incorporating the circuit of FIG. 1.

The transistor 10 comprises at least one first conductive gate element 101. In other words, the first conductive gate element 101 forms the gate of the transistor 10. In the example of fig. 2, the first conductive gate element 101 is formed in the first trench 102 and the second trench 107, the first trench 102 and the second trench 107 themselves being formed in the semiconductor substrate 25. Although the first conductive gate element 101 is formed in two trenches, in other embodiments, the first conductive gate element 101 is formed in a single trench, such as the first trench 102 or the second trench 107. The fact of having the first conductive gate element 101 formed in the first trench 102 and the second trench 107 can increase the surface area of the channel of the transistor 10.

In one example, the first conductive gate element 101 has a width dimension, i.e., a width substantially parallel to the first surface of the substrate 25, that is less than a dimension extending in a depth direction in the trench. This makes it possible to limit the size of the OTP memory cell and also makes it possible to simplify the breakdown of the oxide of the capacitive element 30 by increasing the generated current. Electrical contact on the first conductive gate element 101 occurs at the level of the contact 101d arranged over the first surface of the substrate 25 through the passivation oxide present at the surface of the substrate 25. The first conductive gate element 101 is surrounded by a first insulating layer 104 in the first trench 102 and/or in the second trench 107 to electrically insulate it from the substrate and/or other conductors. In one example, the first insulator layer 104 has a thickness in a range from 35 to 45 nanometers.

In this specification, the first surface of the substrate 25 similarly refers to the outer surface of the substrate or the surface of the passivating oxide that may be present at the surface of the substrate, and which is oriented towards the substrate 25.

In one example, the first insulator layer 104 is formed of silicon oxide or silicon nitride.

In one example, the first conductive gate element 101 is formed of polysilicon.

In one example, the length Lg of the first conductive gate element 101 is in a range from 3 to 4 microns, which length extends parallel to the first surface of the substrate 25.

In one example, the width Lrg of the first conductive gate element 101 is in a range from 0.4 to 0.8 microns.

In the example of fig. 2, the transistor 10 further includes a first channel portion 103. In other words, the channel of the transistor 10 is formed by the first channel portion 103. The first channel portion 103 is buried in the substrate 25 and extends, for example, at the level of at least the first side surface 101a of the first conductive gate element 101. The side surface 101a is, for example, substantially oriented such that a normal to the side surface 101a is parallel to the first surface of the substrate 25. The term "buried" means that the first channel portion 103 extends in depth in the substrate. In other words, the first channel portion 103 forms a three-dimensional structure having a substantially rectangular or square shape with two surfaces parallel to the first surface of the substrate and the length of the first conductive gate element 101. The height of the rectangular shape is, for example, equal to the height of the first conductive gate element 101. In one example, the overall shape of the first channel portion 103 is similar to the shape of the first conductive gate element 101.

In one example, the first channel portion 103 has a first P doping type with a dopant concentration from 7x10 ¹⁹ To 2x10 ²⁰ at.cm ^-3 Within the range of (1). However, the skilled person may modify the different doping types based on their knowledge, for example selecting according to the doping type of the substrate 25. Dopants such as aluminum, boron, gallium or indium may be used, for example, as P-dopants for silicon substrates.

In the example of fig. 2 having a structure with two

trenches

102, 107 and a first conductive gate element 101 arranged in the first and second trenches 107, the first channel portion 103 extends, for example, at least between the first trench 102 and the second trench 107. The first channel portion 103 may, for example, similarly, extend further with respect to the first surface 101a at the level of the at least one second side surface 101b of the first conductive gate element 101. This enables further increase of channel conduction to mitigate the breakdown step of the oxide of the capacitive element 30.

In one example, the substrate 25 is doped according to a first P doping type. In another example, the substrate 25 is doped according to a second N doping type. In the rest of the description, the case of an N-type substrate is taken as an example. However, one skilled in the art may modify the different doping types according to the selected doping type of the substrate 25 based on their knowledge. Substrate 25 may be formed of silicon, germanium, a carbide such as SiC, a nitride such as GaN, or another semiconductor known to those skilled in the art. Dopants such as phosphorus or antimony may be used for N-doping of silicon.

In the example of fig. 2, the transistor 10 includes at least one channel biasing portion 106, the at least one channel biasing portion 106 corresponding to a substrate contact and being arranged in contact with the first channel portion 103. One or more contacts 106a disposed at the surface of substrate 25 can be at a potential Vs/V _B (two contact points areShort) to bias the channel bias portion 106.

If the first channel portion 103 is arranged in a plurality of positions as shown in the example of fig. 2, a plurality of channel bias portions 106 may be formed.

In one example, the channel biasing portion 106 is formed according to a first P doping type, wherein the dopant concentration is, for example, greater than the dopant concentration of the first channel portion 103.

In one example, the channel bias portion 106 has a width of from 1x10 ¹⁷ To 5x10 ¹⁷ at.cm ^-3 A dopant concentration within a range.

In one example, the channel biasing portion 106 is separated from the first conductive gate element 101 by the first insulator layer 104.

In the example of fig. 2, the transistor 10 includes a source 108, the source 108 being formed in the substrate 25 and arranged to be in contact with the first channel portion 103. If the first channel portion 103 is arranged in a plurality of positions as shown in the example of fig. 2, a plurality of sources 108 may be formed.

In one example, the source 108 is formed according to a second N doping type. In one example, the dopant concentration of the source is greater than the dopant concentration of the substrate 25.

In the example of fig. 2, the source 108 is separated from the first conductive gate element 101 by the first insulator layer 104.

In one example, one or more contacts 108a disposed at a surface of substrate 25 can couple a potential V _S Is applied to the source 108.

In the example of fig. 2, different channel biasing portions 106 of the same transistor 10 may be connected to each other by conductive tracks 106 c.

In the example of fig. 2, the different sources 108 of the same transistor 10 may be connected together by conductive tracks 108 c.

In the example of fig. 2, different first conductive gate elements 101 of the same transistor 10 may be connected by conductive tracks 101 c.

In the example of fig. 2, the OTP memory cell also optionally includes a third conductive element 400. The third conductive element 400 is electrically insulated from the first conductive gate element 101 and the substrate 25. The third conductive element 400 is, for example, at least partially disposed in the first trench 102 and, if present, the second trench 107, at least partially disposed in the second trench 107.

The third conductive element 400 is, for example, a field plate. It is made of, for example, polysilicon.

In the example of fig. 2, the third conductive element 400 is arranged at least below the first conductive gate element 101, i.e. at the bottom of the

trenches

102, 107. In other words, the first conductive gate element 101 is arranged between the third conductive element 400 and the first surface of the substrate 25. This can limit the effect of the high voltage generated by gate 101 on the rest of substrate 25.

In one example, the third conductive element 400 is coupled to electrical ground. This can improve the isolation of the OTP memory cell from electrical interference and/or isolate the remainder of substrate 25 from the high voltage generated by the components of the OTP memory cell.

In the example of fig. 2, a third conductive element 400 is further arranged in the substrate 25 to surround at least one component formed by the transistor 10 and the capacitive element 30 of the OTP memory cell. In one example, in portions of the

trenches

102, 107 where the third conductive element 400 is not formed, the third conductive element 400 extends, for example, from the first surface of the substrate 25 down to a depth equal to the trench depth.

A contact 400a may be formed on the first surface of the substrate 25 to enable biasing the third conductive element 400 to ground, for example.

The use of this third conductive element 400 further enables the size of the OTP memory cell on the substrate 25 to be limited. In fact, the use of an isolation trench coupled with an isolation well connection is subsequently avoided, considering that the isolation trench takes up more space.

In the example of fig. 2, the OTP memory cell further includes a capacitive element 30 for forming the memory element.

The first channel portion 103 is coupled to an electrode of a capacitive element 30 located, for example, in the substrate 25. In other words, the drain of the transistor 10 is formed by the portion of the substrate 25 located between the first channel portion 103 and the electrode of the capacitive element 30 formed in the substrate 25. This enables the charge originating from the first channel portion 103 to be guided to the oxide of the capacitance element 30. The term "coupled" here means that the first channel portion 103 can transfer charges and/or potentials to the electrodes of the capacitive element either directly or indirectly via the second optional portion 304.

In the example of fig. 2, the capacitive element 30 includes a second insulator layer 301 disposed on the first surface of the substrate 25. The term "insulating layer" is synonymous with the term oxide. In other words, the second insulator layer 301 is broken down after programming. The term "over 8230that is used herein means that the second insulator layer 301 (in other words, an oxide) may be formed over and in contact with the first surface of the substrate 25, or at the same level as the first surface of the substrate 25, or below but in contact with the first surface of the substrate, for example. In one example, the second insulator layer 301 may be formed of silicon dioxide. In one example, the thickness of the second insulator layer 301 is in a range from 5 nanometers to 10 nanometers, and is, for example, about 6 or 7 nanometers.

Capacitive element 30 also includes a second conductive element 302 formed on second insulator layer 301. The second conductive element 302 forms one of the two electrodes of the capacitive element 30. The second conductive element 302 is formed of, for example, polysilicon. In one example, the second conductive element 302 is formed to protrude with respect to the substrate 25. The contact 302a may be formed to apply a potential V to the second conductive element 302 _CAPA 。

The capacitive element 30 further comprises an electrode 303. In one example, the electrode is formed in substrate 25 according to a first P doping type. In one example, the dopant concentration of the electrode 303 is greater than the dopant concentration of the channel 103. For example, the dopant concentration of the electrode 303 is from 1x10 ¹⁹ To 7x10 ¹⁹ at.cm ^-3 In the presence of a surfactant. In one example, the electrode 303 is formed before at least a portion of the second conductive element 302.

In one example, a second insulator layer 301 (e.g., an oxide layer) is at least partially disposed between the electrode 303 and the second conductive element 302. In the example of fig. 2, in a top view, the second insulator layer 301 extends along the first surface of the substrate 25, beyond the second conductive element 302 by a distance E in the range from 0.4 to 1 micron, and beyond the electrode 303 toward the transistor 10. This enables copying of the contacts for reading from the memory cell. In another example, the second insulator layer 301 is limited to the physical extension of the second conductive element 302 along the first surface of the substrate 25.

A contact 303a may be formed through the substrate 25 and the second insulator layer 301 to detect the potential V on the second conductive element 303 _OTP-OUT 。

In the example of fig. 2, the capacitive element 30 optionally includes a second portion 304 formed in the substrate 25. In one example, the second portion 304 is in contact with the second insulator 301 and, for example, with the electrode 303. For example, the second portion 304 is arranged between the electrode 303 of the capacitive element 30 and the first channel portion 103 of the transistor 10. In the example of fig. 2, the extension of the second portion 304 is limited along the first surface of the substrate 25 to a width Le that is less than the width Lec of the second conductive element 302. This facilitates concentrating the charge originating from the first channel portion 103 at the level of the second portion 304, and/or at the level of the interface between the second portion 304 and the conductive element 302, so that the resistance of the second insulator layer 301 after breakdown can be accurately and reproducibly obtained. The second portion 304 and the conductive element 302 may thus be considered to be the same electrode.

To improve the charge concentration at the level of the second portion 304, the second portion is formed, for example, according to a second N doping type, wherein the dopant concentration is greater than the dopant concentration of the substrate 25. In one example, the dopant concentration of the second portion 304 is from 1x10 ¹⁹ To 7x10 ¹⁹ at.cm ^-3 In the presence of a surfactant. The doping type or concentration may be modified by a person skilled in the art, for example, depending on the substrate doping, or depending on the doping of the electrode 303, or the doping of the first channel portion 103.

In the example of fig. 2, the second portion 304 is spaced apart from the first channel portion 103 in the substrate 25 by a distance S of about 0.5 microns. In this example, the second portion 304 may be disposed before and/or at a similar depth with respect to at least a portion of the first channel portion 103. This enables further improvement of the charge concentration towards the second portion 304 when breaking down the oxide 301. It is possible to precisely control which portion of the oxide is broken down.

FIG. 3 is a simplified perspective view of an embodiment of an OTP memory cell at the level of region A of FIG. 2, with the substrate made transparent for better understanding.

Fig. 3 enables, among other things, to see the arrangement between the gate 101 and this conductive element 400 at the level of the trench 102.

The first conductive gate element 101 is arranged in an upper portion of the first trench 102. The edges of the first trench 102 are covered by a first insulator layer 104. A first insulator layer 104 is also disposed in the upper portion of the trench, on the right side of the gate 101 in fig. 3. This enables the gate 101 to be insulated from the channel bias portion 106 and/or the source 108.

In fig. 3, it can be seen that the first channel portion 103 is arranged along substantially the same depth as the first conductive gate element 101.

In one example, the first channel portion 103 extends a depth Dc of 0.5 to 1.5 microns relative to the first surface of the substrate.

In fig. 3, it can be seen that the third conductive element 400 is arranged in a lower portion, i.e. a deeper portion, of the first trench 102. The depth Dpf of the third conductive element 400 is, for example, in the range from 1.5 to 2.5 micrometers. The third conductive element 400 is electrically insulated from the first conductive gate element 101 by a first insulator layer 104, the first insulator layer 104 extending substantially parallel to the first surface of the substrate 25 between the first conductive gate element 101 and the third conductive element 400. The conductive element 400 is also insulated from the substrate 25 by the first insulator layer 104.

In one example, the height of the first conductive gate element 101 (in other words, the depth Dg with respect to the first surface of the substrate 25) is in a range from 0.5 to 1.5 micrometers.

FIG. 4 is a simplified cross-sectional view of an embodiment of an OTP memory cell at the level of region B of FIG. 2 and as seen from the right in the orientation of FIG. 2.

Fig. 4 can have an example of the arrangement of the second insulator layer 301 relative to the first surface of the substrate 25.

The first conductive gate element 101 and the third conductive element 400 are illustrated in dashed lines because they are retracted. The second portion 304 is partially disposed vertically with the second conductive element 302. The second insulator layer 301 extends beyond the second portion 304 and the second conductive element 302. In the example of fig. 4, the second portion 304 is thinner than the electrode 303 and is in contact with the second insulator layer 301. The thickness Ec of the second portion 304 is, for example, in the range from 100 to 500 nanometers.

In the example of fig. 4, a portion of the second insulator layer 301 located furthest to the right in the figure may be thicker and deeper in the substrate 25, for example, relative to its thickness at the level of the second portion 304. This enables the memory cell to be electrically insulated.

In the example of fig. 4, the first channel portion 103 is separated from the second portion 304 by a portion of the substrate 25.

When a voltage V is applied to the gate 101 _G E.g. greater than 5 volts, and a voltage V _S And V _B For example, a voltage V equal to 0 is maintained and applied to the outer electrode 302 _CAPA E.g., greater than 5 volts, a significant amount of charge is generated in the first channel portion 103 along the height of the first channel portion 103, which extends in front of the first conductive gate element 101. These charges are then concentrated on a second portion 304 having dimensions reduced with respect to the second insulating layer 301 and with respect to the second conductive element 302 forming the external electrode of the capacitive element 30, as indicated by the arrows in fig. 4. These reduced dimensions and/or higher dopant concentrations relative to the dopant concentration of substrate 25 at the level of second portion 304 enable accurate positioning of the charge and control of the area where oxide 301 is broken down. The resulting resistance dispersion is therefore limited.

The amount of charge is proportional to the surface formed by all vertical surfaces of the first channel portion 103 before the first conductive gate element 101. This charge generation surface is vertical, which can significantly reduce the volume of the OTP memory cell, as opposed to a transistor where the channel is formed only at the surface.

In the example of fig. 4, the capacitive element further comprises a portion 303b doped according to the first P doping type, the portion 303b being arranged in contact with the electrode 303 and being formed in the substrate 25 below the electrode 303. This portion 303b enables the cells to be electrically isolated due to the well and the state of each memory cell to be read.

Fig. 5 illustrates in top view an electronic device 500 comprising four OTP memory cells such as described in the previous example. Other examples of electronic device 500 that are not illustrated may include from one to hundreds of OTP memory cells such as described in the previous examples.

In the example of fig. 5, the OTP memory cells are each surrounded by a third conductive element 400. This enables the OTP memory cells to be insulated from each other and from possible external interference. Between two adjacent memory cells, there is a single third conductive element 400. In other words, a single third conductive element 400 is common to two adjacent OTP memory cells. This enables the size of the OTP memory cell on substrate 25 to be limited. Such an electronic device 500 has a small size and a controlled oxide resistance.

The electronic device 500 further includes, for example, a control circuit CTRL configured to apply, during a programming operation of one or more OTP memory cells, a corresponding gate voltage according to a value of a data bit to be stored in each cell. In the example of FIG. 5, four gate voltages V _G1 、V _G2 、V _G3 And V _G4 The four OTP cells are controlled separately by a circuit CTRL. In some cases, circuit CTRL is further configured to generate voltage V _CAPA Voltage V of _CAPA Is, for example, a voltage common to all cells, and/or receives an output voltage V of one or more OTP memory cells during a sensing phase _{OTP_OUT1} 、V _{OTP_OUT2} 、V _{OTP_OUT3} And V _{OTP_OUT4} 。

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

Finally, the actual implementation of the described embodiments and variants is within the abilities of a person skilled in the art based on the functional indications given above. In particular, the doping types shown may be interchanged and adjusted by those skilled in the art.

Claims

1. A one-time programmable memory cell, comprising:

a transistor, comprising:

at least one first conductive gate element disposed in at least a first trench formed in a semiconductor substrate; and

at least a first channel portion buried in the semiconductor substrate and extending parallel to at least one first side surface of the at least one first conductive gate element; and

a capacitive element forming a memory element;

wherein the at least one first channel portion is coupled to an electrode of the capacitive element.

2. The memory cell of claim 1, wherein the at least one first channel portion is doped with a first doping type.

3. The memory cell of claim 2, wherein the at least one first channel portion is separated from the at least one first conductive gate element by a first insulator layer.

4. The memory cell of claim 3, wherein the capacitive element comprises:

a second insulator layer disposed on the first surface of the semiconductor substrate;

at least one second conductive element formed on the second insulator layer; and

an electrode formed in the semiconductor substrate according to the first doping type,

wherein the second insulator layer is at least partially disposed between the electrode and the at least one second conductive element.

5. The memory cell of claim 4, wherein the capacitive element includes a second portion formed in the semiconductor substrate in contact with the second insulator layer and disposed between the electrode of the capacitive element and the at least one first channel portion of the transistor;

wherein the second portion is doped with a second doping type having a dopant concentration greater than a dopant concentration of the semiconductor substrate.

6. The memory cell of claim 5, wherein the transistor comprises at least a channel bias portion disposed in contact with the at least one first channel portion;

wherein the channel biasing portion is doped with a first doping type having a dopant concentration greater than a dopant concentration of the at least one first channel portion, and the channel biasing portion is separated from the at least one first conductive gate element by the first insulator layer.

7. The memory cell of claim 6, wherein the transistor comprises at least one source formed in the semiconductor substrate and disposed in contact with the at least one first channel portion;

wherein the source is doped with the second doping type and is separated from the at least one first conductive gate element by the first insulator layer.

8. The memory cell of claim 1, further comprising a third conductive element electrically insulated from the at least one first conductive gate element and the semiconductor substrate and at least partially disposed in the at least one first trench.

9. The memory cell of claim 8, wherein the third conductive element is further disposed in the semiconductor substrate and surrounds at least one component formed by the transistor and the capacitive element.

10. The memory cell of claim 8, wherein the third conductive element is coupled to electrical ground.

11. The memory cell of claim 1, wherein the at least one first conductive gate element is further arranged in at least one second trench formed in the semiconductor substrate, and

wherein the at least one first channel portion extends at least between the first trench and the second trench.

12. The memory cell of claim 1, wherein the at least one first channel portion further extends at a level of at least one second side surface of the at least one first conductive gate element.

13. The memory cell of claim 1, wherein the coupling of the at least one first channel portion to the electrode of the capacitive element is comprised of a portion of the semiconductor substrate.

14. An electronic device, comprising:

at least one OTP memory cell comprising:

a transistor, comprising:

a capacitive element forming a memory element;

wherein the at least one first channel portion is coupled to an electrode of the capacitive element; and

a control circuit configured to: a first voltage in the range of 5 to 15 volts is applied to the at least one first conductive gate element and a second voltage in the range of 5 to 15 volts is applied between the at least one first conductive gate element and the channel biasing portion.

15. The device of claim 14, wherein the control circuit is further configured to apply a voltage greater than 5 volts between the second conductive element and an electrode of the capacitive element.

16. The device of claim 14, wherein the capacitive element comprises:

an insulator layer disposed on a first surface of the semiconductor substrate;

an electrode formed in the semiconductor substrate and before at least a portion of the at least one second conductive element according to a first doping type,

wherein the insulator layer is at least partially disposed between the electrode and the at least one second conductive element.

17. The device of claim 16, wherein the capacitive element includes a second portion formed in the semiconductor substrate in contact with the insulator layer and disposed between the electrode of the capacitive element and the at least one first channel portion of the transistor;

wherein the second portion is doped with a dopant concentration greater than a dopant concentration of the semiconductor substrate.

18. The device of claim 17, wherein the transistor includes at least one channel biasing portion disposed in contact with the at least one first channel portion;

wherein the channel bias portion is doped with a dopant concentration greater than a dopant concentration of the at least one first channel portion and is separate from the at least one first conductive gate element.

19. The device of claim 18, wherein the transistor comprises at least one source formed in the semiconductor substrate and arranged in contact with the at least one first channel portion;

wherein the source is separate from the at least one first conductive gate element.

20. The device of claim 14, further comprising a third conductive element coupled to electrical ground and electrically insulated from the at least one first conductive gate element and the semiconductor substrate and at least partially disposed in the at least one first trench.

21. The device of claim 20, wherein the third conductive element is further disposed in the semiconductor substrate, and the third conductive element surrounds at least one component formed by the transistor and the capacitive element.