CN115620762A - Memory system and memory access interface device thereof - Google Patents

Memory system and memory access interface device thereof Download PDF

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Publication number
CN115620762A
CN115620762A CN202110807461.XA CN202110807461A CN115620762A CN 115620762 A CN115620762 A CN 115620762A CN 202110807461 A CN202110807461 A CN 202110807461A CN 115620762 A CN115620762 A CN 115620762A
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China
Prior art keywords
signal
data
data strobe
strobe signal
read
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CN202110807461.XA
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Chinese (zh)
Inventor
蔡福钦
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202110807461.XA priority Critical patent/CN115620762A/en
Publication of CN115620762A publication Critical patent/CN115620762A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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Abstract

The invention provides a memory access interface device. The clock generation circuit generates a reference clock signal. The pseudo data strobe signal generating circuit receives the reference clock signal, delays a read enable signal from the memory access controller to enable the output of the reference clock signal, and thereby generates the pseudo data strobe signal. The true data strobe signal generating circuit receives a data strobe signal from the memory device, delays the read enable signal to enable the output data strobe signal, thereby generating a true data strobe signal. The data reading circuit samples the data signal from the memory device according to the sampling signal to generate and transmit a read data signal to the memory access controller. The selection circuit selects the dummy data strobe signal and the true data strobe signal as sampling signals in the single data transfer rate mode and the double data transfer rate mode, respectively.

Description

Memory system and memory access interface device thereof
Technical Field
The present invention relates to memory technologies, and in particular, to a memory system and a memory access interface device thereof.
Background
Early memories were commonly low speed Single Data Rate (SDR) memories. However, as product bandwidth requirements have increased, the speed requirements have not been met using conventional single data transfer rate memories. Therefore, double Data Rate (DDR) memories have been proposed to break through the speed limitation.
Under the architecture, increasingly high speed double data rate memory technology is proposed. However, controllers on the market are required to be able to support all speed modes. How to design a memory access interface device that can be applied to a single data transfer rate memory and a double data transfer rate memory at the same time is a problem that needs to be solved urgently.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a memory system and a memory access interface device thereof, so as to improve the prior art.
One objective of the present invention is to provide a memory access interface device, which comprises: the circuit comprises a clock generating circuit, a pseudo data strobe signal generating circuit, a true data strobe signal generating circuit, a data reading circuit and a selecting circuit. The clock generation circuit is configured to generate a reference clock signal. The pseudo data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from the memory access controller to enable the output reference clock signal to generate the pseudo data strobe signal according to an enable section of the read enable signal. The true data strobe signal generating circuit is configured to receive a data strobe signal from the memory device and delay the read enable signal to enable the output data strobe signal to generate a true data strobe signal according to an enable section of the read enable signal. The data reading circuit is configured to sample a data signal from the memory device according to the sampling signal, generate and transmit a read data signal to the memory access controller. The selection circuit is configured to select the dummy data strobe signal as the sampling signal in the single data transfer rate mode and select the true data strobe signal as the sampling signal in the double data transfer rate mode.
It is another object of the present invention to provide a memory system, comprising: memory access controller, memory device and memory access interface device. The memory access interface device includes: the circuit comprises a clock generating circuit, a pseudo data strobe signal generating circuit, a true data strobe signal generating circuit, a data reading circuit and a selecting circuit. The clock generation circuit is configured to generate a reference clock signal. The pseudo data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from the memory access controller to enable the output of the reference clock signal according to an enable section of the read enable signal to generate a pseudo data strobe signal. The true data strobe signal generation circuit is configured to receive a data strobe signal from the memory device and delay the read enable signal to enable the output data strobe signal according to an enable section of the read enable signal to generate a true data strobe signal. The data reading circuit is configured to sample a data signal from the memory device according to the sampling signal, generate and transmit a read data signal to the memory access controller. The selection circuit is configured to select the dummy data strobe signal as the sampling signal in the single data transfer rate mode and select the true data strobe signal as the sampling signal in the double data transfer rate mode.
The features, operation and efficacy of the present invention will now be described in detail with reference to the preferred embodiments illustrated in the accompanying drawings.
Drawings
FIG. 1 is a block diagram illustrating a memory system according to one embodiment of the present invention;
FIG. 2 is a block diagram illustrating the medium memory access interface device of FIG. 1 in greater detail according to one embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating signals associated with the operation of the pseudo data strobe signal generating circuit according to one embodiment of the present invention;
FIG. 4 is a waveform diagram illustrating signals associated with operation of a true data strobe signal generation circuit according to an embodiment of the present invention; and
fig. 5 is a diagram illustrating a timing relationship between a data signal and a sampling signal according to an embodiment of the invention.
Detailed Description
An object of the present invention is to provide a memory system and a memory access interface device thereof, which can realize the access of a memory device with accurate timing in a low cost manner no matter whether the memory device is a single data transfer rate memory or a double data transfer rate memory.
Please refer to fig. 1. FIG. 1 is a block diagram illustrating a memory system 100 according to an embodiment of the invention. Memory system 100 includes a memory access controller 110, a memory access interface device 120, and a memory device 130.
The memory system 100 may be electrically coupled to other modules, such as, but not limited to, a system bus (not shown). For example, the memory system 100 may be electrically coupled to a processor (not shown) via a system bus to enable the processor to access the memory system 100.
In one embodiment, the memory access interface device 120 may be, for example, but not limited to, a physical layer circuit.
Memory device 130 is a single data transfer rate memory or a higher speed double data transfer rate memory.
External access signals, such as access signals from a processor, may be received by the memory access controller 110 and then sent to the memory access interface device 120. Further, the access signal may be transmitted from the memory access interface device 120 to the memory device 130, or may be used as a reference signal in the memory access interface device 120 to access the memory device 130.
In detail, in one embodiment, the memory access controller 110 may receive and transmit access signals, wherein the access signals may include, for example, but not limited to, a read enable signal REN, a command signal CMD, and an address signal access command ADD.
Based on the signals, the memory access interface device 120 may drive (activate) the memory device 130, receive the data signal DQ from the driven memory device 130, sample the data signal DQ to generate the read data signal RDQ, and transmit the RDQ to the memory access controller 110.
When the memory device 130 is a single data transfer rate memory, the memory access interface device 120 receives only the data signal DQ from the memory device 130 being driven, and samples the data signal DQ according to signals generated internally by the memory access interface device 120. When the memory device 130 is a double data rate memory, the memory access interface device 120 may receive the data signal DQ and the data strobe signal DQs from the driven memory device 130 and sample the data signal DQ according to the data strobe signal DQs.
Therefore, the internal data stored in the memory device 130 can be accessed according to the correct timing of the signals.
Memory access interface device 120 actually includes a receiver RX and a transmitter TX. The transmitter TX receives command signals CMD and address signal access commands ADD and transmits the command signals to the memory device 130 to drive the memory device 130, so that the memory device 130 transmits data signals DQ to the memory access interface device 120. The receiver RX may receive the read enable signal REN and generate a related sampling signal according to different types of memory devices 130 (i.e. single data rate memory or double data rate memory), so as to sample the data signal DQ and complete the access operation of the memory device 130.
The following paragraphs will describe the structure and operation of the receiver RX in detail.
Please refer to fig. 2. FIG. 2 is a block diagram illustrating the memory access interface device 120 of FIG. 1 in more detail according to an embodiment of the present invention. It is noted that in fig. 2, only the receiver RX of the memory access interface device 120 is shown, and the transmitter TX is not shown. In detail, in one embodiment, each circuit element shown in fig. 2 is disposed in the receiver RX.
The memory access interface device 120 includes a clock generation circuit 200, a dummy data strobe signal generation circuit 210, a true data strobe signal generation circuit 220, a data read circuit 230, and a selection circuit 240.
The clock generation circuit 200 is configured to generate a reference clock signal CMDCLK. In one embodiment, the clock generation circuit 200 includes a clock source circuit 205A and a frequency divider circuit 205B. Clock source circuitry 205A includes, for example, but not limited to, a phase-locked loop and is configured to generate source clock signal SCLK. Wherein the source clock signal SCLK may be selectively shared with the transmitter TX of fig. 1. The frequency divider circuit 205B is configured to divide the source clock signal SCLK to generate the reference clock signal CMDCLK. In one embodiment, each circuit within the receiver RX is adapted to receive and operate according to the frequency of the reference clock signal CMDCLK.
The dummy data strobe signal generation circuit 210 is configured to receive the reference clock signal CMDCLK and delay the read enable signal REN from the memory access controller 110 to enable the output of the reference clock signal CMDCLK according to an enable section of the read enable signal REN, thereby generating a dummy data strobe signal FDQS.
The true data strobe signal generation circuit 220 is configured to receive the data strobe signal DQS from the memory device 130 being driven and delay the read enable signal REN to enable the output data strobe signal DQS according to an enable section of the read enable signal REN, thereby generating the true data strobe signal TDQS.
The data read circuit 230 is configured to sample the data signal DQ from the driven memory device 130 according to the sampling signal SS, generate and transmit a read data signal RDQ to the memory access controller 110.
The selection circuit 240 is configured to select the dummy data strobe signal FDQS as the sampling signal SS in the single data transfer rate mode and select the true data strobe signal TDQS as the sampling signal SS in the double data transfer rate mode.
In one embodiment, the selection circuit 240 operates in the single data transfer rate mode when the memory device 130 is a single data transfer rate memory, and the selection circuit 240 operates in the double data transfer rate mode when the memory device 130 is a double data transfer rate memory.
Please refer to fig. 3. FIG. 3 is a waveform diagram illustrating signals related to the operation of the pseudo data strobe signal generating circuit 210 according to an embodiment of the present invention.
In the case where the memory device 130 is a single data transfer rate memory, the driven memory device 130 transfers only the data signal DQ to the data reading circuit 230 without transferring the data strobe signal DQs. In this case, the dummy data strobe signal generation circuit 210 is configured to generate the dummy data strobe signal FDQS such that the selection circuit 240 operating in the single data transfer rate mode selects the dummy data strobe signal FDQS as the sampling signal SS.
As shown in fig. 3, the dummy data strobe signal generation circuit 210 delays the read enable signal REN to generate a delayed read enable signal REND. The enable section SEN in the read enable signal REN will also be delayed accordingly and used to enable the output reference clock signal CMDCLK. In detail, the dummy data strobe signal generating circuit 210 will only allow the reference clock signal CMDCLK to be output at the portion of the corresponding enable section SEN as the dummy data strobe signal FDQS.
In one embodiment, the start timing TF1 of the dummy data strobe signal FDQS corresponds to the arrival timing TF2 at which the memory device 130 transmits the data signal DQ to the data reading circuit 230.
In detail, when the memory access interface device 120 performs a read operation on the memory device 130, the required time includes the time when the command signals CMD and the address signals ADD in fig. 1 are transmitted to the memory device 130 through the transmitter TX of the memory access interface device 120, the time when the memory device 130 is processed to retrieve corresponding data from a corresponding address, and the time when the memory device 130 transmits the data signals DQ to the data read circuit 230 through a line.
Therefore, the dummy data strobe signal generation circuit 210 requires a timing corresponding to the sum of the time that the read enable signal REN is delayed and the time that the dummy data strobe signal FDQS is generated to correspond to the timing corresponding to the total time of the above-described operations.
It should be noted that the term "corresponding" refers to that the timings of the two may have a difference within an allowable range without causing an error in the access operation, and are not necessarily completely equal.
In one embodiment, the time length TL of the enable section SEN corresponding to the read enable signal REN of the dummy data strobe signal generating circuit 210 corresponds to the data length DL of the data signal DQ. In detail, the length of time that the enable section SEN is generated is such that the generated dummy data strobe signal FDQS is sufficient to sample all the data contents included by the data signal DQ. In the example of fig. 3, the data signal DQ includes two data items DA and DB. The length of time that the enable section SEN is required to have the dummy data strobe signal FDQS with two sampling periods. The selection circuit 240 causes the data read circuit 230 to sample the data DA and DB, respectively, according to the sampling signal SS after selecting the dummy data strobe signal FDQS as the sampling signal SS.
Similarly, the term "corresponding" refers to that the time length TL and the data length DL may have a difference within an allowable range without causing an access operation error, and are not necessarily completely equal.
Please refer to fig. 4. FIG. 4 is a waveform diagram illustrating signals associated with the operation of the true data strobe signal generation circuit 220, according to one embodiment of the present invention.
In the case where the memory device 130 is a double data transfer rate memory, the driven memory device 130 transmits the data signal DQ and the data strobe signal DQs to the data reading circuit 230. In such a case, the true data strobe signal generation circuit 220 is configured to generate the true data strobe signal TDQS, such that the selection circuit 240 operating in the double data transfer rate mode selects the true data strobe signal TDQS as the sampling signal SS.
As shown in fig. 4, the true data strobe signal generation circuit 220 will delay the read enable signal REN, thereby generating a delayed read enable signal REND. The enable section SEN in the read enable signal REN will also be delayed accordingly and used to enable the output data strobe signal DQS. In detail, the true data strobe signal generating circuit 220 will cause the data strobe signal DQS to be output at the portion of the corresponding enable section SEN as the true data strobe signal TDQS.
In one embodiment, the start timing TT1 of the true data strobe signal TDQS corresponds to the arrival timing TT2 of the memory device 130 transmitting the data strobe signal DQS to the true data strobe signal generating circuit 220.
In detail, when the memory access interface device 120 performs a read operation on the memory device 130, the required time includes the time when the command signal CMD and the address signal ADD of fig. 1 are transmitted to the memory device 130 via the transmitter TX of the memory access interface device 120, the time when the memory device 130 generates the data strobe signal DQS through processing, and the time when the memory device 130 transmits the data strobe signal DQS to the true data strobe signal generating circuit 220 via lines.
Therefore, the time required for the true data strobe signal generation circuit 220 to delay the read enable signal REN corresponds to the total time of the above-described operations.
It should be noted that the term "corresponding" refers to that the timings of the two may have a difference within an allowable range without causing an error in the access operation, and are not necessarily completely equal.
As shown in fig. 4, the data strobe signal DQS may include a tri-state section TS1 before the leading section PRA and a tri-state section TS2 after the trailing section POA. Since the leading segment PRA and the trailing segment POA are relatively short (such as, but not limited to, a length of one cycle or two cycles, respectively), the read enable signal REN provides a gating mechanism to accurately erase the tri-state segments TS1 and TS2 to output the clean true data strobe signal TDQS. Such a design will avoid unstable signal drift due to process, voltage and temperature variations.
In one embodiment, the time length TL of the enable section SEN of the read enable signal REN corresponding to the true data strobe signal generation circuit 220 corresponds to the total time length TTL of the leading section PRA, the strobe section STS and the trailing section POA of the data strobe signal DQS.
In an embodiment, since the data strobe signal DQS is configured to sample the data signal DQ, the data strobe signal DQS corresponds to a timing of the data signal DQ, and a time length of the strobe section STS of the data strobe signal DQS also corresponds to a data length DL of the data signal DQ. Therefore, the true data strobe signal TDQS generated in the above manner will also have a corresponding timing and strobe section STS of the same time length. In the example of FIG. 4, the data signals DQ include eight data DA DH and the strobe block STS has four sampling periods. The selection circuit 240 selects the true data strobe signal TDQS as the sampling signal SS, and then causes the data reading circuit 230 to sample the data DA to DH according to the sampling signal SS.
Similarly, the term "corresponding" refers to that the time length TL and the data length DL may have a difference within an allowable range without causing an error in the access operation, and are not necessarily completely equal.
In one embodiment, the data reading circuit 230 may include a read data receiving circuit 232, a read data FIFO circuit 234, a read calibration circuit 236, and a read data selection circuit 238 that operate according to, for example, but not limited to, the reference clock signal CMDCLK.
The read data receiving circuit 232 is configured to sample the data signal DQ according to the sampling signal SS. The read data FIFO circuit 234 is configured to perform clock domain (clock domain) conversion on the data sampled by the read data receiving circuit 232 to generate a read data signal RDQ.
In one embodiment, the clock domain switching is used to switch the clock domain of the data between the read data receiving circuit 232 and the memory access controller 110.
The read calibration circuit 236 is configured to operate on the data stored in the read data FIFO 234 according to a predetermined calibration algorithm and generate a feedback calibration signal (not shown) to the read data receiving circuit 222.
In the single data transfer rate mode, the data reading circuit 230 is configured to sample the data signal DQ according to two edges of each sampling period of the sampling signal SS, thereby generating two sampling results. The read data selection circuit 238 selects one of the two sampling results to output according to the timing relationship between the sampling signal SS and the data signal DQ, and generates a read data signal RDQ.
Please refer to fig. 5. Fig. 5 is a schematic diagram illustrating a timing relationship between a data signal DQ and a sampling signal SS according to an embodiment of the invention.
As shown in FIG. 5, the timing relationship between the data signal DQ and the sampling signal SS includes conditions 500, 510, and 520.
In the situation 500, the negative terminal 530 of the sampling signal SS is located between the transition states (transition states) of the two data DA and DB, which is prone to cause sampling errors. Thus, the read data selection circuit 238 outputs the sampling result of the positive terminal 540 that selects the sampling signal SS in the condition 500 to generate the read data signal RDQ.
In the condition 510, the positive terminal 540 of the sampling signal SS is located between the two transition states of the data DA and DB, which is prone to sampling errors. Accordingly, the read data selection circuit 238 outputs the sampling result of the negative terminal 530 that selects the sampling signal SS in the condition 500 to generate the read data signal RDQ.
In case 520, both the negative terminal 530 and the positive terminal 540 of the sampled signal SS may be sampled with data. Therefore, the read data selection circuit 238 can arbitrarily select the sampling result of one of the negative terminal 530 and the positive terminal 540 for output to generate the read data signal RDQ.
It should be noted that the timing relationship between the data signal DQ and the sampling signal SS can be obtained by firstly performing a test procedure in advance to sample the data signal DQ to be tested by the sampling signal SS and observing the sampling result, so as to set the data selection circuit 238, and enable the data selection circuit 238 to select the sampling result of one of the negative terminal 530 and the positive terminal 540 of the sampling signal SS for output in the manner described above during actual operation.
On the other hand, in the double data transfer rate mode, the data reading circuit 230 is configured to sample the data signal DQ according to two edges of each sampling period of the sampling signal SS to generate two sampling results. The read data selection circuit 238 bypasses (bypass) the two sampling results to generate the read data signal RDQ.
It should be noted that the above-mentioned embodiments are only examples. In other embodiments, modifications and variations can be made by one skilled in the art without departing from the spirit of the invention.
In summary, the memory system and the memory access interface device thereof of the present invention can achieve the access of the memory device with accurate timing in a low cost manner no matter whether the memory device is a single data transfer rate memory or a double data transfer rate memory.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents explicitly or implicitly included in the present invention, which may fall into the scope of the patent protection claimed in the present invention.
Description of reference numerals:
100: memory system
110: memory access controller
120: memory access interface device
130: memory device
200: clock generation circuit
205A: clock source circuit
205B: frequency eliminating circuit
210: pseudo data strobe signal generating circuit
220: true data strobe signal generating circuit
230: data reading circuit
232: read data receiving circuit
234: read data FIFO circuit
236: read correction circuit
238: read data selection circuit
240: selection circuit
500. 510, 520: condition of the condition
530: negative terminal
540: positive terminal
ADD: address signal access instruction
CMDCLK: reference clock signal
CMD: instruction signal
DA to DH: data of
DL: data length
DQ: data signal
DQS: data strobe signal
FDQS: dummy data strobe signal
POA: rear guide section
PRA: leading segment
RDQ: reading data signals
REN: read enable signal
REND: delayed read enable signal
RX: receiver with a phase locked loop
And SCLK: source clock signal
SEN: enable segment
STS: gated section
And SS: sampling signal
TDQS: true data strobe signal
TF1, TT1: start timing
TF2, TT2: arrival timing
TS1, TS2: three state section
TL: length of time
TTL: total length of time
TX: conveyor

Claims (10)

1. A memory access interface device, comprising:
a clock generation circuit configured to generate a reference clock signal;
a dummy data strobe signal generation circuit configured to receive the reference clock signal and delay a read enable signal from a memory access controller to enable output of the reference clock signal according to an enable section of the read enable signal, thereby generating a dummy data strobe signal;
a true data strobe signal generating circuit configured to receive a data strobe signal from a memory device and delay the read enable signal to enable output of the data strobe signal according to the enable section of the read enable signal to generate a true data strobe signal;
a data read circuit configured to sample a data signal from the memory device according to a sampling signal, generate and transmit a read data signal to the memory access controller; and
a selection circuit configured to select the dummy data strobe signal as the sampling signal in a single data transfer rate mode and the true data strobe signal as the sampling signal in a double data transfer rate mode.
2. The memory access interface device of claim 1, further comprising a receiver, wherein the clock generation circuit, the dummy data strobe signal generation circuit, the true data strobe signal generation circuit, the data read circuit, and the selection circuit are disposed in the receiver, and a transmitter configured to receive a command signal and an address signal from the memory access controller and transmit the command signal and the address signal to the memory device to drive the memory device.
3. The memory access interface device of claim 1, wherein a start timing of the dummy data strobe signal corresponds to an arrival timing of the memory device transmitting the data signal to the data read circuit;
the start timing of the true data strobe signal corresponds to the arrival timing of the memory device transmitting the data strobe signal to the true data strobe signal generating circuit;
a time length of the enable section of the read enable signal corresponding to the dummy data strobe signal generation circuit corresponds to a data length of the data signal;
the time length of the enable section of the read enable signal corresponding to the true data strobe signal generating circuit corresponds to a total time length of a leading section, a strobe section, and a trailing section of the data strobe signal.
4. The memory access interface device of claim 1, wherein in the single data transfer rate mode, the data read circuit is configured to sample the data signal according to two edges of each sampling period of the sampling signal to generate two sampling results, and to select one of the two sampling results for output according to a timing relationship between the sampling signal and the data signal to generate the read data signal; and
in the double data transfer rate mode, the data reading circuit is configured to sample the data signal according to the two edges of each sampling period of the sampling signal to generate the two sampling results and output the two sampling results, so as to generate the read data signal.
5. The memory access interface device of claim 1, wherein the memory device is a single data transfer rate memory or a double data transfer rate memory.
6. A memory system, comprising:
a memory access controller;
a memory device; and
a memory access interface device, comprising:
a clock generation circuit configured to generate a reference clock signal;
a pseudo data strobe signal generating circuit configured to receive the reference clock signal and delay a read enable signal from the memory access controller to enable output of the reference clock signal according to an enable section of the read enable signal, thereby generating a pseudo data strobe signal;
a true data strobe signal generating circuit configured to receive a data strobe signal from the memory device and delay the read enable signal to enable output of the data strobe signal according to the enable section of the read enable signal to generate a true data strobe signal;
a data read circuit configured to sample a data signal from the memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller; and
a selection circuit configured to select the dummy data strobe signal as the sampling signal in a single data transfer rate mode and the true data strobe signal as the sampling signal in a double data transfer rate mode.
7. The memory system of claim 6, wherein the memory access interface device further comprises a receiver and a transmitter, the clock generation circuit, the dummy data strobe signal generation circuit, the true data strobe signal generation circuit, the data read circuit, and the selection circuit are disposed in the receiver, and the transmitter is configured to receive a command signal and an address signal from the memory access controller and transmit the command signal and the address signal to the memory device to drive the memory device.
8. The memory system of claim 6 wherein a start timing of the dummy data strobe signal corresponds to an arrival timing of the memory device transferring the data signal to the data read circuit;
the true data strobe signal corresponds to the timing at which the memory device transmits the data strobe signal to the true data strobe signal generating circuit, respectively;
the start timing of the true data strobe signal corresponds to the arrival timing of the memory device transmitting the data strobe signal to the true data strobe signal generation circuit;
the time length of the enable section of the read enable signal corresponding to the true data strobe signal generating circuit corresponds to a total time length of a leading section, a strobe section, and a trailing section of the data strobe signal.
9. The memory system of claim 6, wherein in the single data transfer rate mode, the data read circuit is configured to sample the data signal according to two edges of each sampling period of the sampling signal to generate two sampling results, and to select one of the two sampling results according to a timing relationship of the sampling signal and the data signal to generate the read data signal; and
in the double data transfer rate mode, the data read circuit is configured to sample the data signal according to the two edges of each of the sampling periods of the sampling signal to generate the two sampling results, thereby generating the read data signal.
10. The memory system of claim 6 wherein the memory device is a single data transfer rate memory or a double data transfer rate memory.
CN202110807461.XA 2021-07-16 2021-07-16 Memory system and memory access interface device thereof Pending CN115620762A (en)

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CN202110807461.XA CN115620762A (en) 2021-07-16 2021-07-16 Memory system and memory access interface device thereof

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Application Number Priority Date Filing Date Title
CN202110807461.XA CN115620762A (en) 2021-07-16 2021-07-16 Memory system and memory access interface device thereof

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