GB2234372A - Mass memory device - Google Patents

Abstract

A controller (12) emits commands (CMND) to a chain of memory modules. Write data may be sent to a selected module on a line (XMIT) which has a one-clock delay through each module. Read data is received from a selected module on a line (RECV) which also has a one-clock delay through each module. To synchronise commands with data they are sent (DCMND) Figure 2 to the modules through a variable delay (30) such as a FIFO which is set (DN) by the controller to a delay N.t where the N'th module is commanded and t is the clock period. Read data is gated in by a command (DDCMND) delayed by N.t. again by a second variable delay (32), Figure 3. A less complex management schedule may be implemented using the controller and mass memory described to ensure that all valid data, but no invalid data, are written or read. <IMAGE>

Description

#s #y DEVICE The present invention relates to a mass memory device comprising a controller and a chain of memory modules to which and from which the controller sends and receives write and read data respectively via a transmit (XMIT) line and receive (RECV) line respectively, each of which lines includes a synchronous delay through each module established by clock pulses distributed to all modules, the controller being further connected without substantial delay to all modules via a command line and each module being responsive to signals sent thereto on the command line, in conjunction with signals on the transmit line, to assume selected states, including write-addressed and read-addressed states and responsive in these latter states to a start/stop command on the command line to toggle between writing or reading data, as the case may be and not writing or reading data.

Such a device is disclosed in our copending British Patent Application 8903181.9 (Ref. 1) and further information is to be found in GB-A 2 177 825 (Ref.2).

Although the invention is described in terms of single, bitserial XMIT and RECV lines, these lines could be replicated to carry a plurality of bits in parallel within the scope of the invention.

The chain of modules may be soft-configured as described in various references, including those already mentioned above and GB-A 1 337 859 (Ref.3) for example. The chain could equally well, within the scope of the present invention, be hard configured.

In a device of the kind described the controller is analogous to a disc controller and acts between a host computer and the memory constituted by the memory modules. The controller is accordingly required to command selected modules and access selected addresses therein for write or read purposes. With a device of the kind described most accesses will consist in writing or reading a substantial block of data.

It is not possible to ensure that the data transfer rates of the memory device and host computer can be matched and it is well known that there must be the ability to interrupt data transfers and restart them again. This may occur several times in the transfer of a complete block of data, whether during reading or writing. It is for this purpose that the stop/starL command is provided to toggle between writing or reading and not writing or reading. This start/stop oammand may be designated STSP.As described in Ref.2, different ccarmands may be distinguished by different durations, each command becoming effective when it terminates and the receiving modules accordingly know the duration of the A problem arises in that STSP acts instantaneously whereas data propagating to or from the N'th module experiences a variable delay of N times the synchronous delay per module, which may be just one clock period. When a decision is taken to stop data transfer, allowance must be made for the segment of data still propagating in the chain to or from the addressed module. Particularly in the case of remote modules, e.g.N in excess of 100, there may be a plurality of valid data segments propagating in the chain with intervening "holes" or invalid data segments.

Accordingly the controller has to implement a fairly complex management schedule in respect of STSP in order to ensure that all valid data, but no invalid data, is written or read. The object of the present invention is to improve the controller so as to simplify management very considerably.

According to the present invention in one aspect, in a mass memory device of the type initially defined, the controller comprises a delay device with a variable delay though which command signals are issued to the command line and means for adjusting this delay N.t to when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal at the N'th module synchronous with the beginnings and ends of valid data segments sent thereto via the transmit (XMIT) line, where t is the synchronous delay through a module.

There are N-l modules between the controller and the addressed module. The required delay may be Nt or (N-l)t, or even an intermediate value if t is more than one clock period, depending on detailed implementation. Hence the foregoing reference to "Nt or such approximation thereto...." According to the present invention in another aspect, in a mass memory device of the type initially defined, the controller comprises a delay device with a variable delay though which command signals issued to the command line are returned to the controller to control input of data to the controller from the receive line and means for adjusting this delay to N.t when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal returned to the controller synchronous with the beginnings and ends of valid data segments sent thereto via the receive (RECV) line, from the N'th module, where t is the synchronous delay through a module.

When a module is read-addressed it would be possible to send commands without delay to the command line and only to delay the returned oommand signals. However it is preferred to provide a first variable delay through which all commands are issued to the aamrrand line and a second variable delay which has its input connected to the output of the first delay line and through which the returned command signals pass.

The or each variable delay is conveniently implemented by means of a variable length FIFO device since such devices are readily available and well known as variable delays.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which Fig. 1 is a block circuit diagram of a mass memory device in which the present invention may be embodied, Fig. 2 is a block circuit diagram of an embodiment for use in write operations, Fig. 3 is a block circuit diagram of an embodiment for use in read operations, Fig. 4 shows a combined read/write embodiment, Fig. 5 is a more detailed diagram of an embodiment for use in read and write operations, and Fig. 6 shows explanatory waveforms.

Fig. 1 shows a host computer 10 connected to a controller 12 via a bus 14, which may be a conventional bus such as the SCSI bus.

The controller 12 responds to camnands from the host computer 10 to effect read and write operations in a mass memory formed by a chain of memory modules MODULE 1, 2 Z. Each module may be based on a DRAM, e.g. a ambit DRAM or larger and there may be a hundred modules or more, e.g. Z = 160. Although Fig.1 illustrates a configured chain in schematic manner it will be appreciated that the chain may actually be configured under software control, being grown module by module through good modules on a wafer zmplementing the mass memory by wafer scale integration. See the references mentioned above.

Communication through the chain is via an outgoing or transmit data line XMIT and an inooming or receive data line RECV which are, in this embodiment, simply bit-serial lines. The controller 12 also oommunicates to all modules via two "global" signals, namely a clock signal WCK (wafer clock) and a command signal CMND. Different oamnands are distinguished by the length of a command signal asserted on CMND.

The The main components of one memory module are shown in very simplified manner in MDDUIE 2 in Fig. 1. The XMIT and RECV lines include single bit buffers 16 and 18 respectively which are clocked by WCK and moreover represent the means of input and output communication respectively with a DRAM unit 20 and a control unit 22. The buffers 16 and 18 establish a synchronous delay through each module of one clock period. Although the present invention is not concerned with the details of the memory modules, sufficient description of these will be given to ensure that the subject matter of the invention is fully comprehensible.

The basic technique of comanding the modules relies upon clocking a bit along a shift register whenever CMND is asserted and latching the bit in a flip-flop when CMND terminates. Since different commands are distinguished by different lengths of CMND the different commands correspond to different ones of a set of flip-flop latches. However, as explained in Ref. 2, some commands are "global" contends which affect all modules unconditionally.

Other commands are "local" corrrnands which affect one module only because they require coincident arrival at the module via XMIT of a token bit. Thus a local command is asserted at module N by launching a token bit from the controller 12, waiting N clock periods and then asserting CMND, with the undertstanding that CMND is asserted at the end of the command signal.

moreover (Ref.1) the token bit stays "parked" at the N'th module and certain ccmnEnds, called "primed" ccamands are operative only at the module with the parked bit. They are thus local in effect but do not require a token bit to be sent via XMIT as do true local commands. The following Table is derived from Ref. 1 and gives one possible set of catitinds.

TABLE I Duration Name Action Global: CMND=01: INIT - reset the wafer to a known state, used after initial power up.

Primed: Q#t#02: AOONE - set address counter bit to logical one, used to initiate start address value for read or write (requires chip to be in address counter load mode as a consequence of executing a local AcLoAD function before the first ATONE function). The MSB of the address counter is loaded first in any load sequence.

Primed: CMNDt03: ACZERO - as for ATONE, setting address counter bit to zero.

Primed: CMND=04: TRP - trigger a memory row pre-charge sequence during read or write (requires chip to be in read or write mode as a consequence of executing a local READ or WRITE function before the first TRP function).

Primed: CMND=05: STSP - start or stop data transfer if in read or write mode (requires chip to be in read or write mode as a consequence of executing a local READ or WRITE function before the first STSP function). This is a toggling function, set initially to STOP by UNIT. After INIT any successive STSP function will alternatelyassert and negate the START state (STOP is NOT START). STSP requires the presence of a parked token.

Global: AND=06: CLR SEL - Resets value in SELECTION REGISTER to logical zero. This register selects the direction to the next module in the chain, see SELN etc. below.

Global: CMND=07: CLR - Clears any parked tokens.

Global: CMND=08: CT;P FUN - Resets value in FUNCTION REGISTER to logical zero. This register selects the functions READ, WRITE, ACLUAD.

local: CMNDF09: SEEN - Select the northern exit direction of the XMIT path fram addressed chip in the SELECTION REGISTER.

local: AND=10: SEEE - Select the eastern exit direction of the 2MIT path from addressed chip.

local: CMND=ll: SEES - Select the southern exit direction of the XMIT path from addressed chip.

local: CMND=12: SEEN - Select the western exit direction of the XMIT path fram addressed chip.

SEEN to SEEW also select the appropriate entry direction for the RECV path into the addressed chip, all as described in Ref.2.

local: CMND=13: READ - Selects READ mode for data transfer from memory.

local: CMND=14: WRITE - Selects WRITE mode for data transfer into memory.

local: CMND15: ACLOAD - Selects address counter load mode.

local: CMND=16: SCR - Resets SKEW COUNTER (contained-in addressed chip) to logical zero.

local: CMND17: SCLEN - Selects length of SKEW COUNTER.

local: CMND=18: RPON - Toggles RAM PCWER-ON LATCH (RPON). RPON set to zero by INIT.

The last three commands c#ims will not be considered further herein. Each chip has a free running refresh address counter (separate from the read/write address counter described below) for effecting DRAM refresh. The skew counters are used to stagger the refresh cycles of the chips so as to even out power supply demands, as explained in GB 2 178 204, which also describes the use of RPON.

The commands of interest in the present invention are as follows. To read or write data it is firstly necessary to set an address counter in the memory unit 20 of the selected module to the desired start address. This is done by the local command ACLOAD followed by the appropriate sequence of ACONE and ACZERO primed ccmmerds. The local command READ or WRITE must then be asserted, followed by the primed command STSP to start and stop reading or writing as required. This merely involves starting and stopping the address counter in the memory unit 20.When the counter is running, the bits successively present in the one-bit buffer 16 are read into the successively addressed DRAM locations in write mode or bits from successively addressed DRAM locations are read into the one bit buffer 18 in read mode.

Fig. 2 shows an embodiment for use in the transmit or WRITE mode. It is assumed that the controller 12 has already set module N into write mode, using a token bit and CMND in accordance with the prior art. It is now necessary to send the data to be written on XMIT and to issue CMND with a duration of five clock periods, i.e.

the command STSP, to start the writing operation at module N. It will be seen from Fig. 2 that CMND is not applied directly to all the modules but by way of a variable delay 30 whose output is denoted DCMND, i.e. CMND delayed. The controller 12 also applies a control signal DN to the variable delay 30 to set the delay thereof to N clock periods. Referring to Fig.6 an example of operation of the invention is shown for the case in which N equals 15. Waveform A shows CMND equals STSP, i.e. CMND 5 clock periods long, terminating at reference time To.It will be recalled fran Ref. 1 and Ref.2 that the decoding of CMND at a module depends upon the length of CMND which is therefore operative at the end of the waveform. Hence the assignment of time to to the end of CMND in waveform A. The controller also starts to send the data to be written, oommencing at time to as shown in waveform C. However this data does not start to arrive at the fifteenth module until time tl5, as shown in waveform D.However, since DCMND (waveform B) is delayed fifteen clock periods relative to CMND by the variable delay 30, DCMND terminates at time t15 and thereby issues the STSP command to the fifteenth module at precisely the right time for this module to commence writing the transmitted data D. Although not illustrated, the next issuance of CMND equals STSP will be with its trailing edge coincident with the end of the XMIT data so that the fifteenth module will be switched off writing in correct synchronism with the termination of the WRITE data.

Fig. 3 shows an embodiment for use in the READ or TRANSMIT mode in which the Nth module is assumed to have been set in READ mode in accordance with the prior art and will start to read out data to RECV on receipt of STSP. In this embodiment it will be seen that CMND is applied direct to the modules but a variable delay 32 controlled by DN is used to return DCMND to the controller 12 in order to control the reception of the READ data at the controller.

This is symbolised by the showing of an AND gate 34 to which RECV is applied and which is enabled by a flipflop 36 toggled by DCMND.

In this embodiment, CMND is immediately effected at the modules and the fifteenth module accordingly starts to read out RECD data at time to. However this does not reach the controller 12 until t15 but the controller does not start to acknowledge RECV data until the AND gate 34 is enabled by the flip-flop 36 which is toggled on by DCMND. Referring to Fig.6 the end of DCMND is synchronous with the start of the RECV data at the controller shown in waveform F.

A complete embodiment of the invention could include circuitry for switching between the WRITE and READ configurations of Fig.2 and Fig. 3 respectively. However it is much preferred to combine the two configurations as shown in Fig.4 where DCMND, provided by the variable delay 30, is always applied to the modules and the command fed back to the controller 12 to control the acknowledgment of RECV data is a doubly delayed command DDCMND provided by the variable delay 32, now connected to the output of the variable delay 30.

Fig.6 shows DDCMND in broken lines in waveform B, terminating at t30, which is when the RECV data from the fifteenth module (waveform G) starts to reach the controller 12.

The variable delays 30 and 32 are preferably implemented as FIFOs which are well known means of implementing variable delays.

Two bit channels of an 8-bit wide FIFO 40 may be employed (Fig.5).

The FIFO 40 is of the type having separately clocked inputs and outputs. The controller 12 includes a counter 42 which is set to the value N. When the controller is initialising the FIFO 40 to a new value of N it clears the FIFO in known manner and then starts to apply a clock signal WCK' directly to the WRITE control input of the FIFO. WCK' is also applied through a gate 44 to count down the counter 42. When the counter reaches zero the gate 44 blocks the passage of further clock pulses to the counter. A ccarplementary gate 46 enables the passage of clock pulses to the READ control input of the FIFO 40. Thus, when the counter reaches zero, both READ and WRITE are applied to the FIFO in synchronism, formed from the WCK' signal. The FIFO is accordingly set to a delay time of N clock pulses.

Claims (4)

CLAIMS:

1. A mass memory device comprising a controller and a chain of memory modules to which and from which the controller sends and receives write and read data respectively via a transmit (XMIT) line and receive (RECV) line respectively, each of which lines includes a synchronous delay through each module established by clock pulses distributed to all modules, the controller being further connected without substantial delay to all modules via a aammand line and each module being responsive to signals sent thereto on the command line, in conjunction with signals on the transmit line, to assume selected states, including write-addressed and read-addressed states and responsive in these latter states to a start/stop camnand on the asmmand line to toggle between writing or reading data, as the case may be and not writing or reading data, characterized in that the controller comprises a delay device with a variable delay though which command signals are issued to the ccmmand line and means for adjusting this delay to N.t when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal at the N'th module synchronous with the beginnings and ends of valid data segments sent thereto via the transmit (XMIT) line, where t is the synchronous delay through a module.

2. A mass memory device comprising a controller and a chain of memory modules to which and fram which the controller sends and receives write and read data respectively via a transmit (XMIT) line and receive (RECV) line respectively, each of which lines includes a synchronous delay through each module established by clock pulses distributed to all modules, the controller being further connected without substantial delay to all modules via a command line and each module being responsive to signals sent thereto on the aammand line, in conjunction with signals on the transmit line, to assume selected states, including writeaddressed and read-addressed states and responsive in these latter states to a start/stop asmmandon the asnmand line to toggle between writing or reading data, as the case may be and not writing or reading data, characterized in that the controller comprises a delay device with a variable delay though which command signals issued to the oomaand line are returned to the controller to control input of data to the controller fram the receive line and means for adjusting this delay to N.t when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal returned to the controller synchronous with the beginnings and ends of valid data segments sent thereto via the receive (RECV) line, fran the N'th module, where t is the synchronous delay through a module.

3. A mass memory device comprising a controller and a chain of memDryamodules to which and from which the controller sends and receives write and read data respectively via a transmit (XMIT) line and receive (RECV) line respectively, each of which lines includes a synchronous delay through each module established by clock pulses distributed to all modules, the controller being further connected without substantial delay to all modules via a command line and each module being responsive to signals sent thereto on the ccmmand line, in conjunction with signals on the transmit line, to assume selected states, including write-addressed and read-addressed states and responsive in these latter states to a start/stop command on the command line to toggle between writing or reading data, as the case may be and not writing or reading data, characterized in that the controller comprises a first delay device with a variable delay though which command signals are issued to the command line and means for adjusting this delay to N.t when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal at the N'th module synchronous with the beginnings and ends of valid data segments sent thereto via the transmit (XMIT) line, where t is the synchronous delay through a module and a second delay device with a variable delay though which command signals issued to the command line are returned to the controller to control input of data to the controller fran the receive line and means for adjusting this delay to N.t when addressing the N'th memory module or such approximation thereto as will render the action of the start/stop signal returned to the controller synchronous with the beginnings and ends of valid data segments sent thereto via the receive (RECV) line, fram the N'th module, where t is the synchronous delay through a module.

4. A mass memory device according to claim 1, 2 or 3, wherein the or each variable delay comprises a FIFO controlled to provide the delay N.t.